iris: hook up batch decoder
[mesa.git] / src / gallium / drivers / iris / iris_batch.h
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef IRIS_BATCH_DOT_H
25 #define IRIS_BATCH_DOT_H
26
27 #include <stdint.h>
28 #include <stdbool.h>
29 #include "common/gen_decoder.h"
30
31 /* The kernel assumes batchbuffers are smaller than 256kB. */
32 #define MAX_BATCH_SIZE (256 * 1024)
33
34 /* 3DSTATE_BINDING_TABLE_POINTERS has a U16 offset from Surface State Base
35 * Address, which means that we can't put binding tables beyond 64kB. This
36 * effectively limits the maximum statebuffer size to 64kB.
37 */
38 #define MAX_STATE_SIZE (64 * 1024)
39
40 struct iris_address {
41 struct iris_bo *bo;
42 uint64_t offset;
43 bool write;
44 };
45
46 struct iris_batch_buffer {
47 struct iris_bo *bo;
48 void *map;
49 void *map_next;
50
51 struct iris_bo *partial_bo;
52 unsigned partial_bytes;
53 };
54
55 struct iris_batch {
56 struct iris_screen *screen;
57 struct pipe_debug_callback *dbg;
58
59 /** Current batchbuffer being queued up. */
60 struct iris_batch_buffer cmdbuf;
61
62 /** Last BO submitted to the hardware. Used for glFinish(). */
63 struct iris_bo *last_cmd_bo;
64
65 uint32_t hw_ctx_id;
66
67 /** Which ring this batch targets - a I915_EXEC_RING_MASK value */
68 uint8_t ring;
69
70 bool no_wrap;
71
72 /** The validation list */
73 struct drm_i915_gem_exec_object2 *validation_list;
74 struct iris_bo **exec_bos;
75 int exec_count;
76 int exec_array_size;
77
78 /** The amount of aperture space (in bytes) used by all exec_bos */
79 int aperture_space;
80
81 #if DEBUG
82 /** Map from batch offset to iris_alloc_state data (with DEBUG_BATCH) */
83 // XXX: unused
84 struct hash_table *state_sizes;
85 struct gen_batch_decode_ctx decoder;
86 #endif
87
88 void (*emit_state_base_address)(struct iris_batch *batch);
89 };
90
91 void iris_init_batch(struct iris_batch *batch,
92 struct iris_screen *screen,
93 struct pipe_debug_callback *dbg,
94 uint8_t ring);
95 void iris_batch_free(struct iris_batch *batch);
96 void iris_require_command_space(struct iris_batch *batch, unsigned size);
97 void iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size);
98
99 int _iris_batch_flush_fence(struct iris_batch *batch,
100 int in_fence_fd, int *out_fence_fd,
101 const char *file, int line);
102
103
104 #define iris_batch_flush_fence(batch, in_fence_fd, out_fence_fd) \
105 _iris_batch_flush_fence((batch), (in_fence_fd), (out_fence_fd), \
106 __FILE__, __LINE__)
107
108 #define iris_batch_flush(batch) iris_batch_flush_fence((batch), -1, NULL)
109
110 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
111
112 #define RELOC_WRITE EXEC_OBJECT_WRITE
113
114 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
115 bool writable);
116
117 #endif