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24 #ifndef IRIS_BATCH_DOT_H
25 #define IRIS_BATCH_DOT_H
31 #include "util/u_dynarray.h"
33 #include "drm-uapi/i915_drm.h"
34 #include "common/gen_decoder.h"
36 #include "iris_fence.h"
37 #include "iris_fine_fence.h"
41 /* The kernel assumes batchbuffers are smaller than 256kB. */
42 #define MAX_BATCH_SIZE (256 * 1024)
44 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
45 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus another
46 * 24 bytes for the seqno write (using PIPE_CONTROL).
48 #define BATCH_RESERVED 36
50 /* Our target batch size - flush approximately at this point. */
51 #define BATCH_SZ (64 * 1024 - BATCH_RESERVED)
53 enum iris_batch_name
{
58 #define IRIS_BATCH_COUNT 2
61 struct iris_screen
*screen
;
62 struct pipe_debug_callback
*dbg
;
63 struct pipe_device_reset_callback
*reset
;
65 /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
66 enum iris_batch_name name
;
68 /** Current batchbuffer being queued up. */
73 /** Size of the primary batch being submitted to execbuf (in bytes). */
74 unsigned primary_batch_size
;
76 /** Total size of all chained batches (in bytes). */
77 unsigned total_chained_batch_size
;
79 /** Last Surface State Base Address set in this hardware context. */
80 uint64_t last_surface_base_address
;
84 /** The validation list */
85 struct drm_i915_gem_exec_object2
*validation_list
;
86 struct iris_bo
**exec_bos
;
90 /** Whether INTEL_BLACKHOLE_RENDER is enabled in the batch (aka first
91 * instruction is a MI_BATCH_BUFFER_END).
96 * A list of iris_syncobjs associated with this batch.
98 * The first list entry will always be a signalling sync-point, indicating
99 * that this batch has completed. The others are likely to be sync-points
100 * to wait on before executing the batch.
102 struct util_dynarray syncobjs
;
104 /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
105 struct util_dynarray exec_fences
;
107 /** The amount of aperture space (in bytes) used by all exec_bos */
111 /** Uploader to use for sequence numbers */
112 struct u_upload_mgr
*uploader
;
114 /** GPU buffer and CPU map where our seqno's will be written. */
115 struct iris_state_ref ref
;
118 /** The sequence number to write the next time we add a fence. */
122 /** A seqno (and syncobj) for the last batch that was submitted. */
123 struct iris_fine_fence
*last_fence
;
125 /** List of other batches which we might need to flush to use a BO */
126 struct iris_batch
*other_batches
[IRIS_BATCH_COUNT
- 1];
130 * Set of struct brw_bo * that have been rendered to within this
131 * batchbuffer and would need flushing before being used from another
132 * cache domain that isn't coherent with it (i.e. the sampler).
134 struct hash_table
*render
;
137 struct gen_batch_decode_ctx decoder
;
138 struct hash_table_u64
*state_sizes
;
141 * Matrix representation of the cache coherency status of the GPU at the
142 * current end point of the batch. For every i and j,
143 * coherent_seqnos[i][j] denotes the seqno of the most recent flush of
144 * cache domain j visible to cache domain i (which obviously implies that
145 * coherent_seqnos[i][i] is the most recent flush of cache domain i). This
146 * can be used to efficiently determine whether synchronization is
147 * necessary before accessing data from cache domain i if it was previously
148 * accessed from another cache domain j.
150 uint64_t coherent_seqnos
[NUM_IRIS_DOMAINS
][NUM_IRIS_DOMAINS
];
153 * Sequence number used to track the completion of any subsequent memory
154 * operations in the batch until the next sync boundary.
158 /** Have we emitted any draw calls to this batch? */
161 /** Have we emitted any draw calls with next_seqno? */
162 bool contains_draw_with_next_seqno
;
165 * Number of times iris_batch_sync_region_start() has been called without a
166 * matching iris_batch_sync_region_end() on this batch.
168 uint32_t sync_region_depth
;
170 uint32_t last_aux_map_state
;
173 void iris_init_batch(struct iris_context
*ice
,
174 enum iris_batch_name name
,
176 void iris_chain_to_new_batch(struct iris_batch
*batch
);
177 void iris_batch_free(struct iris_batch
*batch
);
178 void iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
);
180 void _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
);
181 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
183 bool iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
);
185 bool iris_batch_prepare_noop(struct iris_batch
*batch
, bool noop_enable
);
187 #define RELOC_WRITE EXEC_OBJECT_WRITE
189 void iris_use_pinned_bo(struct iris_batch
*batch
, struct iris_bo
*bo
,
190 bool writable
, enum iris_domain access
);
192 enum pipe_reset_status
iris_batch_check_for_reset(struct iris_batch
*batch
);
194 static inline unsigned
195 iris_batch_bytes_used(struct iris_batch
*batch
)
197 return batch
->map_next
- batch
->map
;
201 * Ensure the current command buffer has \param size bytes of space
202 * remaining. If not, this creates a secondary batch buffer and emits
203 * a jump from the primary batch to the start of the secondary.
205 * Most callers want iris_get_command_space() instead.
208 iris_require_command_space(struct iris_batch
*batch
, unsigned size
)
210 const unsigned required_bytes
= iris_batch_bytes_used(batch
) + size
;
212 if (required_bytes
>= BATCH_SZ
) {
213 iris_chain_to_new_batch(batch
);
218 * Allocate space in the current command buffer, and return a pointer
219 * to the mapped area so the caller can write commands there.
221 * This should be called whenever emitting commands.
224 iris_get_command_space(struct iris_batch
*batch
, unsigned bytes
)
226 iris_require_command_space(batch
, bytes
);
227 void *map
= batch
->map_next
;
228 batch
->map_next
+= bytes
;
233 * Helper to emit GPU commands - allocates space, copies them there.
236 iris_batch_emit(struct iris_batch
*batch
, const void *data
, unsigned size
)
238 void *map
= iris_get_command_space(batch
, size
);
239 memcpy(map
, data
, size
);
243 * Get a pointer to the batch's signalling syncobj. Does not refcount.
245 static inline struct iris_syncobj
*
246 iris_batch_get_signal_syncobj(struct iris_batch
*batch
)
248 /* The signalling syncobj is the first one in the list. */
249 struct iris_syncobj
*syncobj
=
250 ((struct iris_syncobj
**) util_dynarray_begin(&batch
->syncobjs
))[0];
256 * Take a reference to the batch's signalling syncobj.
258 * Callers can use this to wait for the the current batch under construction
259 * to complete (after flushing it).
262 iris_batch_reference_signal_syncobj(struct iris_batch
*batch
,
263 struct iris_syncobj
**out_syncobj
)
265 struct iris_syncobj
*syncobj
= iris_batch_get_signal_syncobj(batch
);
266 iris_syncobj_reference(batch
->screen
, out_syncobj
, syncobj
);
270 * Record the size of a piece of state for use in INTEL_DEBUG=bat printing.
273 iris_record_state_size(struct hash_table_u64
*ht
,
274 uint32_t offset_from_base
,
278 _mesa_hash_table_u64_insert(ht
, offset_from_base
,
279 (void *)(uintptr_t) size
);
284 * Mark the start of a region in the batch with stable synchronization
285 * sequence number. Any buffer object accessed by the batch buffer only needs
286 * to be marked once (e.g. via iris_bo_bump_seqno()) within a region delimited
287 * by iris_batch_sync_region_start() and iris_batch_sync_region_end().
290 iris_batch_sync_region_start(struct iris_batch
*batch
)
292 batch
->sync_region_depth
++;
296 * Mark the end of a region in the batch with stable synchronization sequence
297 * number. Should be called once after each call to
298 * iris_batch_sync_region_start().
301 iris_batch_sync_region_end(struct iris_batch
*batch
)
303 assert(batch
->sync_region_depth
);
304 batch
->sync_region_depth
--;
308 * Start a new synchronization section at the current point of the batch,
309 * unless disallowed by a previous iris_batch_sync_region_start().
312 iris_batch_sync_boundary(struct iris_batch
*batch
)
314 if (!batch
->sync_region_depth
) {
315 batch
->contains_draw_with_next_seqno
= false;
316 batch
->next_seqno
= p_atomic_inc_return(&batch
->screen
->last_seqno
);
317 assert(batch
->next_seqno
> 0);
322 * Update the cache coherency status of the batch to reflect a flush of the
323 * specified caching domain.
326 iris_batch_mark_flush_sync(struct iris_batch
*batch
,
327 enum iris_domain access
)
329 batch
->coherent_seqnos
[access
][access
] = batch
->next_seqno
- 1;
333 * Update the cache coherency status of the batch to reflect an invalidation
334 * of the specified caching domain. All prior flushes of other caches will be
335 * considered visible to the specified caching domain.
338 iris_batch_mark_invalidate_sync(struct iris_batch
*batch
,
339 enum iris_domain access
)
341 for (unsigned i
= 0; i
< NUM_IRIS_DOMAINS
; i
++)
342 batch
->coherent_seqnos
[access
][i
] = batch
->coherent_seqnos
[i
][i
];
346 * Update the cache coherency status of the batch to reflect a reset. All
347 * previously accessed data can be considered visible to every caching domain
348 * thanks to the kernel's heavyweight flushing at batch buffer boundaries.
351 iris_batch_mark_reset_sync(struct iris_batch
*batch
)
353 for (unsigned i
= 0; i
< NUM_IRIS_DOMAINS
; i
++)
354 for (unsigned j
= 0; j
< NUM_IRIS_DOMAINS
; j
++)
355 batch
->coherent_seqnos
[i
][j
] = batch
->next_seqno
- 1;