src/gallium/drivers/iris/iris_batch.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BATCH_DOT_H
  25 #define IRIS_BATCH_DOT_H
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29 #include <string.h>
  30 #include "i915_drm.h"
  31 #include "common/gen_decoder.h"
  32
  33 /* The kernel assumes batchbuffers are smaller than 256kB. */
  34 #define MAX_BATCH_SIZE (256 * 1024)
  35
  36 /* Our target batch size - flush approximately at this point. */
  37 #define BATCH_SZ (20 * 1024)
  38
  39 #define IRIS_BATCH_COUNT 2
  40
  41 struct iris_address {
  42    struct iris_bo *bo;
  43    uint64_t offset;
  44    bool write;
  45 };
  46
  47 struct iris_batch {
  48    struct iris_screen *screen;
  49    struct iris_vtable *vtbl;
  50    struct pipe_debug_callback *dbg;
  51
  52    /** Current batchbuffer being queued up. */
  53    struct iris_bo *bo;
  54    void *map;
  55    void *map_next;
  56    /** Size of the primary batch if we've moved on to a secondary. */
  57    unsigned primary_batch_size;
  58
  59    /** Last BO submitted to the hardware.  Used for glFinish(). */
  60    struct iris_bo *last_bo;
  61
  62    /** Last Surface State Base Address set in this hardware context. */
  63    uint64_t last_surface_base_address;
  64
  65    uint32_t hw_ctx_id;
  66
  67    /** Which engine this batch targets - a I915_EXEC_RING_MASK value */
  68    uint8_t engine;
  69
  70    /** The validation list */
  71    struct drm_i915_gem_exec_object2 *validation_list;
  72    struct iris_bo **exec_bos;
  73    int exec_count;
  74    int exec_array_size;
  75
  76    /** The amount of aperture space (in bytes) used by all exec_bos */
  77    int aperture_space;
  78
  79    /** List of other batches which we might need to flush to use a BO */
  80    struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
  81
  82    struct {
  83       /**
  84        * Set of struct brw_bo * that have been rendered to within this
  85        * batchbuffer and would need flushing before being used from another
  86        * cache domain that isn't coherent with it (i.e. the sampler).
  87        */
  88       struct hash_table *render;
  89
  90       /**
  91        * Set of struct brw_bo * that have been used as a depth buffer within
  92        * this batchbuffer and would need flushing before being used from
  93        * another cache domain that isn't coherent with it (i.e. the sampler).
  94        */
  95       struct set *depth;
  96    } cache;
  97
  98    /** Map from batch offset to iris_alloc_state data (with DEBUG_BATCH) */
  99    // XXX: unused
 100    struct hash_table *state_sizes;
 101    struct gen_batch_decode_ctx decoder;
 102
 103    /** Have we emitted any draw calls to this batch? */
 104    bool contains_draw;
 105 };
 106
 107 void iris_init_batch(struct iris_batch *batch,
 108                      struct iris_screen *screen,
 109                      struct iris_vtable *vtbl,
 110                      struct pipe_debug_callback *dbg,
 111                      struct iris_batch **other_batches,
 112                      uint8_t ring);
 113 void iris_chain_to_new_batch(struct iris_batch *batch);
 114 void iris_batch_free(struct iris_batch *batch);
 115 void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
 116
 117 int _iris_batch_flush_fence(struct iris_batch *batch,
 118                             int in_fence_fd, int *out_fence_fd,
 119                             const char *file, int line);
 120
 121
 122 #define iris_batch_flush_fence(batch, in_fence_fd, out_fence_fd) \
 123    _iris_batch_flush_fence((batch), (in_fence_fd), (out_fence_fd), \
 124                            __FILE__, __LINE__)
 125
 126 #define iris_batch_flush(batch) iris_batch_flush_fence((batch), -1, NULL)
 127
 128 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
 129
 130 #define RELOC_WRITE EXEC_OBJECT_WRITE
 131
 132 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
 133                         bool writable);
 134
 135 static inline unsigned
 136 iris_batch_bytes_used(struct iris_batch *batch)
 137 {
 138    return batch->map_next - batch->map;
 139 }
 140
 141 /**
 142  * Ensure the current command buffer has \param size bytes of space
 143  * remaining.  If not, this creates a secondary batch buffer and emits
 144  * a jump from the primary batch to the start of the secondary.
 145  *
 146  * Most callers want iris_get_command_space() instead.
 147  */
 148 static inline void
 149 iris_require_command_space(struct iris_batch *batch, unsigned size)
 150 {
 151    const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
 152
 153    if (required_bytes >= BATCH_SZ) {
 154       iris_chain_to_new_batch(batch);
 155    }
 156 }
 157
 158 /**
 159  * Allocate space in the current command buffer, and return a pointer
 160  * to the mapped area so the caller can write commands there.
 161  *
 162  * This should be called whenever emitting commands.
 163  */
 164 static inline void *
 165 iris_get_command_space(struct iris_batch *batch, unsigned bytes)
 166 {
 167    iris_require_command_space(batch, bytes);
 168    void *map = batch->map_next;
 169    batch->map_next += bytes;
 170    return map;
 171 }
 172
 173 /**
 174  * Helper to emit GPU commands - allocates space, copies them there.
 175  */
 176 static inline void
 177 iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
 178 {
 179    void *map = iris_get_command_space(batch, size);
 180    memcpy(map, data, size);
 181 }
 182
 183 #endif