src/gallium/drivers/iris/iris_batch.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BATCH_DOT_H
  25 #define IRIS_BATCH_DOT_H
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29 #include <string.h>
  30
  31 #include "util/u_dynarray.h"
  32
  33 #include "i915_drm.h"
  34 #include "common/gen_decoder.h"
  35
  36 /* The kernel assumes batchbuffers are smaller than 256kB. */
  37 #define MAX_BATCH_SIZE (256 * 1024)
  38
  39 /* Our target batch size - flush approximately at this point. */
  40 #define BATCH_SZ (20 * 1024)
  41
  42 #define IRIS_BATCH_COUNT 2
  43
  44 struct iris_address {
  45    struct iris_bo *bo;
  46    uint64_t offset;
  47    bool write;
  48 };
  49
  50 struct iris_batch {
  51    struct iris_screen *screen;
  52    struct iris_vtable *vtbl;
  53    struct pipe_debug_callback *dbg;
  54
  55    /** The name of this batch for debug info (e.g. "render") */
  56    const char *name;
  57
  58    /** Current batchbuffer being queued up. */
  59    struct iris_bo *bo;
  60    void *map;
  61    void *map_next;
  62    /** Size of the primary batch if we've moved on to a secondary. */
  63    unsigned primary_batch_size;
  64
  65    /** Last Surface State Base Address set in this hardware context. */
  66    uint64_t last_surface_base_address;
  67
  68    uint32_t hw_ctx_id;
  69
  70    /** Which engine this batch targets - a I915_EXEC_RING_MASK value */
  71    uint8_t engine;
  72
  73    /** The validation list */
  74    struct drm_i915_gem_exec_object2 *validation_list;
  75    struct iris_bo **exec_bos;
  76    int exec_count;
  77    int exec_array_size;
  78
  79    /**
  80     * A list of iris_syncpts associated with this batch.
  81     *
  82     * The first list entry will always be a signalling sync-point, indicating
  83     * that this batch has completed.  The others are likely to be sync-points
  84     * to wait on before executing the batch.
  85     */
  86    struct util_dynarray syncpts;
  87
  88    /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
  89    struct util_dynarray exec_fences;
  90
  91    /** The amount of aperture space (in bytes) used by all exec_bos */
  92    int aperture_space;
  93
  94    /** A sync-point for the last batch that was submitted. */
  95    struct iris_syncpt *last_syncpt;
  96
  97    /** List of other batches which we might need to flush to use a BO */
  98    struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
  99
 100    struct {
 101       /**
 102        * Set of struct brw_bo * that have been rendered to within this
 103        * batchbuffer and would need flushing before being used from another
 104        * cache domain that isn't coherent with it (i.e. the sampler).
 105        */
 106       struct hash_table *render;
 107
 108       /**
 109        * Set of struct brw_bo * that have been used as a depth buffer within
 110        * this batchbuffer and would need flushing before being used from
 111        * another cache domain that isn't coherent with it (i.e. the sampler).
 112        */
 113       struct set *depth;
 114    } cache;
 115
 116    /** Map from batch offset to iris_alloc_state data (with DEBUG_BATCH) */
 117    // XXX: unused
 118    struct hash_table *state_sizes;
 119    struct gen_batch_decode_ctx decoder;
 120
 121    /** Have we emitted any draw calls to this batch? */
 122    bool contains_draw;
 123 };
 124
 125 void iris_init_batch(struct iris_batch *batch,
 126                      struct iris_screen *screen,
 127                      struct iris_vtable *vtbl,
 128                      struct pipe_debug_callback *dbg,
 129                      struct iris_batch **other_batches,
 130                      const char *name,
 131                      uint8_t ring);
 132 void iris_chain_to_new_batch(struct iris_batch *batch);
 133 void iris_batch_free(struct iris_batch *batch);
 134 void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
 135
 136 void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
 137 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
 138
 139 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
 140
 141 #define RELOC_WRITE EXEC_OBJECT_WRITE
 142
 143 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
 144                         bool writable);
 145
 146 static inline unsigned
 147 iris_batch_bytes_used(struct iris_batch *batch)
 148 {
 149    return batch->map_next - batch->map;
 150 }
 151
 152 /**
 153  * Ensure the current command buffer has \param size bytes of space
 154  * remaining.  If not, this creates a secondary batch buffer and emits
 155  * a jump from the primary batch to the start of the secondary.
 156  *
 157  * Most callers want iris_get_command_space() instead.
 158  */
 159 static inline void
 160 iris_require_command_space(struct iris_batch *batch, unsigned size)
 161 {
 162    const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
 163
 164    if (required_bytes >= BATCH_SZ) {
 165       iris_chain_to_new_batch(batch);
 166    }
 167 }
 168
 169 /**
 170  * Allocate space in the current command buffer, and return a pointer
 171  * to the mapped area so the caller can write commands there.
 172  *
 173  * This should be called whenever emitting commands.
 174  */
 175 static inline void *
 176 iris_get_command_space(struct iris_batch *batch, unsigned bytes)
 177 {
 178    iris_require_command_space(batch, bytes);
 179    void *map = batch->map_next;
 180    batch->map_next += bytes;
 181    return map;
 182 }
 183
 184 /**
 185  * Helper to emit GPU commands - allocates space, copies them there.
 186  */
 187 static inline void
 188 iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
 189 {
 190    void *map = iris_get_command_space(batch, size);
 191    memcpy(map, data, size);
 192 }
 193
 194 #endif