src/gallium/drivers/iris/iris_batch.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BATCH_DOT_H
  25 #define IRIS_BATCH_DOT_H
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29 #include <string.h>
  30
  31 #include "util/u_dynarray.h"
  32
  33 #include "drm-uapi/i915_drm.h"
  34 #include "common/gen_decoder.h"
  35
  36 #include "iris_fence.h"
  37 #include "iris_seqno.h"
  38
  39 struct iris_context;
  40
  41 /* The kernel assumes batchbuffers are smaller than 256kB. */
  42 #define MAX_BATCH_SIZE (256 * 1024)
  43
  44 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
  45  * or 12 bytes for MI_BATCH_BUFFER_START (when chaining).  Plus another
  46  * 24 bytes for the seqno write (using PIPE_CONTROL).
  47  */
  48 #define BATCH_RESERVED 36
  49
  50 /* Our target batch size - flush approximately at this point. */
  51 #define BATCH_SZ (64 * 1024 - BATCH_RESERVED)
  52
  53 enum iris_batch_name {
  54    IRIS_BATCH_RENDER,
  55    IRIS_BATCH_COMPUTE,
  56 };
  57
  58 #define IRIS_BATCH_COUNT 2
  59
  60 struct iris_address {
  61    struct iris_bo *bo;
  62    uint64_t offset;
  63    bool write;
  64 };
  65
  66 struct iris_batch {
  67    struct iris_screen *screen;
  68    struct pipe_debug_callback *dbg;
  69    struct pipe_device_reset_callback *reset;
  70
  71    /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
  72    enum iris_batch_name name;
  73
  74    /** Current batchbuffer being queued up. */
  75    struct iris_bo *bo;
  76    void *map;
  77    void *map_next;
  78
  79    /** Size of the primary batch being submitted to execbuf (in bytes). */
  80    unsigned primary_batch_size;
  81
  82    /** Total size of all chained batches (in bytes). */
  83    unsigned total_chained_batch_size;
  84
  85    /** Last Surface State Base Address set in this hardware context. */
  86    uint64_t last_surface_base_address;
  87
  88    uint32_t hw_ctx_id;
  89
  90    /** The validation list */
  91    struct drm_i915_gem_exec_object2 *validation_list;
  92    struct iris_bo **exec_bos;
  93    int exec_count;
  94    int exec_array_size;
  95
  96    /** Whether INTEL_BLACKHOLE_RENDER is enabled in the batch (aka first
  97     * instruction is a MI_BATCH_BUFFER_END).
  98     */
  99    bool noop_enabled;
 100
 101    /**
 102     * A list of iris_syncobjs associated with this batch.
 103     *
 104     * The first list entry will always be a signalling sync-point, indicating
 105     * that this batch has completed.  The others are likely to be sync-points
 106     * to wait on before executing the batch.
 107     */
 108    struct util_dynarray syncobjs;
 109
 110    /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
 111    struct util_dynarray exec_fences;
 112
 113    /** The amount of aperture space (in bytes) used by all exec_bos */
 114    int aperture_space;
 115
 116    struct {
 117       /** Uploader to use for sequence numbers */
 118       struct u_upload_mgr *uploader;
 119
 120       /** GPU buffer and CPU map where our seqno's will be written. */
 121       struct iris_state_ref ref;
 122       uint32_t *map;
 123
 124       /** The sequence number to write the next time we add a fence. */
 125       uint32_t next;
 126    } seqno;
 127
 128    /** A seqno (and syncobj) for the last batch that was submitted. */
 129    struct iris_seqno *last_seqno;
 130
 131    /** List of other batches which we might need to flush to use a BO */
 132    struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
 133
 134    struct {
 135       /**
 136        * Set of struct brw_bo * that have been rendered to within this
 137        * batchbuffer and would need flushing before being used from another
 138        * cache domain that isn't coherent with it (i.e. the sampler).
 139        */
 140       struct hash_table *render;
 141
 142       /**
 143        * Set of struct brw_bo * that have been used as a depth buffer within
 144        * this batchbuffer and would need flushing before being used from
 145        * another cache domain that isn't coherent with it (i.e. the sampler).
 146        */
 147       struct set *depth;
 148    } cache;
 149
 150    struct gen_batch_decode_ctx decoder;
 151    struct hash_table_u64 *state_sizes;
 152
 153    /** Have we emitted any draw calls to this batch? */
 154    bool contains_draw;
 155
 156    uint32_t last_aux_map_state;
 157 };
 158
 159 void iris_init_batch(struct iris_context *ice,
 160                      enum iris_batch_name name,
 161                      int priority);
 162 void iris_chain_to_new_batch(struct iris_batch *batch);
 163 void iris_batch_free(struct iris_batch *batch);
 164 void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
 165
 166 void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
 167 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
 168
 169 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
 170
 171 uint64_t iris_batch_prepare_noop(struct iris_batch *batch,
 172                                  bool noop_enable,
 173                                  uint64_t dirty_flags);
 174
 175 #define RELOC_WRITE EXEC_OBJECT_WRITE
 176
 177 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
 178                         bool writable);
 179
 180 enum pipe_reset_status iris_batch_check_for_reset(struct iris_batch *batch);
 181
 182 static inline unsigned
 183 iris_batch_bytes_used(struct iris_batch *batch)
 184 {
 185    return batch->map_next - batch->map;
 186 }
 187
 188 /**
 189  * Ensure the current command buffer has \param size bytes of space
 190  * remaining.  If not, this creates a secondary batch buffer and emits
 191  * a jump from the primary batch to the start of the secondary.
 192  *
 193  * Most callers want iris_get_command_space() instead.
 194  */
 195 static inline void
 196 iris_require_command_space(struct iris_batch *batch, unsigned size)
 197 {
 198    const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
 199
 200    if (required_bytes >= BATCH_SZ) {
 201       iris_chain_to_new_batch(batch);
 202    }
 203 }
 204
 205 /**
 206  * Allocate space in the current command buffer, and return a pointer
 207  * to the mapped area so the caller can write commands there.
 208  *
 209  * This should be called whenever emitting commands.
 210  */
 211 static inline void *
 212 iris_get_command_space(struct iris_batch *batch, unsigned bytes)
 213 {
 214    iris_require_command_space(batch, bytes);
 215    void *map = batch->map_next;
 216    batch->map_next += bytes;
 217    return map;
 218 }
 219
 220 /**
 221  * Helper to emit GPU commands - allocates space, copies them there.
 222  */
 223 static inline void
 224 iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
 225 {
 226    void *map = iris_get_command_space(batch, size);
 227    memcpy(map, data, size);
 228 }
 229
 230 /**
 231  * Get a pointer to the batch's signalling syncobj.  Does not refcount.
 232  */
 233 static inline struct iris_syncobj *
 234 iris_batch_get_signal_syncobj(struct iris_batch *batch)
 235 {
 236    /* The signalling syncobj is the first one in the list. */
 237    struct iris_syncobj *syncobj =
 238       ((struct iris_syncobj **) util_dynarray_begin(&batch->syncobjs))[0];
 239    return syncobj;
 240 }
 241
 242
 243 /**
 244  * Take a reference to the batch's signalling syncobj.
 245  *
 246  * Callers can use this to wait for the the current batch under construction
 247  * to complete (after flushing it).
 248  */
 249 static inline void
 250 iris_batch_reference_signal_syncobj(struct iris_batch *batch,
 251                                    struct iris_syncobj **out_syncobj)
 252 {
 253    struct iris_syncobj *syncobj = iris_batch_get_signal_syncobj(batch);
 254    iris_syncobj_reference(batch->screen, out_syncobj, syncobj);
 255 }
 256
 257 /**
 258  * Record the size of a piece of state for use in INTEL_DEBUG=bat printing.
 259  */
 260 static inline void
 261 iris_record_state_size(struct hash_table_u64 *ht,
 262                        uint32_t offset_from_base,
 263                        uint32_t size)
 264 {
 265    if (ht) {
 266       _mesa_hash_table_u64_insert(ht, offset_from_base,
 267                                   (void *)(uintptr_t) size);
 268    }
 269 }
 270
 271 #endif