amd/registers: switch to new generated register definitions
[mesa.git] / src / gallium / drivers / iris / iris_binder.c
1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_binder.c
25 *
26 * Shader programs refer to most resources via integer handles. These are
27 * indexes (BTIs) into a "Binding Table", which is simply a list of pointers
28 * to SURFACE_STATE entries. Each shader stage has its own binding table,
29 * set by the 3DSTATE_BINDING_TABLE_POINTERS_* commands. We stream out
30 * binding tables dynamically, storing them in special BOs we call "binders."
31 *
32 * Unfortunately, the hardware designers made 3DSTATE_BINDING_TABLE_POINTERS
33 * only accept a 16-bit pointer. This means that all binding tables have to
34 * live within the 64kB range starting at Surface State Base Address. (The
35 * actual SURFACE_STATE entries can live anywhere in the 4GB zone, as the
36 * binding table entries are full 32-bit pointers.)
37 *
38 * To handle this, we split a 4GB region of VMA into two memory zones.
39 * IRIS_MEMZONE_BINDER is a small region at the bottom able to hold a few
40 * binder BOs. IRIS_MEMZONE_SURFACE contains the rest of the 4GB, and is
41 * always at a higher address than the binders. This allows us to program
42 * Surface State Base Address to the binder BO's address, and offset the
43 * values in the binding table to account for the base not starting at the
44 * beginning of the 4GB region.
45 *
46 * This does mean that we have to emit STATE_BASE_ADDRESS and stall when
47 * we run out of space in the binder, which hopefully won't happen too often.
48 */
49
50 #include <stdlib.h>
51 #include "util/u_math.h"
52 #include "iris_binder.h"
53 #include "iris_bufmgr.h"
54 #include "iris_context.h"
55
56 #define BTP_ALIGNMENT 32
57
58 /* Avoid using offset 0, tools consider it NULL */
59 #define INIT_INSERT_POINT BTP_ALIGNMENT
60
61 static bool
62 binder_has_space(struct iris_binder *binder, unsigned size)
63 {
64 return binder->insert_point + size <= IRIS_BINDER_SIZE;
65 }
66
67 static void
68 binder_realloc(struct iris_context *ice)
69 {
70 struct iris_screen *screen = (void *) ice->ctx.screen;
71 struct iris_bufmgr *bufmgr = screen->bufmgr;
72 struct iris_binder *binder = &ice->state.binder;
73
74 uint64_t next_address = IRIS_MEMZONE_BINDER_START;
75
76 if (binder->bo) {
77 /* Place the new binder just after the old binder, unless we've hit the
78 * end of the memory zone...then wrap around to the start again.
79 */
80 next_address = binder->bo->gtt_offset + IRIS_BINDER_SIZE;
81 if (next_address >= IRIS_MEMZONE_SURFACE_START)
82 next_address = IRIS_MEMZONE_BINDER_START;
83
84 iris_bo_unreference(binder->bo);
85 }
86
87
88 binder->bo =
89 iris_bo_alloc(bufmgr, "binder", IRIS_BINDER_SIZE, IRIS_MEMZONE_BINDER);
90 binder->bo->gtt_offset = next_address;
91 binder->map = iris_bo_map(NULL, binder->bo, MAP_WRITE);
92 binder->insert_point = INIT_INSERT_POINT;
93
94 /* Allocating a new binder requires changing Surface State Base Address,
95 * which also invalidates all our previous binding tables - each entry
96 * in those tables is an offset from the old base.
97 *
98 * We do this here so that iris_binder_reserve_3d correctly gets a new
99 * larger total_size when making the updated reservation.
100 */
101 ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
102 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
103 }
104
105 static uint32_t
106 binder_insert(struct iris_binder *binder, unsigned size)
107 {
108 uint32_t offset = binder->insert_point;
109
110 binder->insert_point = align(binder->insert_point + size, BTP_ALIGNMENT);
111
112 return offset;
113 }
114
115 /**
116 * Reserve a block of space in the binder, given the raw size in bytes.
117 */
118 uint32_t
119 iris_binder_reserve(struct iris_context *ice,
120 unsigned size)
121 {
122 struct iris_binder *binder = &ice->state.binder;
123
124 if (!binder_has_space(binder, size))
125 binder_realloc(ice);
126
127 assert(size > 0);
128 return binder_insert(binder, size);
129 }
130
131 /**
132 * Reserve and record binder space for 3D pipeline shader stages.
133 *
134 * Note that you must actually populate the new binding tables after
135 * calling this command - the new area is uninitialized.
136 */
137 void
138 iris_binder_reserve_3d(struct iris_context *ice)
139 {
140 struct iris_compiled_shader **shaders = ice->shaders.prog;
141 struct iris_binder *binder = &ice->state.binder;
142 unsigned sizes[MESA_SHADER_STAGES] = {};
143 unsigned total_size;
144
145 /* If nothing is dirty, skip all this. */
146 if (!(ice->state.dirty & IRIS_DIRTY_RENDER_BUFFER) &&
147 !(ice->state.stage_dirty & IRIS_ALL_STAGE_DIRTY_BINDINGS))
148 return;
149
150 /* Get the binding table sizes for each stage */
151 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
152 if (!shaders[stage])
153 continue;
154
155 /* Round up the size so our next table has an aligned starting offset */
156 sizes[stage] = align(shaders[stage]->bt.size_bytes, BTP_ALIGNMENT);
157 }
158
159 /* Make space for the new binding tables...this may take two tries. */
160 while (true) {
161 total_size = 0;
162 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
163 if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage))
164 total_size += sizes[stage];
165 }
166
167 assert(total_size < IRIS_BINDER_SIZE);
168
169 if (total_size == 0)
170 return;
171
172 if (binder_has_space(binder, total_size))
173 break;
174
175 /* It didn't fit. Allocate a new buffer and try again. Note that
176 * this will flag all bindings dirty, which may increase total_size
177 * on the next iteration.
178 */
179 binder_realloc(ice);
180 }
181
182 /* Assign space and record the new binding table offsets. */
183 uint32_t offset = binder_insert(binder, total_size);
184
185 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
186 if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage)) {
187 binder->bt_offset[stage] = sizes[stage] > 0 ? offset : 0;
188 iris_record_state_size(ice->state.sizes,
189 binder->bo->gtt_offset + offset, sizes[stage]);
190 offset += sizes[stage];
191 }
192 }
193 }
194
195 void
196 iris_binder_reserve_compute(struct iris_context *ice)
197 {
198 if (!(ice->state.stage_dirty & IRIS_STAGE_DIRTY_BINDINGS_CS))
199 return;
200
201 struct iris_binder *binder = &ice->state.binder;
202 struct iris_compiled_shader *shader =
203 ice->shaders.prog[MESA_SHADER_COMPUTE];
204
205 unsigned size = shader->bt.size_bytes;
206
207 if (size == 0)
208 return;
209
210 binder->bt_offset[MESA_SHADER_COMPUTE] = iris_binder_reserve(ice, size);
211 }
212
213 void
214 iris_init_binder(struct iris_context *ice)
215 {
216 memset(&ice->state.binder, 0, sizeof(struct iris_binder));
217 binder_realloc(ice);
218 }
219
220 void
221 iris_destroy_binder(struct iris_binder *binder)
222 {
223 iris_bo_unreference(binder->bo);
224 }