2 * Copyright © 2018 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * GenX specific code for working with BLORP (blitting, resolves, clears
31 * on the 3D engine). This provides the driver-specific hooks needed to
32 * implement the BLORP API.
34 * See iris_blit.c, iris_clear.c, and so on.
39 #include "iris_batch.h"
40 #include "iris_resource.h"
41 #include "iris_context.h"
43 #include "util/u_upload_mgr.h"
44 #include "intel/common/gen_l3_config.h"
46 #define BLORP_USE_SOFTPIN
47 #include "blorp/blorp_genX_exec.h"
52 #define MOCS_WB (2 << 1)
56 stream_state(struct iris_batch
*batch
,
57 struct u_upload_mgr
*uploader
,
61 struct iris_bo
**out_bo
)
63 struct pipe_resource
*res
= NULL
;
66 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
68 struct iris_bo
*bo
= iris_resource_bo(res
);
69 iris_use_pinned_bo(batch
, bo
, false);
71 iris_record_state_size(batch
->state_sizes
,
72 bo
->gtt_offset
+ *out_offset
, size
);
74 /* If the caller has asked for a BO, we leave them the responsibility of
75 * adding bo->gtt_offset (say, by handing an address to genxml). If not,
76 * we assume they want the offset from a base address.
81 *out_offset
+= iris_bo_offset_from_base_address(bo
);
83 pipe_resource_reference(&res
, NULL
);
89 blorp_emit_dwords(struct blorp_batch
*blorp_batch
, unsigned n
)
91 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
92 return iris_get_command_space(batch
, n
* sizeof(uint32_t));
96 combine_and_pin_address(struct blorp_batch
*blorp_batch
,
97 struct blorp_address addr
)
99 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
100 struct iris_bo
*bo
= addr
.buffer
;
102 iris_use_pinned_bo(batch
, bo
, addr
.reloc_flags
& RELOC_WRITE
);
104 /* Assume this is a general address, not relative to a base. */
105 return bo
->gtt_offset
+ addr
.offset
;
109 blorp_emit_reloc(struct blorp_batch
*blorp_batch
, UNUSED
void *location
,
110 struct blorp_address addr
, uint32_t delta
)
112 return combine_and_pin_address(blorp_batch
, addr
) + delta
;
116 blorp_surface_reloc(struct blorp_batch
*blorp_batch
, uint32_t ss_offset
,
117 struct blorp_address addr
, uint32_t delta
)
119 /* Let blorp_get_surface_address do the pinning. */
123 blorp_get_surface_address(struct blorp_batch
*blorp_batch
,
124 struct blorp_address addr
)
126 return combine_and_pin_address(blorp_batch
, addr
);
129 UNUSED
static struct blorp_address
130 blorp_get_surface_base_address(UNUSED
struct blorp_batch
*blorp_batch
)
132 return (struct blorp_address
) { .offset
= IRIS_MEMZONE_BINDER_START
};
136 blorp_alloc_dynamic_state(struct blorp_batch
*blorp_batch
,
141 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
142 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
144 return stream_state(batch
, ice
->state
.dynamic_uploader
,
145 size
, alignment
, offset
, NULL
);
149 blorp_alloc_binding_table(struct blorp_batch
*blorp_batch
,
150 unsigned num_entries
,
152 unsigned state_alignment
,
154 uint32_t *surface_offsets
,
157 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
158 struct iris_binder
*binder
= &ice
->state
.binder
;
159 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
161 *bt_offset
= iris_binder_reserve(ice
, num_entries
* sizeof(uint32_t));
162 uint32_t *bt_map
= binder
->map
+ *bt_offset
;
164 for (unsigned i
= 0; i
< num_entries
; i
++) {
165 surface_maps
[i
] = stream_state(batch
, ice
->state
.surface_uploader
,
166 state_size
, state_alignment
,
167 &surface_offsets
[i
], NULL
);
168 bt_map
[i
] = surface_offsets
[i
] - (uint32_t) binder
->bo
->gtt_offset
;
171 iris_use_pinned_bo(batch
, binder
->bo
, false);
173 ice
->vtbl
.update_surface_base_address(batch
, binder
);
177 blorp_alloc_vertex_buffer(struct blorp_batch
*blorp_batch
,
179 struct blorp_address
*addr
)
181 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
182 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
186 void *map
= stream_state(batch
, ice
->ctx
.stream_uploader
, size
, 64,
189 *addr
= (struct blorp_address
) {
199 * See iris_upload_render_state's IRIS_DIRTY_VERTEX_BUFFERS handling for
200 * a comment about why these VF invalidations are needed.
203 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*blorp_batch
,
204 const struct blorp_address
*addrs
,
207 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
208 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
209 bool need_invalidate
= false;
211 for (unsigned i
= 0; i
< num_vbs
; i
++) {
212 struct iris_bo
*bo
= addrs
[i
].buffer
;
213 uint16_t high_bits
= bo
? bo
->gtt_offset
>> 32u : 0;
215 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
216 need_invalidate
= true;
217 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
221 if (need_invalidate
) {
222 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
|
223 PIPE_CONTROL_CS_STALL
);
227 static struct blorp_address
228 blorp_get_workaround_page(struct blorp_batch
*blorp_batch
)
230 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
232 return (struct blorp_address
) { .buffer
= batch
->screen
->workaround_bo
};
236 blorp_flush_range(UNUSED
struct blorp_batch
*blorp_batch
,
240 /* All allocated states come from the batch which we will flush before we
241 * submit it. There's nothing for us to do here.
246 blorp_emit_urb_config(struct blorp_batch
*blorp_batch
,
247 unsigned vs_entry_size
,
248 UNUSED
unsigned sf_entry_size
)
250 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
251 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
253 unsigned size
[4] = { vs_entry_size
, 1, 1, 1 };
255 /* If last VS URB size is good enough for what the BLORP operation needed,
256 * then we can skip reconfiguration
258 if (ice
->shaders
.last_vs_entry_size
>= vs_entry_size
)
261 genX(emit_urb_setup
)(ice
, batch
, size
, false, false);
262 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
266 iris_blorp_exec(struct blorp_batch
*blorp_batch
,
267 const struct blorp_params
*params
)
269 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
270 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
273 /* The PIPE_CONTROL command description says:
275 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
276 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
277 * Target Cache Flush by enabling this bit. When render target flush
278 * is set due to new association of BTI, PS Scoreboard Stall bit must
279 * be set in this packet."
281 iris_emit_pipe_control_flush(batch
,
282 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
283 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
286 /* Flush the sampler and render caches. We definitely need to flush the
287 * sampler cache so that we get updated contents from the render cache for
288 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
289 * docs to flush the cache between reinterpretations of the same surface
290 * data with different formats, which blorp does for stencil and depth
293 if (params
->src
.enabled
)
294 iris_cache_flush_for_read(batch
, params
->src
.addr
.buffer
);
295 if (params
->dst
.enabled
) {
296 iris_cache_flush_for_render(batch
, params
->dst
.addr
.buffer
,
297 params
->dst
.view
.format
,
298 params
->dst
.aux_usage
);
300 if (params
->depth
.enabled
)
301 iris_cache_flush_for_depth(batch
, params
->depth
.addr
.buffer
);
302 if (params
->stencil
.enabled
)
303 iris_cache_flush_for_depth(batch
, params
->stencil
.addr
.buffer
);
305 iris_require_command_space(batch
, 1400);
307 // XXX: Emit L3 state
310 // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
313 // XXX: TODO...drawing rectangle...unrevert Jason's patches on master
315 blorp_exec(blorp_batch
, params
);
317 // XXX: aperture checks?
319 /* We've smashed all state compared to what the normal 3D pipeline
320 * rendering tracks for GL.
323 uint64_t skip_bits
= (IRIS_DIRTY_POLYGON_STIPPLE
|
324 IRIS_DIRTY_SO_BUFFERS
|
325 IRIS_DIRTY_SO_DECL_LIST
|
326 IRIS_DIRTY_LINE_STIPPLE
|
327 IRIS_ALL_DIRTY_FOR_COMPUTE
|
328 IRIS_DIRTY_SCISSOR_RECT
|
329 IRIS_DIRTY_UNCOMPILED_VS
|
330 IRIS_DIRTY_UNCOMPILED_TCS
|
331 IRIS_DIRTY_UNCOMPILED_TES
|
332 IRIS_DIRTY_UNCOMPILED_GS
|
333 IRIS_DIRTY_UNCOMPILED_FS
|
336 IRIS_DIRTY_SF_CL_VIEWPORT
|
337 IRIS_DIRTY_SAMPLER_STATES_VS
|
338 IRIS_DIRTY_SAMPLER_STATES_TCS
|
339 IRIS_DIRTY_SAMPLER_STATES_TES
|
340 IRIS_DIRTY_SAMPLER_STATES_GS
);
342 /* we can skip flagging IRIS_DIRTY_DEPTH_BUFFER, if
343 * BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set.
345 if (blorp_batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
)
346 skip_bits
|= IRIS_DIRTY_DEPTH_BUFFER
;
348 if (!params
->wm_prog_data
)
349 skip_bits
|= IRIS_DIRTY_BLEND_STATE
| IRIS_DIRTY_PS_BLEND
;
351 ice
->state
.dirty
|= ~skip_bits
;
353 if (params
->dst
.enabled
) {
354 iris_render_cache_add_bo(batch
, params
->dst
.addr
.buffer
,
355 params
->dst
.view
.format
,
356 params
->dst
.aux_usage
);
358 if (params
->depth
.enabled
)
359 iris_depth_cache_add_bo(batch
, params
->depth
.addr
.buffer
);
360 if (params
->stencil
.enabled
)
361 iris_depth_cache_add_bo(batch
, params
->stencil
.addr
.buffer
);
365 genX(init_blorp
)(struct iris_context
*ice
)
367 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
369 blorp_init(&ice
->blorp
, ice
, &screen
->isl_dev
);
370 ice
->blorp
.compiler
= screen
->compiler
;
371 ice
->blorp
.lookup_shader
= iris_blorp_lookup_shader
;
372 ice
->blorp
.upload_shader
= iris_blorp_upload_shader
;
373 ice
->blorp
.exec
= iris_blorp_exec
;