2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * GenX specific code for working with BLORP (blitting, resolves, clears
31 * on the 3D engine). This provides the driver-specific hooks needed to
32 * implement the BLORP API.
34 * See iris_blit.c, iris_clear.c, and so on.
39 #include "iris_batch.h"
40 #include "iris_resource.h"
41 #include "iris_context.h"
43 #include "util/u_upload_mgr.h"
44 #include "intel/common/gen_l3_config.h"
46 #include "blorp/blorp_genX_exec.h"
49 stream_state(struct iris_batch
*batch
,
50 struct u_upload_mgr
*uploader
,
54 struct iris_bo
**out_bo
)
56 struct pipe_resource
*res
= NULL
;
59 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
61 struct iris_bo
*bo
= iris_resource_bo(res
);
62 iris_use_pinned_bo(batch
, bo
, false, IRIS_DOMAIN_NONE
);
64 iris_record_state_size(batch
->state_sizes
,
65 bo
->gtt_offset
+ *out_offset
, size
);
67 /* If the caller has asked for a BO, we leave them the responsibility of
68 * adding bo->gtt_offset (say, by handing an address to genxml). If not,
69 * we assume they want the offset from a base address.
74 *out_offset
+= iris_bo_offset_from_base_address(bo
);
76 pipe_resource_reference(&res
, NULL
);
82 blorp_emit_dwords(struct blorp_batch
*blorp_batch
, unsigned n
)
84 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
85 return iris_get_command_space(batch
, n
* sizeof(uint32_t));
89 combine_and_pin_address(struct blorp_batch
*blorp_batch
,
90 struct blorp_address addr
)
92 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
93 struct iris_bo
*bo
= addr
.buffer
;
95 iris_use_pinned_bo(batch
, bo
, addr
.reloc_flags
& RELOC_WRITE
,
98 /* Assume this is a general address, not relative to a base. */
99 return bo
->gtt_offset
+ addr
.offset
;
103 blorp_emit_reloc(struct blorp_batch
*blorp_batch
, UNUSED
void *location
,
104 struct blorp_address addr
, uint32_t delta
)
106 return combine_and_pin_address(blorp_batch
, addr
) + delta
;
110 blorp_surface_reloc(struct blorp_batch
*blorp_batch
, uint32_t ss_offset
,
111 struct blorp_address addr
, uint32_t delta
)
113 /* Let blorp_get_surface_address do the pinning. */
117 blorp_get_surface_address(struct blorp_batch
*blorp_batch
,
118 struct blorp_address addr
)
120 return combine_and_pin_address(blorp_batch
, addr
);
123 UNUSED
static struct blorp_address
124 blorp_get_surface_base_address(UNUSED
struct blorp_batch
*blorp_batch
)
126 return (struct blorp_address
) { .offset
= IRIS_MEMZONE_BINDER_START
};
130 blorp_alloc_dynamic_state(struct blorp_batch
*blorp_batch
,
135 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
136 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
138 return stream_state(batch
, ice
->state
.dynamic_uploader
,
139 size
, alignment
, offset
, NULL
);
143 blorp_alloc_binding_table(struct blorp_batch
*blorp_batch
,
144 unsigned num_entries
,
146 unsigned state_alignment
,
148 uint32_t *surface_offsets
,
151 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
152 struct iris_binder
*binder
= &ice
->state
.binder
;
153 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
155 *bt_offset
= iris_binder_reserve(ice
, num_entries
* sizeof(uint32_t));
156 uint32_t *bt_map
= binder
->map
+ *bt_offset
;
158 for (unsigned i
= 0; i
< num_entries
; i
++) {
159 surface_maps
[i
] = stream_state(batch
, ice
->state
.surface_uploader
,
160 state_size
, state_alignment
,
161 &surface_offsets
[i
], NULL
);
162 bt_map
[i
] = surface_offsets
[i
] - (uint32_t) binder
->bo
->gtt_offset
;
165 iris_use_pinned_bo(batch
, binder
->bo
, false, IRIS_DOMAIN_NONE
);
167 batch
->screen
->vtbl
.update_surface_base_address(batch
, binder
);
171 blorp_alloc_vertex_buffer(struct blorp_batch
*blorp_batch
,
173 struct blorp_address
*addr
)
175 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
176 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
180 void *map
= stream_state(batch
, ice
->ctx
.stream_uploader
, size
, 64,
183 *addr
= (struct blorp_address
) {
186 .mocs
= iris_mocs(bo
, &batch
->screen
->isl_dev
),
193 * See iris_upload_render_state's IRIS_DIRTY_VERTEX_BUFFERS handling for
194 * a comment about why these VF invalidations are needed.
197 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*blorp_batch
,
198 const struct blorp_address
*addrs
,
199 UNUSED
uint32_t *sizes
,
203 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
204 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
205 bool need_invalidate
= false;
207 for (unsigned i
= 0; i
< num_vbs
; i
++) {
208 struct iris_bo
*bo
= addrs
[i
].buffer
;
209 uint16_t high_bits
= bo
->gtt_offset
>> 32u;
211 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
212 need_invalidate
= true;
213 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
217 if (need_invalidate
) {
218 iris_emit_pipe_control_flush(batch
,
219 "workaround: VF cache 32-bit key [blorp]",
220 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
221 PIPE_CONTROL_CS_STALL
);
226 static struct blorp_address
227 blorp_get_workaround_address(struct blorp_batch
*blorp_batch
)
229 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
231 return (struct blorp_address
) {
232 .buffer
= batch
->screen
->workaround_address
.bo
,
233 .offset
= batch
->screen
->workaround_address
.offset
,
238 blorp_flush_range(UNUSED
struct blorp_batch
*blorp_batch
,
242 /* All allocated states come from the batch which we will flush before we
243 * submit it. There's nothing for us to do here.
247 static const struct gen_l3_config
*
248 blorp_get_l3_config(struct blorp_batch
*blorp_batch
)
250 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
251 return batch
->screen
->l3_config_3d
;
255 iris_blorp_exec(struct blorp_batch
*blorp_batch
,
256 const struct blorp_params
*params
)
258 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
259 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
262 /* The PIPE_CONTROL command description says:
264 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
265 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
266 * Target Cache Flush by enabling this bit. When render target flush
267 * is set due to new association of BTI, PS Scoreboard Stall bit must
268 * be set in this packet."
270 iris_emit_pipe_control_flush(batch
,
271 "workaround: RT BTI change [blorp]",
272 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
273 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
276 /* Flush the render cache in cases where the same surface is reinterpreted
277 * with a differernt format, which blorp does for stencil and depth data
278 * among other things. Invalidation of sampler caches and flushing of any
279 * caches which had previously written the source surfaces should already
280 * have been handled by the caller.
282 if (params
->dst
.enabled
) {
283 iris_cache_flush_for_render(batch
, params
->dst
.addr
.buffer
,
284 params
->dst
.view
.format
,
285 params
->dst
.aux_usage
);
288 iris_require_command_space(batch
, 1400);
291 genX(update_pma_fix
)(ice
, batch
, false);
294 const unsigned scale
= params
->fast_clear_op
? UINT_MAX
: 1;
295 if (ice
->state
.current_hash_scale
!= scale
) {
296 genX(emit_hashing_mode
)(ice
, batch
, params
->x1
- params
->x0
,
297 params
->y1
- params
->y0
, scale
);
301 genX(invalidate_aux_map_state
)(batch
);
304 iris_handle_always_flush_cache(batch
);
306 blorp_exec(blorp_batch
, params
);
308 iris_handle_always_flush_cache(batch
);
310 /* We've smashed all state compared to what the normal 3D pipeline
311 * rendering tracks for GL.
314 uint64_t skip_bits
= (IRIS_DIRTY_POLYGON_STIPPLE
|
315 IRIS_DIRTY_SO_BUFFERS
|
316 IRIS_DIRTY_SO_DECL_LIST
|
317 IRIS_DIRTY_LINE_STIPPLE
|
318 IRIS_ALL_DIRTY_FOR_COMPUTE
|
319 IRIS_DIRTY_SCISSOR_RECT
|
321 IRIS_DIRTY_SF_CL_VIEWPORT
);
322 uint64_t skip_stage_bits
= (IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE
|
323 IRIS_STAGE_DIRTY_UNCOMPILED_VS
|
324 IRIS_STAGE_DIRTY_UNCOMPILED_TCS
|
325 IRIS_STAGE_DIRTY_UNCOMPILED_TES
|
326 IRIS_STAGE_DIRTY_UNCOMPILED_GS
|
327 IRIS_STAGE_DIRTY_UNCOMPILED_FS
|
328 IRIS_STAGE_DIRTY_SAMPLER_STATES_VS
|
329 IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS
|
330 IRIS_STAGE_DIRTY_SAMPLER_STATES_TES
|
331 IRIS_STAGE_DIRTY_SAMPLER_STATES_GS
);
333 if (!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
]) {
334 /* BLORP disabled tessellation, that's fine for the next draw */
335 skip_stage_bits
|= IRIS_STAGE_DIRTY_TCS
|
336 IRIS_STAGE_DIRTY_TES
|
337 IRIS_STAGE_DIRTY_CONSTANTS_TCS
|
338 IRIS_STAGE_DIRTY_CONSTANTS_TES
|
339 IRIS_STAGE_DIRTY_BINDINGS_TCS
|
340 IRIS_STAGE_DIRTY_BINDINGS_TES
;
343 if (!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
]) {
344 /* BLORP disabled geometry shaders, that's fine for the next draw */
345 skip_stage_bits
|= IRIS_STAGE_DIRTY_GS
|
346 IRIS_STAGE_DIRTY_CONSTANTS_GS
|
347 IRIS_STAGE_DIRTY_BINDINGS_GS
;
350 /* we can skip flagging IRIS_DIRTY_DEPTH_BUFFER, if
351 * BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set.
353 if (blorp_batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
)
354 skip_bits
|= IRIS_DIRTY_DEPTH_BUFFER
;
356 if (!params
->wm_prog_data
)
357 skip_bits
|= IRIS_DIRTY_BLEND_STATE
| IRIS_DIRTY_PS_BLEND
;
359 ice
->state
.dirty
|= ~skip_bits
;
360 ice
->state
.stage_dirty
|= ~skip_stage_bits
;
362 if (params
->src
.enabled
)
363 iris_bo_bump_seqno(params
->src
.addr
.buffer
, batch
->next_seqno
,
364 IRIS_DOMAIN_OTHER_READ
);
365 if (params
->dst
.enabled
)
366 iris_bo_bump_seqno(params
->dst
.addr
.buffer
, batch
->next_seqno
,
367 IRIS_DOMAIN_RENDER_WRITE
);
368 if (params
->depth
.enabled
)
369 iris_bo_bump_seqno(params
->depth
.addr
.buffer
, batch
->next_seqno
,
370 IRIS_DOMAIN_DEPTH_WRITE
);
371 if (params
->stencil
.enabled
)
372 iris_bo_bump_seqno(params
->stencil
.addr
.buffer
, batch
->next_seqno
,
373 IRIS_DOMAIN_DEPTH_WRITE
);
377 genX(init_blorp
)(struct iris_context
*ice
)
379 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
381 blorp_init(&ice
->blorp
, ice
, &screen
->isl_dev
);
382 ice
->blorp
.compiler
= screen
->compiler
;
383 ice
->blorp
.lookup_shader
= iris_blorp_lookup_shader
;
384 ice
->blorp
.upload_shader
= iris_blorp_upload_shader
;
385 ice
->blorp
.exec
= iris_blorp_exec
;