src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <assert.h>
  24
  25 #include "iris_batch.h"
  26 #include "iris_resource.h"
  27 #include "iris_context.h"
  28
  29 #include "blorp/blorp_genX_exec.h"
  30 #include "util/u_upload_mgr.h"
  31
  32 static uint32_t *
  33 stream_state(struct iris_batch *batch,
  34              struct u_upload_mgr *uploader,
  35              unsigned size,
  36              unsigned alignment,
  37              uint32_t *out_offset,
  38              struct iris_bo **out_bo,
  39              bool relative_to_base)
  40 {
  41    struct pipe_resource *res = NULL;
  42    void *ptr = NULL;
  43
  44    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  45
  46    struct iris_bo *bo = iris_resource_bo(res);
  47    iris_use_pinned_bo(batch, bo, false);
  48
  49    *out_bo = bo;
  50    *out_offset += relative_to_base ? iris_bo_offset_from_base_address(bo)
  51                                    : bo->gtt_offset;
  52
  53    pipe_resource_reference(&res, NULL);
  54
  55    return ptr;
  56 }
  57
  58 static void *
  59 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  60 {
  61    struct iris_batch *batch = blorp_batch->driver_batch;
  62    return iris_get_command_space(batch, n * sizeof(uint32_t));
  63 }
  64
  65 static uint64_t
  66 combine_and_pin_address(struct blorp_batch *blorp_batch,
  67                         struct blorp_address addr)
  68 {
  69    struct iris_batch *batch = blorp_batch->driver_batch;
  70    struct iris_bo *bo = addr.buffer;
  71
  72    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
  73
  74    /* Assume this is a general address, not relative to a base. */
  75    return bo->gtt_offset + addr.offset;
  76 }
  77
  78 static uint64_t
  79 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
  80                  struct blorp_address addr, uint32_t delta)
  81 {
  82    return combine_and_pin_address(blorp_batch, addr) + delta;
  83 }
  84
  85 static void
  86 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
  87                     struct blorp_address addr, uint32_t delta)
  88 {
  89    /* Let blorp_get_surface_address do the pinning. */
  90 }
  91
  92 static uint64_t
  93 blorp_get_surface_address(struct blorp_batch *blorp_batch,
  94                           struct blorp_address addr)
  95 {
  96    return combine_and_pin_address(blorp_batch, addr);
  97 }
  98
  99 UNUSED static struct blorp_address
 100 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
 101 {
 102    return (struct blorp_address) { .offset = IRIS_MEMZONE_SURFACE_START };
 103 }
 104
 105 static void *
 106 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 107                           uint32_t size,
 108                           uint32_t alignment,
 109                           uint32_t *offset)
 110 {
 111    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 112    struct iris_batch *batch = blorp_batch->driver_batch;
 113    struct iris_bo *bo;
 114
 115    return stream_state(batch, ice->state.dynamic_uploader,
 116                        size, alignment, offset, &bo, true);
 117 }
 118
 119 static void
 120 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 121                           unsigned num_entries,
 122                           unsigned state_size,
 123                           unsigned state_alignment,
 124                           uint32_t *bt_offset,
 125                           uint32_t *surface_offsets,
 126                           void **surface_maps)
 127 {
 128    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 129    struct iris_batch *batch = blorp_batch->driver_batch;
 130    struct iris_bo *bo;
 131
 132    uint32_t *bt_map = iris_binder_reserve(&ice->state.binder,
 133                                           num_entries * sizeof(uint32_t),
 134                                           bt_offset);
 135    iris_use_pinned_bo(batch, ice->state.binder.bo, false);
 136
 137    for (unsigned i = 0; i < num_entries; i++) {
 138       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 139                                      state_size, state_alignment,
 140                                      &surface_offsets[i], &bo, true);
 141       bt_map[i] = surface_offsets[i];
 142    }
 143 }
 144
 145 static void *
 146 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 147                           uint32_t size,
 148                           struct blorp_address *addr)
 149 {
 150    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 151    struct iris_batch *batch = blorp_batch->driver_batch;
 152    struct iris_bo *bo;
 153    uint32_t offset;
 154
 155    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 156                             &offset, &bo, false);
 157
 158    *addr = (struct blorp_address) {
 159       .buffer = bo,
 160       .offset = offset,
 161       // XXX: Broadwell MOCS
 162       .mocs = I915_MOCS_CACHED,
 163    };
 164
 165    return map;
 166 }
 167
 168 /**
 169  * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
 170  * XXX: actually add this
 171  */
 172 static void
 173 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
 174                                            const struct blorp_address *addrs,
 175                                            unsigned num_vbs)
 176 {
 177 #if 0
 178    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 179    struct iris_batch *batch = blorp_batch->driver_batch;
 180    bool need_invalidate = false;
 181
 182    for (unsigned i = 0; i < num_vbs; i++) {
 183       struct iris_bo *bo = addrs[i].buffer;
 184       uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
 185
 186       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 187          need_invalidate = true;
 188          ice->state.last_vbo_high_bits[i] = high_bits;
 189       }
 190    }
 191
 192    if (need_invalidate) {
 193       iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
 194    }
 195 #endif
 196 }
 197
 198 static struct blorp_address
 199 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 200 {
 201    struct iris_batch *batch = blorp_batch->driver_batch;
 202
 203    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 204 }
 205
 206 static void
 207 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 208                   UNUSED void *start,
 209                   UNUSED size_t size)
 210 {
 211    /* All allocated states come from the batch which we will flush before we
 212     * submit it.  There's nothing for us to do here.
 213     */
 214 }
 215
 216 static void
 217 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 218                       unsigned vs_entry_size,
 219                       UNUSED unsigned sf_entry_size)
 220 {
 221    // XXX: URB...
 222 #if 0
 223    if (ice->urb.vsize >= vs_entry_size)
 224       return;
 225
 226    gen7_upload_urb(ice, vs_entry_size, false, false);
 227 #endif
 228 }
 229
 230 static void
 231 iris_blorp_exec(struct blorp_batch *blorp_batch,
 232                 const struct blorp_params *params)
 233 {
 234    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 235    struct iris_batch *batch = blorp_batch->driver_batch;
 236
 237    /* Flush the sampler and render caches.  We definitely need to flush the
 238     * sampler cache so that we get updated contents from the render cache for
 239     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 240     * docs to flush the cache between reinterpretations of the same surface
 241     * data with different formats, which blorp does for stencil and depth
 242     * data.
 243     */
 244    if (params->src.enabled)
 245       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 246    if (params->dst.enabled) {
 247       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 248                                   params->dst.view.format,
 249                                   params->dst.aux_usage);
 250    }
 251    if (params->depth.enabled)
 252       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 253    if (params->stencil.enabled)
 254       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 255
 256    iris_require_command_space(batch, 1400);
 257    //iris_require_statebuffer_space(ice, 600); // XXX: THIS.  Need this.
 258    batch->no_wrap = true;
 259
 260    // XXX: Emit L3 state
 261
 262 #if GEN_GEN == 8
 263    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 264 #endif
 265
 266    // XXX: knock this off...land Jason's i965 patches...
 267    blorp_emit(blorp_batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 268       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 269       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 270    }
 271
 272    blorp_exec(blorp_batch, params);
 273
 274    batch->no_wrap = false;
 275
 276    // XXX: aperture checks?
 277
 278    /* We've smashed all state compared to what the normal 3D pipeline
 279     * rendering tracks for GL.
 280     */
 281    // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
 282    ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
 283                          IRIS_DIRTY_LINE_STIPPLE);
 284
 285 #if 0
 286    ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
 287                        IRIS_DIRTY_COLOR_CALC_STATE |
 288                        IRIS_DIRTY_CONSTANTS_VS |
 289                        IRIS_DIRTY_CONSTANTS_TCS |
 290                        IRIS_DIRTY_CONSTANTS_TES |
 291                        IRIS_DIRTY_CONSTANTS_GS |
 292                        IRIS_DIRTY_CONSTANTS_PS |
 293                        IRIS_DIRTY_CONSTANTS_PS |
 294                        IRIS_DIRTY_SAMPLER_STATES_VS |
 295                        IRIS_DIRTY_SAMPLER_STATES_TCS |
 296                        IRIS_DIRTY_SAMPLER_STATES_TES |
 297                        IRIS_DIRTY_SAMPLER_STATES_GS |
 298                        IRIS_DIRTY_SAMPLER_STATES_PS |
 299                        IRIS_DIRTY_SAMPLER_STATES_PS |
 300                        IRIS_DIRTY_MULTISAMPLE |
 301                        IRIS_DIRTY_SAMPLE_MASK |
 302                        IRIS_DIRTY_VS |
 303                        IRIS_DIRTY_TCS |
 304                        IRIS_DIRTY_TES |
 305                        // IRIS_DIRTY_STREAMOUT |
 306                        IRIS_DIRTY_GS |
 307                        IRIS_DIRTY_CLIP |
 308                        IRIS_DIRTY_FS |
 309                        IRIS_DIRTY_CC_VIEWPORT |
 310 #endif
 311
 312    if (params->dst.enabled) {
 313       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 314                                params->dst.view.format,
 315                                params->dst.aux_usage);
 316    }
 317    if (params->depth.enabled)
 318       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 319    if (params->stencil.enabled)
 320       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 321 }
 322
 323 void
 324 genX(init_blorp)(struct iris_context *ice)
 325 {
 326    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 327
 328    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 329    ice->blorp.compiler = screen->compiler;
 330    ice->blorp.lookup_shader = iris_blorp_lookup_shader;
 331    ice->blorp.upload_shader = iris_blorp_upload_shader;
 332    ice->blorp.exec = iris_blorp_exec;
 333 }