src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <assert.h>
  24
  25 #include "iris_batch.h"
  26 #include "iris_resource.h"
  27 #include "iris_context.h"
  28
  29 #include "intel/common/gen_l3_config.h"
  30 #include "blorp/blorp_genX_exec.h"
  31 #include "util/u_upload_mgr.h"
  32
  33 static uint32_t *
  34 stream_state(struct iris_batch *batch,
  35              struct u_upload_mgr *uploader,
  36              unsigned size,
  37              unsigned alignment,
  38              uint32_t *out_offset,
  39              struct iris_bo **out_bo,
  40              bool relative_to_base)
  41 {
  42    struct pipe_resource *res = NULL;
  43    void *ptr = NULL;
  44
  45    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  46
  47    struct iris_bo *bo = iris_resource_bo(res);
  48    iris_use_pinned_bo(batch, bo, false);
  49
  50    *out_bo = bo;
  51    *out_offset += relative_to_base ? iris_bo_offset_from_base_address(bo)
  52                                    : bo->gtt_offset;
  53
  54    pipe_resource_reference(&res, NULL);
  55
  56    return ptr;
  57 }
  58
  59 static void *
  60 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  61 {
  62    struct iris_batch *batch = blorp_batch->driver_batch;
  63    return iris_get_command_space(batch, n * sizeof(uint32_t));
  64 }
  65
  66 static uint64_t
  67 combine_and_pin_address(struct blorp_batch *blorp_batch,
  68                         struct blorp_address addr)
  69 {
  70    struct iris_batch *batch = blorp_batch->driver_batch;
  71    struct iris_bo *bo = addr.buffer;
  72
  73    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
  74
  75    /* Assume this is a general address, not relative to a base. */
  76    return bo->gtt_offset + addr.offset;
  77 }
  78
  79 static uint64_t
  80 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
  81                  struct blorp_address addr, uint32_t delta)
  82 {
  83    return combine_and_pin_address(blorp_batch, addr) + delta;
  84 }
  85
  86 static void
  87 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
  88                     struct blorp_address addr, uint32_t delta)
  89 {
  90    /* Let blorp_get_surface_address do the pinning. */
  91 }
  92
  93 static uint64_t
  94 blorp_get_surface_address(struct blorp_batch *blorp_batch,
  95                           struct blorp_address addr)
  96 {
  97    return combine_and_pin_address(blorp_batch, addr);
  98 }
  99
 100 UNUSED static struct blorp_address
 101 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
 102 {
 103    return (struct blorp_address) { .offset = IRIS_MEMZONE_SURFACE_START };
 104 }
 105
 106 static void *
 107 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 108                           uint32_t size,
 109                           uint32_t alignment,
 110                           uint32_t *offset)
 111 {
 112    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 113    struct iris_batch *batch = blorp_batch->driver_batch;
 114    struct iris_bo *bo;
 115
 116    return stream_state(batch, ice->state.dynamic_uploader,
 117                        size, alignment, offset, &bo, true);
 118 }
 119
 120 static void
 121 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 122                           unsigned num_entries,
 123                           unsigned state_size,
 124                           unsigned state_alignment,
 125                           uint32_t *bt_offset,
 126                           uint32_t *surface_offsets,
 127                           void **surface_maps)
 128 {
 129    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 130    struct iris_batch *batch = blorp_batch->driver_batch;
 131    struct iris_bo *bo;
 132
 133    uint32_t *bt_map = iris_binder_reserve(&ice->state.binder,
 134                                           num_entries * sizeof(uint32_t),
 135                                           bt_offset);
 136    iris_use_pinned_bo(batch, ice->state.binder.bo, false);
 137
 138    for (unsigned i = 0; i < num_entries; i++) {
 139       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 140                                      state_size, state_alignment,
 141                                      &surface_offsets[i], &bo, true);
 142       bt_map[i] = surface_offsets[i];
 143    }
 144 }
 145
 146 static void *
 147 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 148                           uint32_t size,
 149                           struct blorp_address *addr)
 150 {
 151    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 152    struct iris_batch *batch = blorp_batch->driver_batch;
 153    struct iris_bo *bo;
 154    uint32_t offset;
 155
 156    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 157                             &offset, &bo, false);
 158
 159    *addr = (struct blorp_address) {
 160       .buffer = bo,
 161       .offset = offset,
 162       // XXX: Broadwell MOCS
 163       .mocs = I915_MOCS_CACHED,
 164    };
 165
 166    return map;
 167 }
 168
 169 /**
 170  * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
 171  * XXX: actually add this
 172  */
 173 static void
 174 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
 175                                            const struct blorp_address *addrs,
 176                                            unsigned num_vbs)
 177 {
 178 #if 0
 179    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 180    struct iris_batch *batch = blorp_batch->driver_batch;
 181    bool need_invalidate = false;
 182
 183    for (unsigned i = 0; i < num_vbs; i++) {
 184       struct iris_bo *bo = addrs[i].buffer;
 185       uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
 186
 187       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 188          need_invalidate = true;
 189          ice->state.last_vbo_high_bits[i] = high_bits;
 190       }
 191    }
 192
 193    if (need_invalidate) {
 194       iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
 195    }
 196 #endif
 197 }
 198
 199 static struct blorp_address
 200 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 201 {
 202    struct iris_batch *batch = blorp_batch->driver_batch;
 203
 204    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 205 }
 206
 207 static void
 208 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 209                   UNUSED void *start,
 210                   UNUSED size_t size)
 211 {
 212    /* All allocated states come from the batch which we will flush before we
 213     * submit it.  There's nothing for us to do here.
 214     */
 215 }
 216
 217 static void
 218 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 219                       unsigned vs_entry_size,
 220                       UNUSED unsigned sf_entry_size)
 221 {
 222    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 223    struct iris_batch *batch = blorp_batch->driver_batch;
 224    const struct gen_device_info *devinfo = &batch->screen->devinfo;
 225
 226    // XXX: Track last URB config and avoid re-emitting it if it's good enough
 227    const unsigned push_size_kB = 32;
 228    unsigned entries[4];
 229    unsigned start[4];
 230    unsigned size[4] = { vs_entry_size, 1, 1, 1 };
 231
 232    gen_get_urb_config(devinfo, 1024 * push_size_kB,
 233                       1024 * ice->shaders.urb_size,
 234                       false, false, size, entries, start);
 235
 236    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 237       blorp_emit(blorp_batch, GENX(3DSTATE_URB_VS), urb) {
 238          urb._3DCommandSubOpcode += i;
 239          urb.VSURBStartingAddress     = start[i];
 240          urb.VSURBEntryAllocationSize = size[i] - 1;
 241          urb.VSNumberofURBEntries     = entries[i];
 242       }
 243    }
 244 }
 245
 246 static void
 247 iris_blorp_exec(struct blorp_batch *blorp_batch,
 248                 const struct blorp_params *params)
 249 {
 250    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 251    struct iris_batch *batch = blorp_batch->driver_batch;
 252
 253    /* Flush the sampler and render caches.  We definitely need to flush the
 254     * sampler cache so that we get updated contents from the render cache for
 255     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 256     * docs to flush the cache between reinterpretations of the same surface
 257     * data with different formats, which blorp does for stencil and depth
 258     * data.
 259     */
 260    if (params->src.enabled)
 261       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 262    if (params->dst.enabled) {
 263       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 264                                   params->dst.view.format,
 265                                   params->dst.aux_usage);
 266    }
 267    if (params->depth.enabled)
 268       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 269    if (params->stencil.enabled)
 270       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 271
 272    iris_require_command_space(batch, 1400);
 273    //iris_require_statebuffer_space(ice, 600); // XXX: THIS.  Need this.
 274    batch->no_wrap = true;
 275
 276    // XXX: Emit L3 state
 277
 278 #if GEN_GEN == 8
 279    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 280 #endif
 281
 282    // XXX: knock this off...land Jason's i965 patches...
 283    blorp_emit(blorp_batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 284       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 285       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 286    }
 287
 288    blorp_exec(blorp_batch, params);
 289
 290    batch->no_wrap = false;
 291
 292    // XXX: aperture checks?
 293
 294    /* We've smashed all state compared to what the normal 3D pipeline
 295     * rendering tracks for GL.
 296     */
 297    // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
 298    ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
 299                          IRIS_DIRTY_LINE_STIPPLE);
 300
 301 #if 0
 302    ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
 303                        IRIS_DIRTY_COLOR_CALC_STATE |
 304                        IRIS_DIRTY_CONSTANTS_VS |
 305                        IRIS_DIRTY_CONSTANTS_TCS |
 306                        IRIS_DIRTY_CONSTANTS_TES |
 307                        IRIS_DIRTY_CONSTANTS_GS |
 308                        IRIS_DIRTY_CONSTANTS_PS |
 309                        IRIS_DIRTY_CONSTANTS_PS |
 310                        IRIS_DIRTY_SAMPLER_STATES_VS |
 311                        IRIS_DIRTY_SAMPLER_STATES_TCS |
 312                        IRIS_DIRTY_SAMPLER_STATES_TES |
 313                        IRIS_DIRTY_SAMPLER_STATES_GS |
 314                        IRIS_DIRTY_SAMPLER_STATES_PS |
 315                        IRIS_DIRTY_SAMPLER_STATES_PS |
 316                        IRIS_DIRTY_MULTISAMPLE |
 317                        IRIS_DIRTY_SAMPLE_MASK |
 318                        IRIS_DIRTY_VS |
 319                        IRIS_DIRTY_TCS |
 320                        IRIS_DIRTY_TES |
 321                        // IRIS_DIRTY_STREAMOUT |
 322                        IRIS_DIRTY_GS |
 323                        IRIS_DIRTY_CLIP |
 324                        IRIS_DIRTY_FS |
 325                        IRIS_DIRTY_CC_VIEWPORT |
 326 #endif
 327
 328    if (params->dst.enabled) {
 329       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 330                                params->dst.view.format,
 331                                params->dst.aux_usage);
 332    }
 333    if (params->depth.enabled)
 334       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 335    if (params->stencil.enabled)
 336       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 337 }
 338
 339 void
 340 genX(init_blorp)(struct iris_context *ice)
 341 {
 342    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 343
 344    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 345    ice->blorp.compiler = screen->compiler;
 346    ice->blorp.lookup_shader = iris_blorp_lookup_shader;
 347    ice->blorp.upload_shader = iris_blorp_upload_shader;
 348    ice->blorp.exec = iris_blorp_exec;
 349 }