src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_blorp.c
  25  *
  26  * ============================= GENXML CODE =============================
  27  *              [This file is compiled once per generation.]
  28  * =======================================================================
  29  *
  30  * GenX specific code for working with BLORP (blitting, resolves, clears
  31  * on the 3D engine).  This provides the driver-specific hooks needed to
  32  * implement the BLORP API.
  33  *
  34  * See iris_blit.c, iris_clear.c, and so on.
  35  */
  36
  37 #include <assert.h>
  38
  39 #include "iris_batch.h"
  40 #include "iris_resource.h"
  41 #include "iris_context.h"
  42
  43 #include "util/u_upload_mgr.h"
  44 #include "intel/common/gen_l3_config.h"
  45
  46 #define BLORP_USE_SOFTPIN
  47 #include "blorp/blorp_genX_exec.h"
  48
  49 static uint32_t *
  50 stream_state(struct iris_batch *batch,
  51              struct u_upload_mgr *uploader,
  52              unsigned size,
  53              unsigned alignment,
  54              uint32_t *out_offset,
  55              struct iris_bo **out_bo)
  56 {
  57    struct pipe_resource *res = NULL;
  58    void *ptr = NULL;
  59
  60    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  61
  62    struct iris_bo *bo = iris_resource_bo(res);
  63    iris_use_pinned_bo(batch, bo, false);
  64
  65    /* If the caller has asked for a BO, we leave them the responsibility of
  66     * adding bo->gtt_offset (say, by handing an address to genxml).  If not,
  67     * we assume they want the offset from a base address.
  68     */
  69    if (out_bo)
  70       *out_bo = bo;
  71    else
  72       *out_offset += iris_bo_offset_from_base_address(bo);
  73
  74    pipe_resource_reference(&res, NULL);
  75
  76    return ptr;
  77 }
  78
  79 static void *
  80 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  81 {
  82    struct iris_batch *batch = blorp_batch->driver_batch;
  83    return iris_get_command_space(batch, n * sizeof(uint32_t));
  84 }
  85
  86 static uint64_t
  87 combine_and_pin_address(struct blorp_batch *blorp_batch,
  88                         struct blorp_address addr)
  89 {
  90    struct iris_batch *batch = blorp_batch->driver_batch;
  91    struct iris_bo *bo = addr.buffer;
  92
  93    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
  94
  95    /* Assume this is a general address, not relative to a base. */
  96    return bo->gtt_offset + addr.offset;
  97 }
  98
  99 static uint64_t
 100 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
 101                  struct blorp_address addr, uint32_t delta)
 102 {
 103    return combine_and_pin_address(blorp_batch, addr) + delta;
 104 }
 105
 106 static void
 107 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
 108                     struct blorp_address addr, uint32_t delta)
 109 {
 110    /* Let blorp_get_surface_address do the pinning. */
 111 }
 112
 113 static uint64_t
 114 blorp_get_surface_address(struct blorp_batch *blorp_batch,
 115                           struct blorp_address addr)
 116 {
 117    return combine_and_pin_address(blorp_batch, addr);
 118 }
 119
 120 UNUSED static struct blorp_address
 121 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
 122 {
 123    return (struct blorp_address) { .offset = IRIS_MEMZONE_BINDER_START };
 124 }
 125
 126 static void *
 127 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 128                           uint32_t size,
 129                           uint32_t alignment,
 130                           uint32_t *offset)
 131 {
 132    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 133    struct iris_batch *batch = blorp_batch->driver_batch;
 134
 135    return stream_state(batch, ice->state.dynamic_uploader,
 136                        size, alignment, offset, NULL);
 137 }
 138
 139 static void
 140 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 141                           unsigned num_entries,
 142                           unsigned state_size,
 143                           unsigned state_alignment,
 144                           uint32_t *bt_offset,
 145                           uint32_t *surface_offsets,
 146                           void **surface_maps)
 147 {
 148    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 149    struct iris_binder *binder = &ice->state.binder;
 150    struct iris_batch *batch = blorp_batch->driver_batch;
 151
 152    *bt_offset = iris_binder_reserve(ice, num_entries * sizeof(uint32_t));
 153    uint32_t *bt_map = binder->map + *bt_offset;
 154
 155    for (unsigned i = 0; i < num_entries; i++) {
 156       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 157                                      state_size, state_alignment,
 158                                      &surface_offsets[i], NULL);
 159       bt_map[i] = surface_offsets[i] - (uint32_t) binder->bo->gtt_offset;
 160    }
 161
 162    iris_use_pinned_bo(batch, binder->bo, false);
 163
 164    ice->vtbl.update_surface_base_address(batch, binder);
 165 }
 166
 167 static void *
 168 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 169                           uint32_t size,
 170                           struct blorp_address *addr)
 171 {
 172    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 173    struct iris_batch *batch = blorp_batch->driver_batch;
 174    struct iris_bo *bo;
 175    uint32_t offset;
 176
 177    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 178                             &offset, &bo);
 179
 180    *addr = (struct blorp_address) {
 181       .buffer = bo,
 182       .offset = offset,
 183       // XXX: Broadwell MOCS
 184       .mocs = I915_MOCS_CACHED,
 185    };
 186
 187    return map;
 188 }
 189
 190 /**
 191  * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
 192  * XXX: actually add this
 193  */
 194 static void
 195 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
 196                                            const struct blorp_address *addrs,
 197                                            unsigned num_vbs)
 198 {
 199 #if 0
 200    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 201    struct iris_batch *batch = blorp_batch->driver_batch;
 202    bool need_invalidate = false;
 203
 204    for (unsigned i = 0; i < num_vbs; i++) {
 205       struct iris_bo *bo = addrs[i].buffer;
 206       uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
 207
 208       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 209          need_invalidate = true;
 210          ice->state.last_vbo_high_bits[i] = high_bits;
 211       }
 212    }
 213
 214    if (need_invalidate) {
 215       iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
 216    }
 217 #endif
 218 }
 219
 220 static struct blorp_address
 221 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 222 {
 223    struct iris_batch *batch = blorp_batch->driver_batch;
 224
 225    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 226 }
 227
 228 static void
 229 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 230                   UNUSED void *start,
 231                   UNUSED size_t size)
 232 {
 233    /* All allocated states come from the batch which we will flush before we
 234     * submit it.  There's nothing for us to do here.
 235     */
 236 }
 237
 238 static void
 239 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 240                       unsigned vs_entry_size,
 241                       UNUSED unsigned sf_entry_size)
 242 {
 243    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 244    struct iris_batch *batch = blorp_batch->driver_batch;
 245    const struct gen_device_info *devinfo = &batch->screen->devinfo;
 246
 247    // XXX: Track last URB config and avoid re-emitting it if it's good enough
 248    const unsigned push_size_kB = 32;
 249    unsigned entries[4];
 250    unsigned start[4];
 251    unsigned size[4] = { vs_entry_size, 1, 1, 1 };
 252
 253    gen_get_urb_config(devinfo, 1024 * push_size_kB,
 254                       1024 * ice->shaders.urb_size,
 255                       false, false, size, entries, start);
 256
 257    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 258       blorp_emit(blorp_batch, GENX(3DSTATE_URB_VS), urb) {
 259          urb._3DCommandSubOpcode += i;
 260          urb.VSURBStartingAddress     = start[i];
 261          urb.VSURBEntryAllocationSize = size[i] - 1;
 262          urb.VSNumberofURBEntries     = entries[i];
 263       }
 264    }
 265 }
 266
 267 static void
 268 iris_blorp_exec(struct blorp_batch *blorp_batch,
 269                 const struct blorp_params *params)
 270 {
 271    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 272    struct iris_batch *batch = blorp_batch->driver_batch;
 273
 274 #if GEN_GEN >= 11
 275    /* The PIPE_CONTROL command description says:
 276     *
 277     *    "Whenever a Binding Table Index (BTI) used by a Render Target Message
 278     *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
 279     *     Target Cache Flush by enabling this bit. When render target flush
 280     *     is set due to new association of BTI, PS Scoreboard Stall bit must
 281     *     be set in this packet."
 282     */
 283    iris_emit_pipe_control_flush(batch,
 284                                 PIPE_CONTROL_RENDER_TARGET_FLUSH |
 285                                 PIPE_CONTROL_STALL_AT_SCOREBOARD);
 286 #endif
 287
 288    /* Flush the sampler and render caches.  We definitely need to flush the
 289     * sampler cache so that we get updated contents from the render cache for
 290     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 291     * docs to flush the cache between reinterpretations of the same surface
 292     * data with different formats, which blorp does for stencil and depth
 293     * data.
 294     */
 295    if (params->src.enabled)
 296       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 297    if (params->dst.enabled) {
 298       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 299                                   params->dst.view.format,
 300                                   params->dst.aux_usage);
 301    }
 302    if (params->depth.enabled)
 303       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 304    if (params->stencil.enabled)
 305       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 306
 307    iris_require_command_space(batch, 1400);
 308
 309    // XXX: Emit L3 state
 310
 311 #if GEN_GEN == 8
 312    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 313 #endif
 314
 315    // XXX: TODO...drawing rectangle...unrevert Jason's patches on master
 316
 317    blorp_exec(blorp_batch, params);
 318
 319    // XXX: aperture checks?
 320
 321    /* We've smashed all state compared to what the normal 3D pipeline
 322     * rendering tracks for GL.
 323     */
 324    // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
 325    ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
 326                          IRIS_DIRTY_LINE_STIPPLE);
 327
 328    if (params->dst.enabled) {
 329       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 330                                params->dst.view.format,
 331                                params->dst.aux_usage);
 332    }
 333    if (params->depth.enabled)
 334       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 335    if (params->stencil.enabled)
 336       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 337 }
 338
 339 void
 340 genX(init_blorp)(struct iris_context *ice)
 341 {
 342    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 343
 344    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 345    ice->blorp.compiler = screen->compiler;
 346    ice->blorp.lookup_shader = iris_blorp_lookup_shader;
 347    ice->blorp.upload_shader = iris_blorp_upload_shader;
 348    ice->blorp.exec = iris_blorp_exec;
 349 }