src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <assert.h>
  24
  25 #include "iris_batch.h"
  26 #include "iris_resource.h"
  27 #include "iris_context.h"
  28
  29 #include "util/u_upload_mgr.h"
  30 #include "intel/common/gen_l3_config.h"
  31
  32 #define BLORP_USE_SOFTPIN
  33 #include "blorp/blorp_genX_exec.h"
  34
  35 static uint32_t *
  36 stream_state(struct iris_batch *batch,
  37              struct u_upload_mgr *uploader,
  38              unsigned size,
  39              unsigned alignment,
  40              uint32_t *out_offset,
  41              struct iris_bo **out_bo)
  42 {
  43    struct pipe_resource *res = NULL;
  44    void *ptr = NULL;
  45
  46    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  47
  48    struct iris_bo *bo = iris_resource_bo(res);
  49    iris_use_pinned_bo(batch, bo, false);
  50
  51    /* If the caller has asked for a BO, we leave them the responsibility of
  52     * adding bo->gtt_offset (say, by handing an address to genxml).  If not,
  53     * we assume they want the offset from a base address.
  54     */
  55    if (out_bo)
  56       *out_bo = bo;
  57    else
  58       *out_offset += iris_bo_offset_from_base_address(bo);
  59
  60    pipe_resource_reference(&res, NULL);
  61
  62    return ptr;
  63 }
  64
  65 static void *
  66 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  67 {
  68    struct iris_batch *batch = blorp_batch->driver_batch;
  69    return iris_get_command_space(batch, n * sizeof(uint32_t));
  70 }
  71
  72 static uint64_t
  73 combine_and_pin_address(struct blorp_batch *blorp_batch,
  74                         struct blorp_address addr)
  75 {
  76    struct iris_batch *batch = blorp_batch->driver_batch;
  77    struct iris_bo *bo = addr.buffer;
  78
  79    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
  80
  81    /* Assume this is a general address, not relative to a base. */
  82    return bo->gtt_offset + addr.offset;
  83 }
  84
  85 static uint64_t
  86 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
  87                  struct blorp_address addr, uint32_t delta)
  88 {
  89    return combine_and_pin_address(blorp_batch, addr) + delta;
  90 }
  91
  92 static void
  93 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
  94                     struct blorp_address addr, uint32_t delta)
  95 {
  96    /* Let blorp_get_surface_address do the pinning. */
  97 }
  98
  99 static uint64_t
 100 blorp_get_surface_address(struct blorp_batch *blorp_batch,
 101                           struct blorp_address addr)
 102 {
 103    return combine_and_pin_address(blorp_batch, addr);
 104 }
 105
 106 UNUSED static struct blorp_address
 107 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
 108 {
 109    return (struct blorp_address) { .offset = IRIS_MEMZONE_SURFACE_START };
 110 }
 111
 112 static void *
 113 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 114                           uint32_t size,
 115                           uint32_t alignment,
 116                           uint32_t *offset)
 117 {
 118    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 119    struct iris_batch *batch = blorp_batch->driver_batch;
 120
 121    return stream_state(batch, ice->state.dynamic_uploader,
 122                        size, alignment, offset, NULL);
 123 }
 124
 125 static void
 126 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 127                           unsigned num_entries,
 128                           unsigned state_size,
 129                           unsigned state_alignment,
 130                           uint32_t *bt_offset,
 131                           uint32_t *surface_offsets,
 132                           void **surface_maps)
 133 {
 134    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 135    struct iris_batch *batch = blorp_batch->driver_batch;
 136
 137    uint32_t *bt_map = iris_binder_reserve(&ice->state.binder,
 138                                           num_entries * sizeof(uint32_t),
 139                                           bt_offset);
 140    iris_use_pinned_bo(batch, ice->state.binder.bo, false);
 141
 142    for (unsigned i = 0; i < num_entries; i++) {
 143       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 144                                      state_size, state_alignment,
 145                                      &surface_offsets[i], NULL);
 146       bt_map[i] = surface_offsets[i];
 147    }
 148 }
 149
 150 static void *
 151 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 152                           uint32_t size,
 153                           struct blorp_address *addr)
 154 {
 155    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 156    struct iris_batch *batch = blorp_batch->driver_batch;
 157    struct iris_bo *bo;
 158    uint32_t offset;
 159
 160    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 161                             &offset, &bo);
 162
 163    *addr = (struct blorp_address) {
 164       .buffer = bo,
 165       .offset = offset,
 166       // XXX: Broadwell MOCS
 167       .mocs = I915_MOCS_CACHED,
 168    };
 169
 170    return map;
 171 }
 172
 173 /**
 174  * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
 175  * XXX: actually add this
 176  */
 177 static void
 178 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
 179                                            const struct blorp_address *addrs,
 180                                            unsigned num_vbs)
 181 {
 182 #if 0
 183    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 184    struct iris_batch *batch = blorp_batch->driver_batch;
 185    bool need_invalidate = false;
 186
 187    for (unsigned i = 0; i < num_vbs; i++) {
 188       struct iris_bo *bo = addrs[i].buffer;
 189       uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
 190
 191       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 192          need_invalidate = true;
 193          ice->state.last_vbo_high_bits[i] = high_bits;
 194       }
 195    }
 196
 197    if (need_invalidate) {
 198       iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
 199    }
 200 #endif
 201 }
 202
 203 static struct blorp_address
 204 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 205 {
 206    struct iris_batch *batch = blorp_batch->driver_batch;
 207
 208    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 209 }
 210
 211 static void
 212 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 213                   UNUSED void *start,
 214                   UNUSED size_t size)
 215 {
 216    /* All allocated states come from the batch which we will flush before we
 217     * submit it.  There's nothing for us to do here.
 218     */
 219 }
 220
 221 static void
 222 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 223                       unsigned vs_entry_size,
 224                       UNUSED unsigned sf_entry_size)
 225 {
 226    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 227    struct iris_batch *batch = blorp_batch->driver_batch;
 228    const struct gen_device_info *devinfo = &batch->screen->devinfo;
 229
 230    // XXX: Track last URB config and avoid re-emitting it if it's good enough
 231    const unsigned push_size_kB = 32;
 232    unsigned entries[4];
 233    unsigned start[4];
 234    unsigned size[4] = { vs_entry_size, 1, 1, 1 };
 235
 236    gen_get_urb_config(devinfo, 1024 * push_size_kB,
 237                       1024 * ice->shaders.urb_size,
 238                       false, false, size, entries, start);
 239
 240    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 241       blorp_emit(blorp_batch, GENX(3DSTATE_URB_VS), urb) {
 242          urb._3DCommandSubOpcode += i;
 243          urb.VSURBStartingAddress     = start[i];
 244          urb.VSURBEntryAllocationSize = size[i] - 1;
 245          urb.VSNumberofURBEntries     = entries[i];
 246       }
 247    }
 248 }
 249
 250 static void
 251 iris_blorp_exec(struct blorp_batch *blorp_batch,
 252                 const struct blorp_params *params)
 253 {
 254    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 255    struct iris_batch *batch = blorp_batch->driver_batch;
 256
 257    /* Flush the sampler and render caches.  We definitely need to flush the
 258     * sampler cache so that we get updated contents from the render cache for
 259     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 260     * docs to flush the cache between reinterpretations of the same surface
 261     * data with different formats, which blorp does for stencil and depth
 262     * data.
 263     */
 264    if (params->src.enabled)
 265       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 266    if (params->dst.enabled) {
 267       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 268                                   params->dst.view.format,
 269                                   params->dst.aux_usage);
 270    }
 271    if (params->depth.enabled)
 272       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 273    if (params->stencil.enabled)
 274       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 275
 276    iris_require_command_space(batch, 1400);
 277
 278    // XXX: Emit L3 state
 279
 280 #if GEN_GEN == 8
 281    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 282 #endif
 283
 284    // XXX: TODO...drawing rectangle...unrevert Jason's patches on master
 285
 286    blorp_exec(blorp_batch, params);
 287
 288    // XXX: aperture checks?
 289
 290    /* We've smashed all state compared to what the normal 3D pipeline
 291     * rendering tracks for GL.
 292     */
 293    // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
 294    ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
 295                          IRIS_DIRTY_LINE_STIPPLE);
 296
 297 #if 0
 298    ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
 299                        IRIS_DIRTY_COLOR_CALC_STATE |
 300                        IRIS_DIRTY_CONSTANTS_VS |
 301                        IRIS_DIRTY_CONSTANTS_TCS |
 302                        IRIS_DIRTY_CONSTANTS_TES |
 303                        IRIS_DIRTY_CONSTANTS_GS |
 304                        IRIS_DIRTY_CONSTANTS_PS |
 305                        IRIS_DIRTY_CONSTANTS_PS |
 306                        IRIS_DIRTY_SAMPLER_STATES_VS |
 307                        IRIS_DIRTY_SAMPLER_STATES_TCS |
 308                        IRIS_DIRTY_SAMPLER_STATES_TES |
 309                        IRIS_DIRTY_SAMPLER_STATES_GS |
 310                        IRIS_DIRTY_SAMPLER_STATES_PS |
 311                        IRIS_DIRTY_SAMPLER_STATES_PS |
 312                        IRIS_DIRTY_MULTISAMPLE |
 313                        IRIS_DIRTY_SAMPLE_MASK |
 314                        IRIS_DIRTY_VS |
 315                        IRIS_DIRTY_TCS |
 316                        IRIS_DIRTY_TES |
 317                        // IRIS_DIRTY_STREAMOUT |
 318                        IRIS_DIRTY_GS |
 319                        IRIS_DIRTY_CLIP |
 320                        IRIS_DIRTY_FS |
 321                        IRIS_DIRTY_CC_VIEWPORT |
 322 #endif
 323
 324    if (params->dst.enabled) {
 325       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 326                                params->dst.view.format,
 327                                params->dst.aux_usage);
 328    }
 329    if (params->depth.enabled)
 330       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 331    if (params->stencil.enabled)
 332       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 333 }
 334
 335 void
 336 genX(init_blorp)(struct iris_context *ice)
 337 {
 338    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 339
 340    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 341    ice->blorp.compiler = screen->compiler;
 342    ice->blorp.lookup_shader = iris_blorp_lookup_shader;
 343    ice->blorp.upload_shader = iris_blorp_upload_shader;
 344    ice->blorp.exec = iris_blorp_exec;
 345 }