src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <assert.h>
  24
  25 #include "iris_batch.h"
  26 #include "iris_resource.h"
  27 #include "iris_context.h"
  28
  29 #include "blorp/blorp_genX_exec.h"
  30 #include "util/u_upload_mgr.h"
  31
  32 static uint32_t *
  33 stream_state(struct iris_batch *batch,
  34              struct u_upload_mgr *uploader,
  35              unsigned size,
  36              unsigned alignment,
  37              uint32_t *out_offset,
  38              struct iris_bo **out_bo)
  39 {
  40    struct pipe_resource *res = NULL;
  41    void *ptr = NULL;
  42
  43    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  44
  45    *out_bo = iris_resource_bo(res);
  46    iris_use_pinned_bo(batch, *out_bo, false);
  47
  48    *out_offset += iris_bo_offset_from_base_address(*out_bo);
  49
  50    pipe_resource_reference(&res, NULL);
  51
  52    return ptr;
  53 }
  54
  55 static void *
  56 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  57 {
  58    struct iris_batch *batch = blorp_batch->driver_batch;
  59    return iris_get_command_space(batch, n * sizeof(uint32_t));
  60 }
  61
  62 static uint64_t
  63 combine_and_pin_address(struct blorp_batch *blorp_batch,
  64                         struct blorp_address addr)
  65 {
  66    struct iris_batch *batch = blorp_batch->driver_batch;
  67    struct iris_bo *bo = addr.buffer;
  68
  69    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
  70
  71    /* Assume this is a general address, not relative to a base. */
  72    return bo->gtt_offset + addr.offset;
  73 }
  74
  75 static uint64_t
  76 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
  77                  struct blorp_address addr, uint32_t delta)
  78 {
  79    return combine_and_pin_address(blorp_batch, addr) + delta;
  80 }
  81
  82 static void
  83 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
  84                     struct blorp_address addr, uint32_t delta)
  85 {
  86    /* Let blorp_get_surface_address do the pinning. */
  87 }
  88
  89 static uint64_t
  90 blorp_get_surface_address(struct blorp_batch *blorp_batch,
  91                           struct blorp_address addr)
  92 {
  93    return combine_and_pin_address(blorp_batch, addr);
  94 }
  95
  96 UNUSED static struct blorp_address
  97 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
  98 {
  99    return (struct blorp_address) { .offset = IRIS_MEMZONE_SURFACE_START };
 100 }
 101
 102 static void *
 103 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 104                           uint32_t size,
 105                           uint32_t alignment,
 106                           uint32_t *offset)
 107 {
 108    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 109    struct iris_batch *batch = blorp_batch->driver_batch;
 110    struct iris_bo *bo;
 111
 112    return stream_state(batch, ice->state.dynamic_uploader,
 113                        size, alignment, offset, &bo);
 114 }
 115
 116 static void
 117 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 118                           unsigned num_entries,
 119                           unsigned state_size,
 120                           unsigned state_alignment,
 121                           uint32_t *bt_offset,
 122                           uint32_t *surface_offsets,
 123                           void **surface_maps)
 124 {
 125    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 126    struct iris_batch *batch = blorp_batch->driver_batch;
 127    struct iris_bo *bo;
 128
 129    uint32_t *bt_map = iris_binder_reserve(&ice->state.binder,
 130                                           num_entries * sizeof(uint32_t),
 131                                           bt_offset);
 132
 133    for (unsigned i = 0; i < num_entries; i++) {
 134       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 135                                      state_size, state_alignment,
 136                                      &surface_offsets[i], &bo);
 137       bt_map[i] = surface_offsets[i];
 138    }
 139 }
 140
 141 static void *
 142 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 143                           uint32_t size,
 144                           struct blorp_address *addr)
 145 {
 146    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 147    struct iris_batch *batch = blorp_batch->driver_batch;
 148    struct iris_bo *bo;
 149    uint32_t offset;
 150
 151    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 152                             &offset, &bo);
 153
 154    *addr = (struct blorp_address) {
 155       .buffer = bo,
 156       .offset = offset,
 157       // XXX: Broadwell MOCS
 158       .mocs = I915_MOCS_CACHED,
 159    };
 160
 161    return map;
 162 }
 163
 164 /**
 165  * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
 166  * XXX: actually add this
 167  */
 168 static void
 169 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
 170                                            const struct blorp_address *addrs,
 171                                            unsigned num_vbs)
 172 {
 173 #if 0
 174    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 175    struct iris_batch *batch = blorp_batch->driver_batch;
 176    bool need_invalidate = false;
 177
 178    for (unsigned i = 0; i < num_vbs; i++) {
 179       struct iris_bo *bo = addrs[i].buffer;
 180       uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
 181
 182       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 183          need_invalidate = true;
 184          ice->state.last_vbo_high_bits[i] = high_bits;
 185       }
 186    }
 187
 188    if (need_invalidate) {
 189       iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
 190    }
 191 #endif
 192 }
 193
 194 static struct blorp_address
 195 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 196 {
 197    struct iris_batch *batch = blorp_batch->driver_batch;
 198
 199    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 200 }
 201
 202 static void
 203 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 204                   UNUSED void *start,
 205                   UNUSED size_t size)
 206 {
 207    /* All allocated states come from the batch which we will flush before we
 208     * submit it.  There's nothing for us to do here.
 209     */
 210 }
 211
 212 static void
 213 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 214                       unsigned vs_entry_size,
 215                       UNUSED unsigned sf_entry_size)
 216 {
 217    // XXX: URB...
 218 #if 0
 219    if (ice->urb.vsize >= vs_entry_size)
 220       return;
 221
 222    gen7_upload_urb(ice, vs_entry_size, false, false);
 223 #endif
 224 }
 225
 226 static void
 227 iris_blorp_exec(struct blorp_batch *blorp_batch,
 228                 const struct blorp_params *params)
 229 {
 230    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 231    struct iris_batch *batch = blorp_batch->driver_batch;
 232
 233    /* Flush the sampler and render caches.  We definitely need to flush the
 234     * sampler cache so that we get updated contents from the render cache for
 235     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 236     * docs to flush the cache between reinterpretations of the same surface
 237     * data with different formats, which blorp does for stencil and depth
 238     * data.
 239     */
 240    if (params->src.enabled)
 241       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 242    if (params->dst.enabled) {
 243       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 244                                   params->dst.view.format,
 245                                   params->dst.aux_usage);
 246    }
 247    if (params->depth.enabled)
 248       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 249    if (params->stencil.enabled)
 250       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 251
 252    iris_require_command_space(batch, 1400);
 253    //iris_require_statebuffer_space(ice, 600); // XXX: THIS.  Need this.
 254    batch->no_wrap = true;
 255
 256    // XXX: Emit L3 state
 257
 258 #if GEN_GEN == 8
 259    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 260 #endif
 261
 262    // XXX: knock this off...land Jason's i965 patches...
 263    blorp_emit(blorp_batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 264       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 265       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 266    }
 267
 268    blorp_exec(blorp_batch, params);
 269
 270    batch->no_wrap = false;
 271
 272    // XXX: aperture checks?
 273
 274    /* We've smashed all state compared to what the normal 3D pipeline
 275     * rendering tracks for GL.
 276     */
 277    // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
 278    ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
 279                          IRIS_DIRTY_LINE_STIPPLE);
 280
 281 #if 0
 282    ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
 283                        IRIS_DIRTY_COLOR_CALC_STATE |
 284                        IRIS_DIRTY_CONSTANTS_VS |
 285                        IRIS_DIRTY_CONSTANTS_TCS |
 286                        IRIS_DIRTY_CONSTANTS_TES |
 287                        IRIS_DIRTY_CONSTANTS_GS |
 288                        IRIS_DIRTY_CONSTANTS_PS |
 289                        IRIS_DIRTY_CONSTANTS_PS |
 290                        IRIS_DIRTY_SAMPLER_STATES_VS |
 291                        IRIS_DIRTY_SAMPLER_STATES_TCS |
 292                        IRIS_DIRTY_SAMPLER_STATES_TES |
 293                        IRIS_DIRTY_SAMPLER_STATES_GS |
 294                        IRIS_DIRTY_SAMPLER_STATES_PS |
 295                        IRIS_DIRTY_SAMPLER_STATES_PS |
 296                        IRIS_DIRTY_MULTISAMPLE |
 297                        IRIS_DIRTY_SAMPLE_MASK |
 298                        IRIS_DIRTY_VS |
 299                        IRIS_DIRTY_TCS |
 300                        IRIS_DIRTY_TES |
 301                        // IRIS_DIRTY_STREAMOUT |
 302                        IRIS_DIRTY_GS |
 303                        IRIS_DIRTY_CLIP |
 304                        IRIS_DIRTY_FS |
 305                        IRIS_DIRTY_CC_VIEWPORT |
 306 #endif
 307
 308    if (params->dst.enabled) {
 309       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 310                                params->dst.view.format,
 311                                params->dst.aux_usage);
 312    }
 313    if (params->depth.enabled)
 314       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 315    if (params->stencil.enabled)
 316       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 317 }
 318
 319 void
 320 genX(init_blorp)(struct iris_context *ice)
 321 {
 322    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 323
 324    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 325    ice->blorp.compiler = screen->compiler;
 326
 327    ice->vtbl.blorp_exec = iris_blorp_exec;
 328 }