src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_blorp.c
  25  *
  26  * ============================= GENXML CODE =============================
  27  *              [This file is compiled once per generation.]
  28  * =======================================================================
  29  *
  30  * GenX specific code for working with BLORP (blitting, resolves, clears
  31  * on the 3D engine).  This provides the driver-specific hooks needed to
  32  * implement the BLORP API.
  33  *
  34  * See iris_blit.c, iris_clear.c, and so on.
  35  */
  36
  37 #include <assert.h>
  38
  39 #include "iris_batch.h"
  40 #include "iris_resource.h"
  41 #include "iris_context.h"
  42
  43 #include "util/u_upload_mgr.h"
  44 #include "intel/common/gen_l3_config.h"
  45
  46 #define BLORP_USE_SOFTPIN
  47 #include "blorp/blorp_genX_exec.h"
  48
  49 #if GEN_GEN == 8
  50 #define MOCS_WB 0x78
  51 #else
  52 #define MOCS_WB (2 << 1)
  53 #endif
  54
  55 static uint32_t *
  56 stream_state(struct iris_batch *batch,
  57              struct u_upload_mgr *uploader,
  58              unsigned size,
  59              unsigned alignment,
  60              uint32_t *out_offset,
  61              struct iris_bo **out_bo)
  62 {
  63    struct pipe_resource *res = NULL;
  64    void *ptr = NULL;
  65
  66    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  67
  68    struct iris_bo *bo = iris_resource_bo(res);
  69    iris_use_pinned_bo(batch, bo, false);
  70
  71    /* If the caller has asked for a BO, we leave them the responsibility of
  72     * adding bo->gtt_offset (say, by handing an address to genxml).  If not,
  73     * we assume they want the offset from a base address.
  74     */
  75    if (out_bo)
  76       *out_bo = bo;
  77    else
  78       *out_offset += iris_bo_offset_from_base_address(bo);
  79
  80    pipe_resource_reference(&res, NULL);
  81
  82    return ptr;
  83 }
  84
  85 static void *
  86 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  87 {
  88    struct iris_batch *batch = blorp_batch->driver_batch;
  89    return iris_get_command_space(batch, n * sizeof(uint32_t));
  90 }
  91
  92 static uint64_t
  93 combine_and_pin_address(struct blorp_batch *blorp_batch,
  94                         struct blorp_address addr)
  95 {
  96    struct iris_batch *batch = blorp_batch->driver_batch;
  97    struct iris_bo *bo = addr.buffer;
  98
  99    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
 100
 101    /* Assume this is a general address, not relative to a base. */
 102    return bo->gtt_offset + addr.offset;
 103 }
 104
 105 static uint64_t
 106 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
 107                  struct blorp_address addr, uint32_t delta)
 108 {
 109    return combine_and_pin_address(blorp_batch, addr) + delta;
 110 }
 111
 112 static void
 113 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
 114                     struct blorp_address addr, uint32_t delta)
 115 {
 116    /* Let blorp_get_surface_address do the pinning. */
 117 }
 118
 119 static uint64_t
 120 blorp_get_surface_address(struct blorp_batch *blorp_batch,
 121                           struct blorp_address addr)
 122 {
 123    return combine_and_pin_address(blorp_batch, addr);
 124 }
 125
 126 UNUSED static struct blorp_address
 127 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
 128 {
 129    return (struct blorp_address) { .offset = IRIS_MEMZONE_BINDER_START };
 130 }
 131
 132 static void *
 133 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 134                           uint32_t size,
 135                           uint32_t alignment,
 136                           uint32_t *offset)
 137 {
 138    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 139    struct iris_batch *batch = blorp_batch->driver_batch;
 140
 141    return stream_state(batch, ice->state.dynamic_uploader,
 142                        size, alignment, offset, NULL);
 143 }
 144
 145 static void
 146 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 147                           unsigned num_entries,
 148                           unsigned state_size,
 149                           unsigned state_alignment,
 150                           uint32_t *bt_offset,
 151                           uint32_t *surface_offsets,
 152                           void **surface_maps)
 153 {
 154    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 155    struct iris_binder *binder = &ice->state.binder;
 156    struct iris_batch *batch = blorp_batch->driver_batch;
 157
 158    *bt_offset = iris_binder_reserve(ice, num_entries * sizeof(uint32_t));
 159    uint32_t *bt_map = binder->map + *bt_offset;
 160
 161    for (unsigned i = 0; i < num_entries; i++) {
 162       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 163                                      state_size, state_alignment,
 164                                      &surface_offsets[i], NULL);
 165       bt_map[i] = surface_offsets[i] - (uint32_t) binder->bo->gtt_offset;
 166    }
 167
 168    iris_use_pinned_bo(batch, binder->bo, false);
 169
 170    ice->vtbl.update_surface_base_address(batch, binder);
 171 }
 172
 173 static void *
 174 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 175                           uint32_t size,
 176                           struct blorp_address *addr)
 177 {
 178    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 179    struct iris_batch *batch = blorp_batch->driver_batch;
 180    struct iris_bo *bo;
 181    uint32_t offset;
 182
 183    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 184                             &offset, &bo);
 185
 186    *addr = (struct blorp_address) {
 187       .buffer = bo,
 188       .offset = offset,
 189       .mocs = MOCS_WB,
 190    };
 191
 192    return map;
 193 }
 194
 195 /**
 196  * See iris_upload_render_state's IRIS_DIRTY_VERTEX_BUFFERS handling for
 197  * a comment about why these VF invalidations are needed.
 198  */
 199 static void
 200 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *blorp_batch,
 201                                            const struct blorp_address *addrs,
 202                                            unsigned num_vbs)
 203 {
 204    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 205    struct iris_batch *batch = blorp_batch->driver_batch;
 206    bool need_invalidate = false;
 207
 208    for (unsigned i = 0; i < num_vbs; i++) {
 209       struct iris_bo *bo = addrs[i].buffer;
 210       uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
 211
 212       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 213          need_invalidate = true;
 214          ice->state.last_vbo_high_bits[i] = high_bits;
 215       }
 216    }
 217
 218    if (need_invalidate) {
 219       iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE |
 220                                           PIPE_CONTROL_CS_STALL);
 221    }
 222 }
 223
 224 static struct blorp_address
 225 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 226 {
 227    struct iris_batch *batch = blorp_batch->driver_batch;
 228
 229    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 230 }
 231
 232 static void
 233 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 234                   UNUSED void *start,
 235                   UNUSED size_t size)
 236 {
 237    /* All allocated states come from the batch which we will flush before we
 238     * submit it.  There's nothing for us to do here.
 239     */
 240 }
 241
 242 static void
 243 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 244                       unsigned vs_entry_size,
 245                       UNUSED unsigned sf_entry_size)
 246 {
 247    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 248    struct iris_batch *batch = blorp_batch->driver_batch;
 249
 250    unsigned size[4] = { vs_entry_size, 1, 1, 1 };
 251
 252    /* If last VS URB size is good enough for what the BLORP operation needed,
 253     * then we can skip reconfiguration
 254     */
 255    if (ice->shaders.last_vs_entry_size >= vs_entry_size)
 256       return;
 257
 258    genX(emit_urb_setup)(ice, batch, size, false, false);
 259    ice->state.dirty |= IRIS_DIRTY_URB;
 260 }
 261
 262 static void
 263 iris_blorp_exec(struct blorp_batch *blorp_batch,
 264                 const struct blorp_params *params)
 265 {
 266    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 267    struct iris_batch *batch = blorp_batch->driver_batch;
 268
 269 #if GEN_GEN >= 11
 270    /* The PIPE_CONTROL command description says:
 271     *
 272     *    "Whenever a Binding Table Index (BTI) used by a Render Target Message
 273     *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
 274     *     Target Cache Flush by enabling this bit. When render target flush
 275     *     is set due to new association of BTI, PS Scoreboard Stall bit must
 276     *     be set in this packet."
 277     */
 278    iris_emit_pipe_control_flush(batch,
 279                                 PIPE_CONTROL_RENDER_TARGET_FLUSH |
 280                                 PIPE_CONTROL_STALL_AT_SCOREBOARD);
 281 #endif
 282
 283    /* Flush the sampler and render caches.  We definitely need to flush the
 284     * sampler cache so that we get updated contents from the render cache for
 285     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 286     * docs to flush the cache between reinterpretations of the same surface
 287     * data with different formats, which blorp does for stencil and depth
 288     * data.
 289     */
 290    if (params->src.enabled)
 291       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 292    if (params->dst.enabled) {
 293       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 294                                   params->dst.view.format,
 295                                   params->dst.aux_usage);
 296    }
 297    if (params->depth.enabled)
 298       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 299    if (params->stencil.enabled)
 300       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 301
 302    iris_require_command_space(batch, 1400);
 303
 304    // XXX: Emit L3 state
 305
 306 #if GEN_GEN == 8
 307    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 308 #endif
 309
 310    // XXX: TODO...drawing rectangle...unrevert Jason's patches on master
 311
 312    blorp_exec(blorp_batch, params);
 313
 314    // XXX: aperture checks?
 315
 316    /* We've smashed all state compared to what the normal 3D pipeline
 317     * rendering tracks for GL.
 318     */
 319
 320    uint64_t skip_bits = (IRIS_DIRTY_POLYGON_STIPPLE |
 321                          IRIS_DIRTY_SO_BUFFERS |
 322                          IRIS_DIRTY_SO_DECL_LIST |
 323                          IRIS_DIRTY_LINE_STIPPLE |
 324                          IRIS_ALL_DIRTY_FOR_COMPUTE |
 325                          IRIS_DIRTY_SCISSOR_RECT |
 326                          IRIS_DIRTY_UNCOMPILED_VS |
 327                          IRIS_DIRTY_UNCOMPILED_TCS |
 328                          IRIS_DIRTY_UNCOMPILED_TES |
 329                          IRIS_DIRTY_UNCOMPILED_GS |
 330                          IRIS_DIRTY_UNCOMPILED_FS |
 331                          IRIS_DIRTY_VF |
 332                          IRIS_DIRTY_SF_CL_VIEWPORT |
 333                          IRIS_DIRTY_SAMPLER_STATES_VS |
 334                          IRIS_DIRTY_SAMPLER_STATES_TCS |
 335                          IRIS_DIRTY_SAMPLER_STATES_TES |
 336                          IRIS_DIRTY_SAMPLER_STATES_GS);
 337
 338    /* we can skip flagging IRIS_DIRTY_DEPTH_BUFFER, if
 339     * BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set.
 340     */
 341    if (blorp_batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)
 342       skip_bits |= IRIS_DIRTY_DEPTH_BUFFER;
 343
 344    if (!params->wm_prog_data)
 345       skip_bits |= IRIS_DIRTY_BLEND_STATE | IRIS_DIRTY_PS_BLEND;
 346
 347    ice->state.dirty |= ~skip_bits;
 348
 349    if (params->dst.enabled) {
 350       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 351                                params->dst.view.format,
 352                                params->dst.aux_usage);
 353    }
 354    if (params->depth.enabled)
 355       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 356    if (params->stencil.enabled)
 357       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 358 }
 359
 360 void
 361 genX(init_blorp)(struct iris_context *ice)
 362 {
 363    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 364
 365    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 366    ice->blorp.compiler = screen->compiler;
 367    ice->blorp.lookup_shader = iris_blorp_lookup_shader;
 368    ice->blorp.upload_shader = iris_blorp_upload_shader;
 369    ice->blorp.exec = iris_blorp_exec;
 370 }