2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "iris_batch.h"
26 #include "iris_resource.h"
27 #include "iris_context.h"
29 #include "blorp/blorp_genX_exec.h"
30 #include "util/u_upload_mgr.h"
33 stream_state(struct iris_batch
*batch
,
34 struct u_upload_mgr
*uploader
,
38 struct iris_bo
**out_bo
,
39 bool relative_to_base
)
41 struct pipe_resource
*res
= NULL
;
44 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
46 struct iris_bo
*bo
= iris_resource_bo(res
);
47 iris_use_pinned_bo(batch
, bo
, false);
50 *out_offset
+= relative_to_base
? iris_bo_offset_from_base_address(bo
)
53 pipe_resource_reference(&res
, NULL
);
59 blorp_emit_dwords(struct blorp_batch
*blorp_batch
, unsigned n
)
61 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
62 return iris_get_command_space(batch
, n
* sizeof(uint32_t));
66 combine_and_pin_address(struct blorp_batch
*blorp_batch
,
67 struct blorp_address addr
)
69 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
70 struct iris_bo
*bo
= addr
.buffer
;
72 iris_use_pinned_bo(batch
, bo
, addr
.reloc_flags
& RELOC_WRITE
);
74 /* Assume this is a general address, not relative to a base. */
75 return bo
->gtt_offset
+ addr
.offset
;
79 blorp_emit_reloc(struct blorp_batch
*blorp_batch
, UNUSED
void *location
,
80 struct blorp_address addr
, uint32_t delta
)
82 return combine_and_pin_address(blorp_batch
, addr
) + delta
;
86 blorp_surface_reloc(struct blorp_batch
*blorp_batch
, uint32_t ss_offset
,
87 struct blorp_address addr
, uint32_t delta
)
89 /* Let blorp_get_surface_address do the pinning. */
93 blorp_get_surface_address(struct blorp_batch
*blorp_batch
,
94 struct blorp_address addr
)
96 return combine_and_pin_address(blorp_batch
, addr
);
99 UNUSED
static struct blorp_address
100 blorp_get_surface_base_address(UNUSED
struct blorp_batch
*blorp_batch
)
102 return (struct blorp_address
) { .offset
= IRIS_MEMZONE_SURFACE_START
};
106 blorp_alloc_dynamic_state(struct blorp_batch
*blorp_batch
,
111 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
112 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
115 return stream_state(batch
, ice
->state
.dynamic_uploader
,
116 size
, alignment
, offset
, &bo
, true);
120 blorp_alloc_binding_table(struct blorp_batch
*blorp_batch
,
121 unsigned num_entries
,
123 unsigned state_alignment
,
125 uint32_t *surface_offsets
,
128 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
129 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
132 uint32_t *bt_map
= iris_binder_reserve(&ice
->state
.binder
,
133 num_entries
* sizeof(uint32_t),
136 for (unsigned i
= 0; i
< num_entries
; i
++) {
137 surface_maps
[i
] = stream_state(batch
, ice
->state
.surface_uploader
,
138 state_size
, state_alignment
,
139 &surface_offsets
[i
], &bo
, true);
140 bt_map
[i
] = surface_offsets
[i
];
145 blorp_alloc_vertex_buffer(struct blorp_batch
*blorp_batch
,
147 struct blorp_address
*addr
)
149 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
150 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
154 void *map
= stream_state(batch
, ice
->ctx
.stream_uploader
, size
, 64,
155 &offset
, &bo
, false);
157 *addr
= (struct blorp_address
) {
160 // XXX: Broadwell MOCS
161 .mocs
= I915_MOCS_CACHED
,
168 * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
169 * XXX: actually add this
172 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*batch
,
173 const struct blorp_address
*addrs
,
177 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
178 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
179 bool need_invalidate
= false;
181 for (unsigned i
= 0; i
< num_vbs
; i
++) {
182 struct iris_bo
*bo
= addrs
[i
].buffer
;
183 uint16_t high_bits
= bo
? bo
->gtt_offset
>> 32u : 0;
185 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
186 need_invalidate
= true;
187 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
191 if (need_invalidate
) {
192 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
197 static struct blorp_address
198 blorp_get_workaround_page(struct blorp_batch
*blorp_batch
)
200 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
202 return (struct blorp_address
) { .buffer
= batch
->screen
->workaround_bo
};
206 blorp_flush_range(UNUSED
struct blorp_batch
*blorp_batch
,
210 /* All allocated states come from the batch which we will flush before we
211 * submit it. There's nothing for us to do here.
216 blorp_emit_urb_config(struct blorp_batch
*blorp_batch
,
217 unsigned vs_entry_size
,
218 UNUSED
unsigned sf_entry_size
)
222 if (ice
->urb
.vsize
>= vs_entry_size
)
225 gen7_upload_urb(ice
, vs_entry_size
, false, false);
230 iris_blorp_exec(struct blorp_batch
*blorp_batch
,
231 const struct blorp_params
*params
)
233 struct iris_context
*ice
= blorp_batch
->blorp
->driver_ctx
;
234 struct iris_batch
*batch
= blorp_batch
->driver_batch
;
236 /* Flush the sampler and render caches. We definitely need to flush the
237 * sampler cache so that we get updated contents from the render cache for
238 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
239 * docs to flush the cache between reinterpretations of the same surface
240 * data with different formats, which blorp does for stencil and depth
243 if (params
->src
.enabled
)
244 iris_cache_flush_for_read(batch
, params
->src
.addr
.buffer
);
245 if (params
->dst
.enabled
) {
246 iris_cache_flush_for_render(batch
, params
->dst
.addr
.buffer
,
247 params
->dst
.view
.format
,
248 params
->dst
.aux_usage
);
250 if (params
->depth
.enabled
)
251 iris_cache_flush_for_depth(batch
, params
->depth
.addr
.buffer
);
252 if (params
->stencil
.enabled
)
253 iris_cache_flush_for_depth(batch
, params
->stencil
.addr
.buffer
);
255 iris_require_command_space(batch
, 1400);
256 //iris_require_statebuffer_space(ice, 600); // XXX: THIS. Need this.
257 batch
->no_wrap
= true;
259 // XXX: Emit L3 state
262 // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
265 // XXX: knock this off...land Jason's i965 patches...
266 blorp_emit(blorp_batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
267 rect
.ClippedDrawingRectangleXMax
= MAX2(params
->x1
, params
->x0
) - 1;
268 rect
.ClippedDrawingRectangleYMax
= MAX2(params
->y1
, params
->y0
) - 1;
271 blorp_exec(blorp_batch
, params
);
273 batch
->no_wrap
= false;
275 // XXX: aperture checks?
277 /* We've smashed all state compared to what the normal 3D pipeline
278 * rendering tracks for GL.
280 // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
281 ice
->state
.dirty
|= ~(IRIS_DIRTY_POLYGON_STIPPLE
|
282 IRIS_DIRTY_LINE_STIPPLE
);
285 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
286 IRIS_DIRTY_COLOR_CALC_STATE
|
287 IRIS_DIRTY_CONSTANTS_VS
|
288 IRIS_DIRTY_CONSTANTS_TCS
|
289 IRIS_DIRTY_CONSTANTS_TES
|
290 IRIS_DIRTY_CONSTANTS_GS
|
291 IRIS_DIRTY_CONSTANTS_PS
|
292 IRIS_DIRTY_CONSTANTS_PS
|
293 IRIS_DIRTY_SAMPLER_STATES_VS
|
294 IRIS_DIRTY_SAMPLER_STATES_TCS
|
295 IRIS_DIRTY_SAMPLER_STATES_TES
|
296 IRIS_DIRTY_SAMPLER_STATES_GS
|
297 IRIS_DIRTY_SAMPLER_STATES_PS
|
298 IRIS_DIRTY_SAMPLER_STATES_PS
|
299 IRIS_DIRTY_MULTISAMPLE
|
300 IRIS_DIRTY_SAMPLE_MASK
|
304 // IRIS_DIRTY_STREAMOUT |
308 IRIS_DIRTY_CC_VIEWPORT
|
311 if (params
->dst
.enabled
) {
312 iris_render_cache_add_bo(batch
, params
->dst
.addr
.buffer
,
313 params
->dst
.view
.format
,
314 params
->dst
.aux_usage
);
316 if (params
->depth
.enabled
)
317 iris_depth_cache_add_bo(batch
, params
->depth
.addr
.buffer
);
318 if (params
->stencil
.enabled
)
319 iris_depth_cache_add_bo(batch
, params
->stencil
.addr
.buffer
);
323 genX(init_blorp
)(struct iris_context
*ice
)
325 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
327 blorp_init(&ice
->blorp
, ice
, &screen
->isl_dev
);
328 ice
->blorp
.compiler
= screen
->compiler
;
329 ice
->blorp
.lookup_shader
= iris_blorp_lookup_shader
;
330 ice
->blorp
.upload_shader
= iris_blorp_upload_shader
;
331 ice
->blorp
.exec
= iris_blorp_exec
;