2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
49 #include <sys/types.h>
55 #define ETIME ETIMEDOUT
57 #include "common/gen_clflush.h"
58 #include "dev/gen_debug.h"
59 #include "common/gen_gem.h"
60 #include "dev/gen_device_info.h"
61 #include "main/macros.h"
62 #include "util/debug.h"
63 #include "util/macros.h"
64 #include "util/hash_table.h"
65 #include "util/list.h"
66 #include "util/u_dynarray.h"
68 #include "iris_bufmgr.h"
69 #include "iris_context.h"
72 #include "drm-uapi/i915_drm.h"
82 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
83 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
84 * leaked. All because it does not call VG(cli_free) from its
85 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
86 * and allocation, we mark it available for use upon mmapping and remove
89 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
90 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
92 #define PAGE_SIZE 4096
94 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
97 * Call ioctl, restarting if it is interupted
100 drm_ioctl(int fd
, unsigned long request
, void *arg
)
105 ret
= ioctl(fd
, request
, arg
);
106 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
111 atomic_add_unless(int *v
, int add
, int unless
)
114 c
= p_atomic_read(v
);
115 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
121 memzone_name(enum iris_memory_zone memzone
)
123 const char *names
[] = {
124 [IRIS_MEMZONE_SHADER
] = "shader",
125 [IRIS_MEMZONE_BINDER
] = "binder",
126 [IRIS_MEMZONE_SURFACE
] = "surface",
127 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
128 [IRIS_MEMZONE_OTHER
] = "other",
129 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
131 assert(memzone
< ARRAY_SIZE(names
));
132 return names
[memzone
];
135 struct bo_cache_bucket
{
136 /** List of cached BOs. */
137 struct list_head head
;
139 /** Size of this bucket, in bytes. */
148 /** Array of lists of cached gem objects of power-of-two sizes */
149 struct bo_cache_bucket cache_bucket
[14 * 4];
153 struct hash_table
*name_table
;
154 struct hash_table
*handle_table
;
156 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
162 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
165 static void bo_free(struct iris_bo
*bo
);
167 static uint64_t vma_alloc(struct iris_bufmgr
*bufmgr
,
168 enum iris_memory_zone memzone
,
169 uint64_t size
, uint64_t alignment
);
172 key_hash_uint(const void *key
)
174 return _mesa_hash_data(key
, 4);
178 key_uint_equal(const void *a
, const void *b
)
180 return *((unsigned *) a
) == *((unsigned *) b
);
183 static struct iris_bo
*
184 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
186 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
187 return entry
? (struct iris_bo
*) entry
->data
: NULL
;
191 * This function finds the correct bucket fit for the input size.
192 * The function works with O(1) complexity when the requested size
193 * was queried instead of iterating the size through all the buckets.
195 static struct bo_cache_bucket
*
196 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
198 /* Calculating the pages and rounding up to the page size. */
199 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
201 /* Row Bucket sizes clz((x-1) | 3) Row Column
202 * in pages stride size
203 * 0: 1 2 3 4 -> 30 30 30 30 4 1
204 * 1: 5 6 7 8 -> 29 29 29 29 4 1
205 * 2: 10 12 14 16 -> 28 28 28 28 8 2
206 * 3: 20 24 28 32 -> 27 27 27 27 16 4
208 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
209 const unsigned row_max_pages
= 4 << row
;
211 /* The '& ~2' is the special case for row 1. In row 1, max pages /
212 * 2 is 2, but the previous row maximum is zero (because there is
213 * no previous row). All row maximum sizes are power of 2, so that
214 * is the only case where that bit will be set.
216 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
217 int col_size_log2
= row
- 1;
218 col_size_log2
+= (col_size_log2
< 0);
220 const unsigned col
= (pages
- prev_row_max_pages
+
221 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
223 /* Calculating the index based on the row and column. */
224 const unsigned index
= (row
* 4) + (col
- 1);
226 return (index
< bufmgr
->num_buckets
) ?
227 &bufmgr
->cache_bucket
[index
] : NULL
;
230 enum iris_memory_zone
231 iris_memzone_for_address(uint64_t address
)
233 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
234 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
235 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
236 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
237 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
239 if (address
>= IRIS_MEMZONE_OTHER_START
)
240 return IRIS_MEMZONE_OTHER
;
242 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
243 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
245 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
246 return IRIS_MEMZONE_DYNAMIC
;
248 if (address
>= IRIS_MEMZONE_SURFACE_START
)
249 return IRIS_MEMZONE_SURFACE
;
251 if (address
>= IRIS_MEMZONE_BINDER_START
)
252 return IRIS_MEMZONE_BINDER
;
254 return IRIS_MEMZONE_SHADER
;
258 * Allocate a section of virtual memory for a buffer, assigning an address.
260 * This uses either the bucket allocator for the given size, or the large
261 * object allocator (util_vma).
264 vma_alloc(struct iris_bufmgr
*bufmgr
,
265 enum iris_memory_zone memzone
,
269 /* Force alignment to be some number of pages */
270 alignment
= ALIGN(alignment
, PAGE_SIZE
);
272 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
273 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
275 /* The binder handles its own allocations. Return non-zero here. */
276 if (memzone
== IRIS_MEMZONE_BINDER
)
277 return IRIS_MEMZONE_BINDER_START
;
280 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
282 assert((addr
>> 48ull) == 0);
283 assert((addr
% alignment
) == 0);
285 return gen_canonical_address(addr
);
289 vma_free(struct iris_bufmgr
*bufmgr
,
293 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
296 /* Un-canonicalize the address. */
297 address
= gen_48b_address(address
);
302 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
304 /* The binder handles its own allocations. */
305 if (memzone
== IRIS_MEMZONE_BINDER
)
308 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
312 iris_bo_busy(struct iris_bo
*bo
)
314 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
315 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
317 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
319 bo
->idle
= !busy
.busy
;
326 iris_bo_madvise(struct iris_bo
*bo
, int state
)
328 struct drm_i915_gem_madvise madv
= {
329 .handle
= bo
->gem_handle
,
334 drm_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
336 return madv
.retained
;
339 static struct iris_bo
*
342 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
344 bo
->hash
= _mesa_hash_pointer(bo
);
349 static struct iris_bo
*
350 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
351 struct bo_cache_bucket
*bucket
,
352 enum iris_memory_zone memzone
,
359 struct iris_bo
*bo
= NULL
;
361 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
362 /* Try a little harder to find one that's already in the right memzone */
363 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
366 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
367 * either falling back to a non-matching memzone, or if that fails,
368 * allocating a fresh buffer.
370 if (iris_bo_busy(cur
))
373 list_del(&cur
->head
);
375 /* Tell the kernel we need this BO. If it still exists, we're done! */
376 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
381 /* This BO was purged, throw it out and keep looking. */
388 /* If the cached BO isn't in the right memory zone, free the old
389 * memory and assign it a new address.
391 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
)) {
392 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
393 bo
->gtt_offset
= 0ull;
396 /* Zero the contents if necessary. If this fails, fall back to
397 * allocating a fresh BO, which will always be zeroed by the kernel.
399 if (flags
& BO_ALLOC_ZEROED
) {
400 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
402 memset(map
, 0, bo
->size
);
412 static struct iris_bo
*
413 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
415 struct iris_bo
*bo
= bo_calloc();
419 struct drm_i915_gem_create create
= { .size
= bo_size
};
421 /* All new BOs we get from the kernel are zeroed, so we don't need to
422 * worry about that here.
424 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
429 bo
->gem_handle
= create
.handle
;
433 bo
->tiling_mode
= I915_TILING_NONE
;
434 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
437 /* Calling set_domain() will allocate pages for the BO outside of the
438 * struct mutex lock in the kernel, which is more efficient than waiting
439 * to create them during the first execbuf that uses the BO.
441 struct drm_i915_gem_set_domain sd
= {
442 .handle
= bo
->gem_handle
,
443 .read_domains
= I915_GEM_DOMAIN_CPU
,
447 if (drm_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
455 static struct iris_bo
*
456 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
459 enum iris_memory_zone memzone
,
461 uint32_t tiling_mode
,
465 unsigned int page_size
= getpagesize();
466 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
468 /* Round the size up to the bucket size, or if we don't have caching
469 * at this size, a multiple of the page size.
472 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
474 mtx_lock(&bufmgr
->lock
);
476 /* Get a buffer out of the cache if available. First, we try to find
477 * one with a matching memory zone so we can avoid reallocating VMA.
479 bo
= alloc_bo_from_cache(bufmgr
, bucket
, memzone
, flags
, true);
481 /* If that fails, we try for any cached BO, without matching memzone. */
483 bo
= alloc_bo_from_cache(bufmgr
, bucket
, memzone
, flags
, false);
486 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
491 if (bo
->gtt_offset
== 0ull) {
492 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, 1);
494 if (bo
->gtt_offset
== 0ull)
498 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
501 mtx_unlock(&bufmgr
->lock
);
504 p_atomic_set(&bo
->refcount
, 1);
505 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
506 bo
->cache_coherent
= bufmgr
->has_llc
;
508 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
510 /* By default, capture all driver-internal buffers like shader kernels,
511 * surface states, dynamic states, border colors, and so on.
513 if (memzone
< IRIS_MEMZONE_OTHER
)
514 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
516 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
517 struct drm_i915_gem_caching arg
= {
518 .handle
= bo
->gem_handle
,
521 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
522 bo
->cache_coherent
= true;
523 bo
->reusable
= false;
527 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
528 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
535 mtx_unlock(&bufmgr
->lock
);
540 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
543 enum iris_memory_zone memzone
)
545 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
546 0, I915_TILING_NONE
, 0);
550 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
551 uint64_t size
, enum iris_memory_zone memzone
,
552 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
554 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
555 flags
, tiling_mode
, pitch
);
559 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
560 void *ptr
, size_t size
,
561 enum iris_memory_zone memzone
)
569 struct drm_i915_gem_userptr arg
= {
570 .user_ptr
= (uintptr_t)ptr
,
573 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
575 bo
->gem_handle
= arg
.handle
;
577 /* Check the buffer for validity before we try and use it in a batch */
578 struct drm_i915_gem_set_domain sd
= {
579 .handle
= bo
->gem_handle
,
580 .read_domains
= I915_GEM_DOMAIN_CPU
,
582 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
590 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
592 mtx_lock(&bufmgr
->lock
);
593 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
594 mtx_unlock(&bufmgr
->lock
);
596 if (bo
->gtt_offset
== 0ull)
599 p_atomic_set(&bo
->refcount
, 1);
601 bo
->cache_coherent
= true;
608 drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &bo
->gem_handle
);
615 * Returns a iris_bo wrapping the given buffer object handle.
617 * This can be used when one application needs to pass a buffer object
621 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
622 const char *name
, unsigned int handle
)
626 /* At the moment most applications only have a few named bo.
627 * For instance, in a DRI client only the render buffers passed
628 * between X and the client are named. And since X returns the
629 * alternating names for the front/back buffer a linear search
630 * provides a sufficiently fast match.
632 mtx_lock(&bufmgr
->lock
);
633 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
635 iris_bo_reference(bo
);
639 struct drm_gem_open open_arg
= { .name
= handle
};
640 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
642 DBG("Couldn't reference %s handle 0x%08x: %s\n",
643 name
, handle
, strerror(errno
));
647 /* Now see if someone has used a prime handle to get this
648 * object from the kernel before by looking through the list
649 * again for a matching gem_handle
651 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
653 iris_bo_reference(bo
);
661 p_atomic_set(&bo
->refcount
, 1);
663 bo
->size
= open_arg
.size
;
666 bo
->gem_handle
= open_arg
.handle
;
668 bo
->global_name
= handle
;
669 bo
->reusable
= false;
671 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
672 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
674 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
675 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
677 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
678 ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
682 bo
->tiling_mode
= get_tiling
.tiling_mode
;
683 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
684 /* XXX stride is unknown */
685 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
688 mtx_unlock(&bufmgr
->lock
);
693 mtx_unlock(&bufmgr
->lock
);
698 bo_free(struct iris_bo
*bo
)
700 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
702 if (bo
->map_cpu
&& !bo
->userptr
) {
703 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
704 munmap(bo
->map_cpu
, bo
->size
);
707 VG_NOACCESS(bo
->map_wc
, bo
->size
);
708 munmap(bo
->map_wc
, bo
->size
);
711 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
712 munmap(bo
->map_gtt
, bo
->size
);
716 struct hash_entry
*entry
;
718 if (bo
->global_name
) {
719 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
720 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
723 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
724 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
727 /* Close this object */
728 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
729 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
731 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
732 bo
->gem_handle
, bo
->name
, strerror(errno
));
735 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
740 /** Frees all cached buffers significantly older than @time. */
742 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
746 if (bufmgr
->time
== time
)
749 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
750 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
752 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
753 if (time
- bo
->free_time
<= 1)
766 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
768 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
769 struct bo_cache_bucket
*bucket
;
771 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
775 bucket
= bucket_for_size(bufmgr
, bo
->size
);
776 /* Put the buffer into our internal cache for reuse if we can. */
777 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
778 bo
->free_time
= time
;
781 list_addtail(&bo
->head
, &bucket
->head
);
788 iris_bo_unreference(struct iris_bo
*bo
)
793 assert(p_atomic_read(&bo
->refcount
) > 0);
795 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
796 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
797 struct timespec time
;
799 clock_gettime(CLOCK_MONOTONIC
, &time
);
801 mtx_lock(&bufmgr
->lock
);
803 if (p_atomic_dec_zero(&bo
->refcount
)) {
804 bo_unreference_final(bo
, time
.tv_sec
);
805 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
808 mtx_unlock(&bufmgr
->lock
);
813 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
817 bool busy
= dbg
&& !bo
->idle
;
818 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
820 iris_bo_wait_rendering(bo
);
822 if (unlikely(busy
)) {
823 elapsed
+= get_time();
824 if (elapsed
> 1e-5) /* 0.01ms */ {
825 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
826 action
, bo
->name
, elapsed
* 1000);
832 print_flags(unsigned flags
)
834 if (flags
& MAP_READ
)
836 if (flags
& MAP_WRITE
)
838 if (flags
& MAP_ASYNC
)
840 if (flags
& MAP_PERSISTENT
)
842 if (flags
& MAP_COHERENT
)
850 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
851 struct iris_bo
*bo
, unsigned flags
)
853 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
855 /* We disallow CPU maps for writing to non-coherent buffers, as the
856 * CPU map can become invalidated when a batch is flushed out, which
857 * can happen at unpredictable times. You should use WC maps instead.
859 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
862 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
864 struct drm_i915_gem_mmap mmap_arg
= {
865 .handle
= bo
->gem_handle
,
868 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
870 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
871 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
874 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
875 VG_DEFINED(map
, bo
->size
);
877 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
878 VG_NOACCESS(map
, bo
->size
);
879 munmap(map
, bo
->size
);
884 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
888 if (!(flags
& MAP_ASYNC
)) {
889 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
892 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
893 /* If we're reusing an existing CPU mapping, the CPU caches may
894 * contain stale data from the last time we read from that mapping.
895 * (With the BO cache, it might even be data from a previous buffer!)
896 * Even if it's a brand new mapping, the kernel may have zeroed the
897 * buffer via CPU writes.
899 * We need to invalidate those cachelines so that we see the latest
900 * contents, and so long as we only read from the CPU mmap we do not
901 * need to write those cachelines back afterwards.
903 * On LLC, the emprical evidence suggests that writes from the GPU
904 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
905 * cachelines. (Other reads, such as the display engine, bypass the
906 * LLC entirely requiring us to keep dirty pixels for the scanout
909 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
916 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
917 struct iris_bo
*bo
, unsigned flags
)
919 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
922 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
924 struct drm_i915_gem_mmap mmap_arg
= {
925 .handle
= bo
->gem_handle
,
927 .flags
= I915_MMAP_WC
,
929 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
931 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
932 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
936 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
937 VG_DEFINED(map
, bo
->size
);
939 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
940 VG_NOACCESS(map
, bo
->size
);
941 munmap(map
, bo
->size
);
946 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
949 if (!(flags
& MAP_ASYNC
)) {
950 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
957 * Perform an uncached mapping via the GTT.
959 * Write access through the GTT is not quite fully coherent. On low power
960 * systems especially, like modern Atoms, we can observe reads from RAM before
961 * the write via GTT has landed. A write memory barrier that flushes the Write
962 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
963 * read after the write as the GTT write suffers a small delay through the GTT
964 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
965 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
966 * flushes prior to execbuf submission. However, if we are not informing the
967 * kernel about our GTT writes, it will not flush before earlier access, such
968 * as when using the cmdparser. Similarly, we need to be careful if we should
969 * ever issue a CPU read immediately following a GTT write.
971 * Telling the kernel about write access also has one more important
972 * side-effect. Upon receiving notification about the write, it cancels any
973 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
974 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
975 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
976 * tracking is handled on the buffer exchange instead.
979 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
980 struct iris_bo
*bo
, unsigned flags
)
982 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
984 /* Get a mapping of the buffer if we haven't before. */
985 if (bo
->map_gtt
== NULL
) {
986 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
988 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
990 /* Get the fake offset back... */
991 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
993 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
994 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
999 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1000 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1001 if (map
== MAP_FAILED
) {
1002 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1003 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1007 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1008 * already intercept this mmap call. However, for consistency between
1009 * all the mmap paths, we mark the pointer as defined now and mark it
1010 * as inaccessible afterwards.
1012 VG_DEFINED(map
, bo
->size
);
1014 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1015 VG_NOACCESS(map
, bo
->size
);
1016 munmap(map
, bo
->size
);
1019 assert(bo
->map_gtt
);
1021 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1024 if (!(flags
& MAP_ASYNC
)) {
1025 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1032 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1034 if (bo
->cache_coherent
)
1037 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1038 * an LLC platform reads always are coherent (as they are performed via the
1039 * central system agent). It is just the writes that we need to take special
1040 * care to ensure that land in main memory and not stick in the CPU cache.
1042 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1045 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1046 * across batch flushes where the kernel will change cache domains of the
1047 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1049 * Similarly, ASYNC typically means that the buffer will be accessed via
1050 * both the CPU and the GPU simultaneously. Batches may be executed that
1051 * use the BO even while it is mapped. While OpenGL technically disallows
1052 * most drawing while non-persistent mappings are active, we may still use
1053 * the GPU for blits or other operations, causing batches to happen at
1054 * inconvenient times.
1056 * If RAW is set, we expect the caller to be able to handle a WC buffer
1057 * more efficiently than the involuntary clflushes.
1059 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1062 return !(flags
& MAP_WRITE
);
1066 iris_bo_map(struct pipe_debug_callback
*dbg
,
1067 struct iris_bo
*bo
, unsigned flags
)
1069 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1070 return iris_bo_map_gtt(dbg
, bo
, flags
);
1074 if (can_map_cpu(bo
, flags
))
1075 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1077 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1079 /* Allow the attempt to fail by falling back to the GTT where necessary.
1081 * Not every buffer can be mmaped directly using the CPU (or WC), for
1082 * example buffers that wrap stolen memory or are imported from other
1083 * devices. For those, we have little choice but to use a GTT mmapping.
1084 * However, if we use a slow GTT mmapping for reads where we expected fast
1085 * access, that order of magnitude difference in throughput will be clearly
1086 * expressed by angry users.
1088 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1090 if (!map
&& !(flags
& MAP_RAW
)) {
1091 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1093 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1099 /** Waits for all GPU rendering with the object to have completed. */
1101 iris_bo_wait_rendering(struct iris_bo
*bo
)
1103 /* We require a kernel recent enough for WAIT_IOCTL support.
1104 * See intel_init_bufmgr()
1106 iris_bo_wait(bo
, -1);
1110 * Waits on a BO for the given amount of time.
1112 * @bo: buffer object to wait for
1113 * @timeout_ns: amount of time to wait in nanoseconds.
1114 * If value is less than 0, an infinite wait will occur.
1116 * Returns 0 if the wait was successful ie. the last batch referencing the
1117 * object has completed within the allotted time. Otherwise some negative return
1118 * value describes the error. Of particular interest is -ETIME when the wait has
1119 * failed to yield the desired result.
1121 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1122 * the operation to give up after a certain amount of time. Another subtle
1123 * difference is the internal locking semantics are different (this variant does
1124 * not hold the lock for the duration of the wait). This makes the wait subject
1125 * to a larger userspace race window.
1127 * The implementation shall wait until the object is no longer actively
1128 * referenced within a batch buffer at the time of the call. The wait will
1129 * not guarantee that the buffer is re-issued via another thread, or an flinked
1130 * handle. Userspace must make sure this race does not occur if such precision
1133 * Note that some kernels have broken the inifite wait for negative values
1134 * promise, upgrade to latest stable kernels if this is the case.
1137 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1139 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1141 /* If we know it's idle, don't bother with the kernel round trip */
1142 if (bo
->idle
&& !bo
->external
)
1145 struct drm_i915_gem_wait wait
= {
1146 .bo_handle
= bo
->gem_handle
,
1147 .timeout_ns
= timeout_ns
,
1149 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1159 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1161 mtx_destroy(&bufmgr
->lock
);
1163 /* Free any cached buffer objects we were going to reuse */
1164 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1165 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1167 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1168 list_del(&bo
->head
);
1174 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1175 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1177 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1178 if (z
!= IRIS_MEMZONE_BINDER
)
1179 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1186 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1189 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1190 struct drm_i915_gem_set_tiling set_tiling
;
1193 if (bo
->global_name
== 0 &&
1194 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1197 memset(&set_tiling
, 0, sizeof(set_tiling
));
1199 /* set_tiling is slightly broken and overwrites the
1200 * input on the error path, so we have to open code
1203 set_tiling
.handle
= bo
->gem_handle
;
1204 set_tiling
.tiling_mode
= tiling_mode
;
1205 set_tiling
.stride
= stride
;
1207 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1208 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1212 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1213 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1214 bo
->stride
= set_tiling
.stride
;
1219 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1220 uint32_t *swizzle_mode
)
1222 *tiling_mode
= bo
->tiling_mode
;
1223 *swizzle_mode
= bo
->swizzle_mode
;
1228 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
)
1233 mtx_lock(&bufmgr
->lock
);
1234 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1236 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1238 mtx_unlock(&bufmgr
->lock
);
1243 * See if the kernel has already returned this buffer to us. Just as
1244 * for named buffers, we must not create two bo's pointing at the same
1247 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1249 iris_bo_reference(bo
);
1257 p_atomic_set(&bo
->refcount
, 1);
1259 /* Determine size of bo. The fd-to-handle ioctl really should
1260 * return the size, but it doesn't. If we have kernel 3.12 or
1261 * later, we can lseek on the prime fd to get the size. Older
1262 * kernels will just fail, in which case we fall back to the
1263 * provided (estimated or guess size). */
1264 ret
= lseek(prime_fd
, 0, SEEK_END
);
1268 bo
->bufmgr
= bufmgr
;
1270 bo
->gem_handle
= handle
;
1271 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1274 bo
->reusable
= false;
1275 bo
->external
= true;
1276 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1277 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1279 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1280 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1283 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1284 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1285 /* XXX stride is unknown */
1288 mtx_unlock(&bufmgr
->lock
);
1293 mtx_unlock(&bufmgr
->lock
);
1298 iris_bo_make_external_locked(struct iris_bo
*bo
)
1300 if (!bo
->external
) {
1301 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1302 bo
->external
= true;
1307 iris_bo_make_external(struct iris_bo
*bo
)
1309 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1314 mtx_lock(&bufmgr
->lock
);
1315 iris_bo_make_external_locked(bo
);
1316 mtx_unlock(&bufmgr
->lock
);
1320 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1322 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1324 iris_bo_make_external(bo
);
1326 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1327 DRM_CLOEXEC
, prime_fd
) != 0)
1330 bo
->reusable
= false;
1336 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1338 iris_bo_make_external(bo
);
1340 return bo
->gem_handle
;
1344 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1346 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1348 if (!bo
->global_name
) {
1349 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1351 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1354 mtx_lock(&bufmgr
->lock
);
1355 if (!bo
->global_name
) {
1356 iris_bo_make_external_locked(bo
);
1357 bo
->global_name
= flink
.name
;
1358 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1360 mtx_unlock(&bufmgr
->lock
);
1362 bo
->reusable
= false;
1365 *name
= bo
->global_name
;
1370 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1372 unsigned int i
= bufmgr
->num_buckets
;
1374 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1376 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1377 bufmgr
->cache_bucket
[i
].size
= size
;
1378 bufmgr
->num_buckets
++;
1380 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1381 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1382 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1386 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1388 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1390 /* OK, so power of two buckets was too wasteful of memory.
1391 * Give 3 other sizes between each power of two, to hopefully
1392 * cover things accurately enough. (The alternative is
1393 * probably to just go for exact matching of sizes, and assume
1394 * that for things like composited window resize the tiled
1395 * width/height alignment and rounding of sizes to pages will
1396 * get us useful cache hit rates anyway)
1398 add_bucket(bufmgr
, PAGE_SIZE
);
1399 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1400 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1402 /* Initialize the linked lists for BO reuse cache. */
1403 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1404 add_bucket(bufmgr
, size
);
1406 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1407 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1408 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1413 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1415 struct drm_i915_gem_context_create create
= { };
1416 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1418 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1422 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1423 * back to the default logical HW state and attempt to continue on to
1424 * our next submitted batchbuffer. However, our render batches assume
1425 * the previous GPU state is preserved, and only emit commands needed
1426 * to incrementally change that state. In particular, we inherit the
1427 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1428 * With default base addresses, our next batches will almost certainly
1429 * cause more GPU hangs, leading to repeated hangs until we're banned
1430 * or the machine is dead.
1432 * Here we tell the kernel not to attempt to recover our context but
1433 * immediately (on the next batchbuffer submission) report that the
1434 * context is lost, and we will do the recovery ourselves. Ideally,
1435 * we'll have two lost batches instead of a continual stream of hangs.
1437 struct drm_i915_gem_context_param p
= {
1438 .ctx_id
= create
.ctx_id
,
1439 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1442 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1444 return create
.ctx_id
;
1448 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1450 struct drm_i915_gem_context_param p
= {
1452 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1454 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1455 return p
.value
; /* on error, return 0 i.e. default priority */
1459 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1463 struct drm_i915_gem_context_param p
= {
1465 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1471 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1478 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1480 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1483 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1484 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1491 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1493 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1496 drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1497 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1503 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1505 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1506 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1508 *result
= reg_read
.val
;
1513 iris_gtt_size(int fd
)
1515 /* We use the default (already allocated) context to determine
1516 * the default configuration of the virtual address space.
1518 struct drm_i915_gem_context_param p
= {
1519 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1521 if (!drm_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1528 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1529 * and manage map buffer objections.
1531 * \param fd File descriptor of the opened DRM device.
1533 struct iris_bufmgr
*
1534 iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
)
1536 uint64_t gtt_size
= iris_gtt_size(fd
);
1537 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1540 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1544 /* Handles to buffer objects belong to the device fd and are not
1545 * reference counted by the kernel. If the same fd is used by
1546 * multiple parties (threads sharing the same screen bufmgr, or
1547 * even worse the same device fd passed to multiple libraries)
1548 * ownership of those handles is shared by those independent parties.
1550 * Don't do this! Ensure that each library/bufmgr has its own device
1551 * fd so that its namespace does not clash with another.
1555 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1560 bufmgr
->has_llc
= devinfo
->has_llc
;
1562 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1563 const uint64_t _4GB
= 1ull << 32;
1565 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1566 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1568 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1569 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1570 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1571 IRIS_MEMZONE_SURFACE_START
,
1572 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1573 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1574 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1575 _4GB_minus_1
- IRIS_BORDER_COLOR_POOL_SIZE
);
1577 /* Leave the last 4GB out of the high vma range, so that no state
1578 * base address + size can overflow 48 bits.
1580 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1581 IRIS_MEMZONE_OTHER_START
,
1582 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1585 bufmgr
->bo_reuse
= env_var_as_boolean("bo_reuse", true);
1587 init_cache_buckets(bufmgr
);
1589 bufmgr
->name_table
=
1590 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1591 bufmgr
->handle_table
=
1592 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);