2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
49 #include <sys/types.h>
54 #include "common/gen_clflush.h"
55 #include "dev/gen_debug.h"
56 #include "common/gen_gem.h"
57 #include "dev/gen_device_info.h"
58 #include "main/macros.h"
59 #include "util/debug.h"
60 #include "util/macros.h"
61 #include "util/hash_table.h"
62 #include "util/list.h"
63 #include "util/u_dynarray.h"
65 #include "iris_bufmgr.h"
66 #include "iris_context.h"
69 #include "drm-uapi/i915_drm.h"
79 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
80 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
81 * leaked. All because it does not call VG(cli_free) from its
82 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
83 * and allocation, we mark it available for use upon mmapping and remove
86 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
87 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
89 #define PAGE_SIZE 4096
91 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
94 atomic_add_unless(int *v
, int add
, int unless
)
98 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
104 memzone_name(enum iris_memory_zone memzone
)
106 const char *names
[] = {
107 [IRIS_MEMZONE_SHADER
] = "shader",
108 [IRIS_MEMZONE_BINDER
] = "binder",
109 [IRIS_MEMZONE_SURFACE
] = "surface",
110 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
111 [IRIS_MEMZONE_OTHER
] = "other",
112 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
114 assert(memzone
< ARRAY_SIZE(names
));
115 return names
[memzone
];
118 struct bo_cache_bucket
{
119 /** List of cached BOs. */
120 struct list_head head
;
122 /** Size of this bucket, in bytes. */
131 /** Array of lists of cached gem objects of power-of-two sizes */
132 struct bo_cache_bucket cache_bucket
[14 * 4];
136 struct hash_table
*name_table
;
137 struct hash_table
*handle_table
;
140 * List of BOs which we've effectively freed, but are hanging on to
141 * until they're idle before closing and returning the VMA.
143 struct list_head zombie_list
;
145 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
151 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
154 static void bo_free(struct iris_bo
*bo
);
156 static uint64_t vma_alloc(struct iris_bufmgr
*bufmgr
,
157 enum iris_memory_zone memzone
,
158 uint64_t size
, uint64_t alignment
);
161 key_hash_uint(const void *key
)
163 return _mesa_hash_data(key
, 4);
167 key_uint_equal(const void *a
, const void *b
)
169 return *((unsigned *) a
) == *((unsigned *) b
);
172 static struct iris_bo
*
173 find_and_ref_external_bo(struct hash_table
*ht
, unsigned int key
)
175 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
176 struct iris_bo
*bo
= entry
? entry
->data
: NULL
;
179 assert(bo
->external
);
180 assert(!bo
->reusable
);
182 /* Being non-reusable, the BO cannot be in the cache lists, but it
183 * may be in the zombie list if it had reached zero references, but
184 * we hadn't yet closed it...and then reimported the same BO. If it
185 * is, then remove it since it's now been resurrected.
187 if (bo
->head
.prev
|| bo
->head
.next
)
190 iris_bo_reference(bo
);
197 * This function finds the correct bucket fit for the input size.
198 * The function works with O(1) complexity when the requested size
199 * was queried instead of iterating the size through all the buckets.
201 static struct bo_cache_bucket
*
202 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
204 /* Calculating the pages and rounding up to the page size. */
205 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
207 /* Row Bucket sizes clz((x-1) | 3) Row Column
208 * in pages stride size
209 * 0: 1 2 3 4 -> 30 30 30 30 4 1
210 * 1: 5 6 7 8 -> 29 29 29 29 4 1
211 * 2: 10 12 14 16 -> 28 28 28 28 8 2
212 * 3: 20 24 28 32 -> 27 27 27 27 16 4
214 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
215 const unsigned row_max_pages
= 4 << row
;
217 /* The '& ~2' is the special case for row 1. In row 1, max pages /
218 * 2 is 2, but the previous row maximum is zero (because there is
219 * no previous row). All row maximum sizes are power of 2, so that
220 * is the only case where that bit will be set.
222 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
223 int col_size_log2
= row
- 1;
224 col_size_log2
+= (col_size_log2
< 0);
226 const unsigned col
= (pages
- prev_row_max_pages
+
227 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
229 /* Calculating the index based on the row and column. */
230 const unsigned index
= (row
* 4) + (col
- 1);
232 return (index
< bufmgr
->num_buckets
) ?
233 &bufmgr
->cache_bucket
[index
] : NULL
;
236 enum iris_memory_zone
237 iris_memzone_for_address(uint64_t address
)
239 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
240 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
241 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
242 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
243 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
245 if (address
>= IRIS_MEMZONE_OTHER_START
)
246 return IRIS_MEMZONE_OTHER
;
248 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
249 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
251 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
252 return IRIS_MEMZONE_DYNAMIC
;
254 if (address
>= IRIS_MEMZONE_SURFACE_START
)
255 return IRIS_MEMZONE_SURFACE
;
257 if (address
>= IRIS_MEMZONE_BINDER_START
)
258 return IRIS_MEMZONE_BINDER
;
260 return IRIS_MEMZONE_SHADER
;
264 * Allocate a section of virtual memory for a buffer, assigning an address.
266 * This uses either the bucket allocator for the given size, or the large
267 * object allocator (util_vma).
270 vma_alloc(struct iris_bufmgr
*bufmgr
,
271 enum iris_memory_zone memzone
,
275 /* Force alignment to be some number of pages */
276 alignment
= ALIGN(alignment
, PAGE_SIZE
);
278 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
279 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
281 /* The binder handles its own allocations. Return non-zero here. */
282 if (memzone
== IRIS_MEMZONE_BINDER
)
283 return IRIS_MEMZONE_BINDER_START
;
286 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
288 assert((addr
>> 48ull) == 0);
289 assert((addr
% alignment
) == 0);
291 return gen_canonical_address(addr
);
295 vma_free(struct iris_bufmgr
*bufmgr
,
299 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
302 /* Un-canonicalize the address. */
303 address
= gen_48b_address(address
);
308 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
310 /* The binder handles its own allocations. */
311 if (memzone
== IRIS_MEMZONE_BINDER
)
314 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
318 iris_bo_busy(struct iris_bo
*bo
)
320 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
321 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
323 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
325 bo
->idle
= !busy
.busy
;
332 iris_bo_madvise(struct iris_bo
*bo
, int state
)
334 struct drm_i915_gem_madvise madv
= {
335 .handle
= bo
->gem_handle
,
340 gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
342 return madv
.retained
;
345 static struct iris_bo
*
348 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
350 bo
->hash
= _mesa_hash_pointer(bo
);
355 static struct iris_bo
*
356 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
357 struct bo_cache_bucket
*bucket
,
359 enum iris_memory_zone memzone
,
366 struct iris_bo
*bo
= NULL
;
368 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
369 /* Try a little harder to find one that's already in the right memzone */
370 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
373 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
374 * either falling back to a non-matching memzone, or if that fails,
375 * allocating a fresh buffer.
377 if (iris_bo_busy(cur
))
380 list_del(&cur
->head
);
382 /* Tell the kernel we need this BO. If it still exists, we're done! */
383 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
388 /* This BO was purged, throw it out and keep looking. */
395 /* If the cached BO isn't in the right memory zone, or the alignment
396 * isn't sufficient, free the old memory and assign it a new address.
398 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
) ||
399 bo
->gtt_offset
% alignment
!= 0) {
400 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
401 bo
->gtt_offset
= 0ull;
404 /* Zero the contents if necessary. If this fails, fall back to
405 * allocating a fresh BO, which will always be zeroed by the kernel.
407 if (flags
& BO_ALLOC_ZEROED
) {
408 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
410 memset(map
, 0, bo
->size
);
420 static struct iris_bo
*
421 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
423 struct iris_bo
*bo
= bo_calloc();
427 struct drm_i915_gem_create create
= { .size
= bo_size
};
429 /* All new BOs we get from the kernel are zeroed, so we don't need to
430 * worry about that here.
432 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
437 bo
->gem_handle
= create
.handle
;
441 bo
->tiling_mode
= I915_TILING_NONE
;
442 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
445 /* Calling set_domain() will allocate pages for the BO outside of the
446 * struct mutex lock in the kernel, which is more efficient than waiting
447 * to create them during the first execbuf that uses the BO.
449 struct drm_i915_gem_set_domain sd
= {
450 .handle
= bo
->gem_handle
,
451 .read_domains
= I915_GEM_DOMAIN_CPU
,
455 if (gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
463 static struct iris_bo
*
464 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
468 enum iris_memory_zone memzone
,
470 uint32_t tiling_mode
,
474 unsigned int page_size
= getpagesize();
475 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
477 /* Round the size up to the bucket size, or if we don't have caching
478 * at this size, a multiple of the page size.
481 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
483 mtx_lock(&bufmgr
->lock
);
485 /* Get a buffer out of the cache if available. First, we try to find
486 * one with a matching memory zone so we can avoid reallocating VMA.
488 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
, true);
490 /* If that fails, we try for any cached BO, without matching memzone. */
492 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
,
496 mtx_unlock(&bufmgr
->lock
);
499 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
504 if (bo
->gtt_offset
== 0ull) {
505 mtx_lock(&bufmgr
->lock
);
506 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, alignment
);
507 mtx_unlock(&bufmgr
->lock
);
509 if (bo
->gtt_offset
== 0ull)
513 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
517 p_atomic_set(&bo
->refcount
, 1);
518 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
519 bo
->cache_coherent
= bufmgr
->has_llc
;
521 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
523 /* By default, capture all driver-internal buffers like shader kernels,
524 * surface states, dynamic states, border colors, and so on.
526 if (memzone
< IRIS_MEMZONE_OTHER
)
527 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
529 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
530 struct drm_i915_gem_caching arg
= {
531 .handle
= bo
->gem_handle
,
534 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
535 bo
->cache_coherent
= true;
536 bo
->reusable
= false;
540 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
541 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
551 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
554 enum iris_memory_zone memzone
)
556 return bo_alloc_internal(bufmgr
, name
, size
, 1, memzone
,
557 0, I915_TILING_NONE
, 0);
561 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
562 uint64_t size
, uint32_t alignment
,
563 enum iris_memory_zone memzone
,
564 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
566 return bo_alloc_internal(bufmgr
, name
, size
, alignment
, memzone
,
567 flags
, tiling_mode
, pitch
);
571 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
572 void *ptr
, size_t size
,
573 enum iris_memory_zone memzone
)
581 struct drm_i915_gem_userptr arg
= {
582 .user_ptr
= (uintptr_t)ptr
,
585 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
587 bo
->gem_handle
= arg
.handle
;
589 /* Check the buffer for validity before we try and use it in a batch */
590 struct drm_i915_gem_set_domain sd
= {
591 .handle
= bo
->gem_handle
,
592 .read_domains
= I915_GEM_DOMAIN_CPU
,
594 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
602 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
604 mtx_lock(&bufmgr
->lock
);
605 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
606 mtx_unlock(&bufmgr
->lock
);
608 if (bo
->gtt_offset
== 0ull)
611 p_atomic_set(&bo
->refcount
, 1);
613 bo
->cache_coherent
= true;
620 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &bo
->gem_handle
);
627 * Returns a iris_bo wrapping the given buffer object handle.
629 * This can be used when one application needs to pass a buffer object
633 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
634 const char *name
, unsigned int handle
)
638 /* At the moment most applications only have a few named bo.
639 * For instance, in a DRI client only the render buffers passed
640 * between X and the client are named. And since X returns the
641 * alternating names for the front/back buffer a linear search
642 * provides a sufficiently fast match.
644 mtx_lock(&bufmgr
->lock
);
645 bo
= find_and_ref_external_bo(bufmgr
->name_table
, handle
);
649 struct drm_gem_open open_arg
= { .name
= handle
};
650 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
652 DBG("Couldn't reference %s handle 0x%08x: %s\n",
653 name
, handle
, strerror(errno
));
657 /* Now see if someone has used a prime handle to get this
658 * object from the kernel before by looking through the list
659 * again for a matching gem_handle
661 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, open_arg
.handle
);
669 p_atomic_set(&bo
->refcount
, 1);
671 bo
->size
= open_arg
.size
;
674 bo
->gem_handle
= open_arg
.handle
;
676 bo
->global_name
= handle
;
677 bo
->reusable
= false;
679 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
680 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
682 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
683 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
685 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
686 ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
690 bo
->tiling_mode
= get_tiling
.tiling_mode
;
691 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
692 /* XXX stride is unknown */
693 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
696 mtx_unlock(&bufmgr
->lock
);
701 mtx_unlock(&bufmgr
->lock
);
706 bo_close(struct iris_bo
*bo
)
708 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
711 struct hash_entry
*entry
;
713 if (bo
->global_name
) {
714 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
715 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
718 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
719 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
722 /* Close this object */
723 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
724 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
726 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
727 bo
->gem_handle
, bo
->name
, strerror(errno
));
730 /* Return the VMA for reuse */
731 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
737 bo_free(struct iris_bo
*bo
)
739 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
741 if (bo
->map_cpu
&& !bo
->userptr
) {
742 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
743 munmap(bo
->map_cpu
, bo
->size
);
746 VG_NOACCESS(bo
->map_wc
, bo
->size
);
747 munmap(bo
->map_wc
, bo
->size
);
750 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
751 munmap(bo
->map_gtt
, bo
->size
);
757 /* Defer closing the GEM BO and returning the VMA for reuse until the
758 * BO is idle. Just move it to the dead list for now.
760 list_addtail(&bo
->head
, &bufmgr
->zombie_list
);
764 /** Frees all cached buffers significantly older than @time. */
766 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
770 if (bufmgr
->time
== time
)
773 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
774 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
776 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
777 if (time
- bo
->free_time
<= 1)
786 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
787 /* Stop once we reach a busy BO - all others past this point were
788 * freed more recently so are likely also busy.
790 if (!bo
->idle
&& iris_bo_busy(bo
))
801 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
803 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
804 struct bo_cache_bucket
*bucket
;
806 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
810 bucket
= bucket_for_size(bufmgr
, bo
->size
);
811 /* Put the buffer into our internal cache for reuse if we can. */
812 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
813 bo
->free_time
= time
;
816 list_addtail(&bo
->head
, &bucket
->head
);
823 iris_bo_unreference(struct iris_bo
*bo
)
828 assert(p_atomic_read(&bo
->refcount
) > 0);
830 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
831 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
832 struct timespec time
;
834 clock_gettime(CLOCK_MONOTONIC
, &time
);
836 mtx_lock(&bufmgr
->lock
);
838 if (p_atomic_dec_zero(&bo
->refcount
)) {
839 bo_unreference_final(bo
, time
.tv_sec
);
840 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
843 mtx_unlock(&bufmgr
->lock
);
848 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
852 bool busy
= dbg
&& !bo
->idle
;
853 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
855 iris_bo_wait_rendering(bo
);
857 if (unlikely(busy
)) {
858 elapsed
+= get_time();
859 if (elapsed
> 1e-5) /* 0.01ms */ {
860 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
861 action
, bo
->name
, elapsed
* 1000);
867 print_flags(unsigned flags
)
869 if (flags
& MAP_READ
)
871 if (flags
& MAP_WRITE
)
873 if (flags
& MAP_ASYNC
)
875 if (flags
& MAP_PERSISTENT
)
877 if (flags
& MAP_COHERENT
)
885 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
886 struct iris_bo
*bo
, unsigned flags
)
888 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
890 /* We disallow CPU maps for writing to non-coherent buffers, as the
891 * CPU map can become invalidated when a batch is flushed out, which
892 * can happen at unpredictable times. You should use WC maps instead.
894 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
897 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
899 struct drm_i915_gem_mmap mmap_arg
= {
900 .handle
= bo
->gem_handle
,
903 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
905 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
906 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
909 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
910 VG_DEFINED(map
, bo
->size
);
912 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
913 VG_NOACCESS(map
, bo
->size
);
914 munmap(map
, bo
->size
);
919 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
923 if (!(flags
& MAP_ASYNC
)) {
924 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
927 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
928 /* If we're reusing an existing CPU mapping, the CPU caches may
929 * contain stale data from the last time we read from that mapping.
930 * (With the BO cache, it might even be data from a previous buffer!)
931 * Even if it's a brand new mapping, the kernel may have zeroed the
932 * buffer via CPU writes.
934 * We need to invalidate those cachelines so that we see the latest
935 * contents, and so long as we only read from the CPU mmap we do not
936 * need to write those cachelines back afterwards.
938 * On LLC, the emprical evidence suggests that writes from the GPU
939 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
940 * cachelines. (Other reads, such as the display engine, bypass the
941 * LLC entirely requiring us to keep dirty pixels for the scanout
944 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
951 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
952 struct iris_bo
*bo
, unsigned flags
)
954 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
957 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
959 struct drm_i915_gem_mmap mmap_arg
= {
960 .handle
= bo
->gem_handle
,
962 .flags
= I915_MMAP_WC
,
964 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
966 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
967 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
971 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
972 VG_DEFINED(map
, bo
->size
);
974 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
975 VG_NOACCESS(map
, bo
->size
);
976 munmap(map
, bo
->size
);
981 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
984 if (!(flags
& MAP_ASYNC
)) {
985 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
992 * Perform an uncached mapping via the GTT.
994 * Write access through the GTT is not quite fully coherent. On low power
995 * systems especially, like modern Atoms, we can observe reads from RAM before
996 * the write via GTT has landed. A write memory barrier that flushes the Write
997 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
998 * read after the write as the GTT write suffers a small delay through the GTT
999 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1000 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1001 * flushes prior to execbuf submission. However, if we are not informing the
1002 * kernel about our GTT writes, it will not flush before earlier access, such
1003 * as when using the cmdparser. Similarly, we need to be careful if we should
1004 * ever issue a CPU read immediately following a GTT write.
1006 * Telling the kernel about write access also has one more important
1007 * side-effect. Upon receiving notification about the write, it cancels any
1008 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1009 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1010 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1011 * tracking is handled on the buffer exchange instead.
1014 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1015 struct iris_bo
*bo
, unsigned flags
)
1017 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1019 /* Get a mapping of the buffer if we haven't before. */
1020 if (bo
->map_gtt
== NULL
) {
1021 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1023 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1025 /* Get the fake offset back... */
1026 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1028 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1029 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1034 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1035 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1036 if (map
== MAP_FAILED
) {
1037 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1038 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1042 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1043 * already intercept this mmap call. However, for consistency between
1044 * all the mmap paths, we mark the pointer as defined now and mark it
1045 * as inaccessible afterwards.
1047 VG_DEFINED(map
, bo
->size
);
1049 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1050 VG_NOACCESS(map
, bo
->size
);
1051 munmap(map
, bo
->size
);
1054 assert(bo
->map_gtt
);
1056 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1059 if (!(flags
& MAP_ASYNC
)) {
1060 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1067 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1069 if (bo
->cache_coherent
)
1072 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1073 * an LLC platform reads always are coherent (as they are performed via the
1074 * central system agent). It is just the writes that we need to take special
1075 * care to ensure that land in main memory and not stick in the CPU cache.
1077 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1080 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1081 * across batch flushes where the kernel will change cache domains of the
1082 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1084 * Similarly, ASYNC typically means that the buffer will be accessed via
1085 * both the CPU and the GPU simultaneously. Batches may be executed that
1086 * use the BO even while it is mapped. While OpenGL technically disallows
1087 * most drawing while non-persistent mappings are active, we may still use
1088 * the GPU for blits or other operations, causing batches to happen at
1089 * inconvenient times.
1091 * If RAW is set, we expect the caller to be able to handle a WC buffer
1092 * more efficiently than the involuntary clflushes.
1094 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1097 return !(flags
& MAP_WRITE
);
1101 iris_bo_map(struct pipe_debug_callback
*dbg
,
1102 struct iris_bo
*bo
, unsigned flags
)
1104 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1105 return iris_bo_map_gtt(dbg
, bo
, flags
);
1109 if (can_map_cpu(bo
, flags
))
1110 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1112 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1114 /* Allow the attempt to fail by falling back to the GTT where necessary.
1116 * Not every buffer can be mmaped directly using the CPU (or WC), for
1117 * example buffers that wrap stolen memory or are imported from other
1118 * devices. For those, we have little choice but to use a GTT mmapping.
1119 * However, if we use a slow GTT mmapping for reads where we expected fast
1120 * access, that order of magnitude difference in throughput will be clearly
1121 * expressed by angry users.
1123 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1125 if (!map
&& !(flags
& MAP_RAW
)) {
1126 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1128 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1134 /** Waits for all GPU rendering with the object to have completed. */
1136 iris_bo_wait_rendering(struct iris_bo
*bo
)
1138 /* We require a kernel recent enough for WAIT_IOCTL support.
1139 * See intel_init_bufmgr()
1141 iris_bo_wait(bo
, -1);
1145 * Waits on a BO for the given amount of time.
1147 * @bo: buffer object to wait for
1148 * @timeout_ns: amount of time to wait in nanoseconds.
1149 * If value is less than 0, an infinite wait will occur.
1151 * Returns 0 if the wait was successful ie. the last batch referencing the
1152 * object has completed within the allotted time. Otherwise some negative return
1153 * value describes the error. Of particular interest is -ETIME when the wait has
1154 * failed to yield the desired result.
1156 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1157 * the operation to give up after a certain amount of time. Another subtle
1158 * difference is the internal locking semantics are different (this variant does
1159 * not hold the lock for the duration of the wait). This makes the wait subject
1160 * to a larger userspace race window.
1162 * The implementation shall wait until the object is no longer actively
1163 * referenced within a batch buffer at the time of the call. The wait will
1164 * not guarantee that the buffer is re-issued via another thread, or an flinked
1165 * handle. Userspace must make sure this race does not occur if such precision
1168 * Note that some kernels have broken the inifite wait for negative values
1169 * promise, upgrade to latest stable kernels if this is the case.
1172 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1174 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1176 /* If we know it's idle, don't bother with the kernel round trip */
1177 if (bo
->idle
&& !bo
->external
)
1180 struct drm_i915_gem_wait wait
= {
1181 .bo_handle
= bo
->gem_handle
,
1182 .timeout_ns
= timeout_ns
,
1184 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1194 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1196 mtx_destroy(&bufmgr
->lock
);
1198 /* Free any cached buffer objects we were going to reuse */
1199 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1200 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1202 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1203 list_del(&bo
->head
);
1209 /* Close any buffer objects on the dead list. */
1210 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
1211 list_del(&bo
->head
);
1215 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1216 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1218 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1219 if (z
!= IRIS_MEMZONE_BINDER
)
1220 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1227 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1230 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1231 struct drm_i915_gem_set_tiling set_tiling
;
1234 if (bo
->global_name
== 0 &&
1235 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1238 memset(&set_tiling
, 0, sizeof(set_tiling
));
1240 /* set_tiling is slightly broken and overwrites the
1241 * input on the error path, so we have to open code
1244 set_tiling
.handle
= bo
->gem_handle
;
1245 set_tiling
.tiling_mode
= tiling_mode
;
1246 set_tiling
.stride
= stride
;
1248 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1249 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1253 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1254 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1255 bo
->stride
= set_tiling
.stride
;
1260 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1261 uint32_t *swizzle_mode
)
1263 *tiling_mode
= bo
->tiling_mode
;
1264 *swizzle_mode
= bo
->swizzle_mode
;
1269 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
)
1274 mtx_lock(&bufmgr
->lock
);
1275 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1277 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1279 mtx_unlock(&bufmgr
->lock
);
1284 * See if the kernel has already returned this buffer to us. Just as
1285 * for named buffers, we must not create two bo's pointing at the same
1288 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, handle
);
1296 p_atomic_set(&bo
->refcount
, 1);
1298 /* Determine size of bo. The fd-to-handle ioctl really should
1299 * return the size, but it doesn't. If we have kernel 3.12 or
1300 * later, we can lseek on the prime fd to get the size. Older
1301 * kernels will just fail, in which case we fall back to the
1302 * provided (estimated or guess size). */
1303 ret
= lseek(prime_fd
, 0, SEEK_END
);
1307 bo
->bufmgr
= bufmgr
;
1309 bo
->reusable
= false;
1310 bo
->external
= true;
1311 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1312 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1313 bo
->gem_handle
= handle
;
1314 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1316 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1317 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1320 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1321 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1322 /* XXX stride is unknown */
1325 mtx_unlock(&bufmgr
->lock
);
1330 mtx_unlock(&bufmgr
->lock
);
1335 iris_bo_make_external_locked(struct iris_bo
*bo
)
1337 if (!bo
->external
) {
1338 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1339 bo
->external
= true;
1340 bo
->reusable
= false;
1345 iris_bo_make_external(struct iris_bo
*bo
)
1347 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1350 assert(!bo
->reusable
);
1354 mtx_lock(&bufmgr
->lock
);
1355 iris_bo_make_external_locked(bo
);
1356 mtx_unlock(&bufmgr
->lock
);
1360 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1362 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1364 iris_bo_make_external(bo
);
1366 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1367 DRM_CLOEXEC
, prime_fd
) != 0)
1374 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1376 iris_bo_make_external(bo
);
1378 return bo
->gem_handle
;
1382 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1384 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1386 if (!bo
->global_name
) {
1387 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1389 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1392 mtx_lock(&bufmgr
->lock
);
1393 if (!bo
->global_name
) {
1394 iris_bo_make_external_locked(bo
);
1395 bo
->global_name
= flink
.name
;
1396 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1398 mtx_unlock(&bufmgr
->lock
);
1401 *name
= bo
->global_name
;
1406 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1408 unsigned int i
= bufmgr
->num_buckets
;
1410 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1412 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1413 bufmgr
->cache_bucket
[i
].size
= size
;
1414 bufmgr
->num_buckets
++;
1416 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1417 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1418 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1422 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1424 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1426 /* OK, so power of two buckets was too wasteful of memory.
1427 * Give 3 other sizes between each power of two, to hopefully
1428 * cover things accurately enough. (The alternative is
1429 * probably to just go for exact matching of sizes, and assume
1430 * that for things like composited window resize the tiled
1431 * width/height alignment and rounding of sizes to pages will
1432 * get us useful cache hit rates anyway)
1434 add_bucket(bufmgr
, PAGE_SIZE
);
1435 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1436 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1438 /* Initialize the linked lists for BO reuse cache. */
1439 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1440 add_bucket(bufmgr
, size
);
1442 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1443 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1444 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1449 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1451 struct drm_i915_gem_context_create create
= { };
1452 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1454 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1458 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1459 * back to the default logical HW state and attempt to continue on to
1460 * our next submitted batchbuffer. However, our render batches assume
1461 * the previous GPU state is preserved, and only emit commands needed
1462 * to incrementally change that state. In particular, we inherit the
1463 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1464 * With default base addresses, our next batches will almost certainly
1465 * cause more GPU hangs, leading to repeated hangs until we're banned
1466 * or the machine is dead.
1468 * Here we tell the kernel not to attempt to recover our context but
1469 * immediately (on the next batchbuffer submission) report that the
1470 * context is lost, and we will do the recovery ourselves. Ideally,
1471 * we'll have two lost batches instead of a continual stream of hangs.
1473 struct drm_i915_gem_context_param p
= {
1474 .ctx_id
= create
.ctx_id
,
1475 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1478 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1480 return create
.ctx_id
;
1484 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1486 struct drm_i915_gem_context_param p
= {
1488 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1490 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1491 return p
.value
; /* on error, return 0 i.e. default priority */
1495 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1499 struct drm_i915_gem_context_param p
= {
1501 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1507 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1514 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1516 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1519 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1520 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1527 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1529 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1532 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1533 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1539 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1541 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1542 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1544 *result
= reg_read
.val
;
1549 iris_gtt_size(int fd
)
1551 /* We use the default (already allocated) context to determine
1552 * the default configuration of the virtual address space.
1554 struct drm_i915_gem_context_param p
= {
1555 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1557 if (!gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1564 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1565 * and manage map buffer objections.
1567 * \param fd File descriptor of the opened DRM device.
1569 struct iris_bufmgr
*
1570 iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1572 uint64_t gtt_size
= iris_gtt_size(fd
);
1573 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1576 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1580 /* Handles to buffer objects belong to the device fd and are not
1581 * reference counted by the kernel. If the same fd is used by
1582 * multiple parties (threads sharing the same screen bufmgr, or
1583 * even worse the same device fd passed to multiple libraries)
1584 * ownership of those handles is shared by those independent parties.
1586 * Don't do this! Ensure that each library/bufmgr has its own device
1587 * fd so that its namespace does not clash with another.
1591 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1596 list_inithead(&bufmgr
->zombie_list
);
1598 bufmgr
->has_llc
= devinfo
->has_llc
;
1599 bufmgr
->bo_reuse
= bo_reuse
;
1601 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1602 const uint64_t _4GB
= 1ull << 32;
1604 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1605 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1607 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1608 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1609 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1610 IRIS_MEMZONE_SURFACE_START
,
1611 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1612 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1613 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1614 _4GB_minus_1
- IRIS_BORDER_COLOR_POOL_SIZE
);
1616 /* Leave the last 4GB out of the high vma range, so that no state
1617 * base address + size can overflow 48 bits.
1619 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1620 IRIS_MEMZONE_OTHER_START
,
1621 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1623 init_cache_buckets(bufmgr
);
1625 bufmgr
->name_table
=
1626 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1627 bufmgr
->handle_table
=
1628 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);