2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
49 #include <sys/types.h>
55 #include "common/gen_aux_map.h"
56 #include "common/gen_clflush.h"
57 #include "dev/gen_debug.h"
58 #include "common/gen_gem.h"
59 #include "dev/gen_device_info.h"
60 #include "main/macros.h"
61 #include "os/os_mman.h"
62 #include "util/debug.h"
63 #include "util/macros.h"
64 #include "util/hash_table.h"
65 #include "util/list.h"
66 #include "util/u_dynarray.h"
68 #include "iris_bufmgr.h"
69 #include "iris_context.h"
72 #include "drm-uapi/i915_drm.h"
82 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
83 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
84 * leaked. All because it does not call VG(cli_free) from its
85 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
86 * and allocation, we mark it available for use upon mmapping and remove
89 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
90 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
92 #define PAGE_SIZE 4096
94 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
97 atomic_add_unless(int *v
, int add
, int unless
)
100 c
= p_atomic_read(v
);
101 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
107 memzone_name(enum iris_memory_zone memzone
)
109 const char *names
[] = {
110 [IRIS_MEMZONE_SHADER
] = "shader",
111 [IRIS_MEMZONE_BINDER
] = "binder",
112 [IRIS_MEMZONE_SURFACE
] = "surface",
113 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
114 [IRIS_MEMZONE_OTHER
] = "other",
115 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
117 assert(memzone
< ARRAY_SIZE(names
));
118 return names
[memzone
];
121 struct bo_cache_bucket
{
122 /** List of cached BOs. */
123 struct list_head head
;
125 /** Size of this bucket, in bytes. */
131 * List into the list of bufmgr.
133 struct list_head link
;
141 /** Array of lists of cached gem objects of power-of-two sizes */
142 struct bo_cache_bucket cache_bucket
[14 * 4];
146 struct hash_table
*name_table
;
147 struct hash_table
*handle_table
;
150 * List of BOs which we've effectively freed, but are hanging on to
151 * until they're idle before closing and returning the VMA.
153 struct list_head zombie_list
;
155 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
160 struct gen_aux_map_context
*aux_map_ctx
;
163 static mtx_t global_bufmgr_list_mutex
= _MTX_INITIALIZER_NP
;
164 static struct list_head global_bufmgr_list
= {
165 .next
= &global_bufmgr_list
,
166 .prev
= &global_bufmgr_list
,
169 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
172 static void bo_free(struct iris_bo
*bo
);
174 static struct iris_bo
*
175 find_and_ref_external_bo(struct hash_table
*ht
, unsigned int key
)
177 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
178 struct iris_bo
*bo
= entry
? entry
->data
: NULL
;
181 assert(bo
->external
);
182 assert(!bo
->reusable
);
184 /* Being non-reusable, the BO cannot be in the cache lists, but it
185 * may be in the zombie list if it had reached zero references, but
186 * we hadn't yet closed it...and then reimported the same BO. If it
187 * is, then remove it since it's now been resurrected.
189 if (bo
->head
.prev
|| bo
->head
.next
)
192 iris_bo_reference(bo
);
199 * This function finds the correct bucket fit for the input size.
200 * The function works with O(1) complexity when the requested size
201 * was queried instead of iterating the size through all the buckets.
203 static struct bo_cache_bucket
*
204 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
206 /* Calculating the pages and rounding up to the page size. */
207 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
209 /* Row Bucket sizes clz((x-1) | 3) Row Column
210 * in pages stride size
211 * 0: 1 2 3 4 -> 30 30 30 30 4 1
212 * 1: 5 6 7 8 -> 29 29 29 29 4 1
213 * 2: 10 12 14 16 -> 28 28 28 28 8 2
214 * 3: 20 24 28 32 -> 27 27 27 27 16 4
216 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
217 const unsigned row_max_pages
= 4 << row
;
219 /* The '& ~2' is the special case for row 1. In row 1, max pages /
220 * 2 is 2, but the previous row maximum is zero (because there is
221 * no previous row). All row maximum sizes are power of 2, so that
222 * is the only case where that bit will be set.
224 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
225 int col_size_log2
= row
- 1;
226 col_size_log2
+= (col_size_log2
< 0);
228 const unsigned col
= (pages
- prev_row_max_pages
+
229 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
231 /* Calculating the index based on the row and column. */
232 const unsigned index
= (row
* 4) + (col
- 1);
234 return (index
< bufmgr
->num_buckets
) ?
235 &bufmgr
->cache_bucket
[index
] : NULL
;
238 enum iris_memory_zone
239 iris_memzone_for_address(uint64_t address
)
241 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
242 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
243 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
244 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
245 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
247 if (address
>= IRIS_MEMZONE_OTHER_START
)
248 return IRIS_MEMZONE_OTHER
;
250 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
251 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
253 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
254 return IRIS_MEMZONE_DYNAMIC
;
256 if (address
>= IRIS_MEMZONE_SURFACE_START
)
257 return IRIS_MEMZONE_SURFACE
;
259 if (address
>= IRIS_MEMZONE_BINDER_START
)
260 return IRIS_MEMZONE_BINDER
;
262 return IRIS_MEMZONE_SHADER
;
266 * Allocate a section of virtual memory for a buffer, assigning an address.
268 * This uses either the bucket allocator for the given size, or the large
269 * object allocator (util_vma).
272 vma_alloc(struct iris_bufmgr
*bufmgr
,
273 enum iris_memory_zone memzone
,
277 /* Force alignment to be some number of pages */
278 alignment
= ALIGN(alignment
, PAGE_SIZE
);
280 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
281 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
283 /* The binder handles its own allocations. Return non-zero here. */
284 if (memzone
== IRIS_MEMZONE_BINDER
)
285 return IRIS_MEMZONE_BINDER_START
;
288 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
290 assert((addr
>> 48ull) == 0);
291 assert((addr
% alignment
) == 0);
293 return gen_canonical_address(addr
);
297 vma_free(struct iris_bufmgr
*bufmgr
,
301 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
304 /* Un-canonicalize the address. */
305 address
= gen_48b_address(address
);
310 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
312 /* The binder handles its own allocations. */
313 if (memzone
== IRIS_MEMZONE_BINDER
)
316 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
320 iris_bo_busy(struct iris_bo
*bo
)
322 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
323 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
325 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
327 bo
->idle
= !busy
.busy
;
334 iris_bo_madvise(struct iris_bo
*bo
, int state
)
336 struct drm_i915_gem_madvise madv
= {
337 .handle
= bo
->gem_handle
,
342 gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
344 return madv
.retained
;
347 static struct iris_bo
*
350 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
352 bo
->hash
= _mesa_hash_pointer(bo
);
357 static struct iris_bo
*
358 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
359 struct bo_cache_bucket
*bucket
,
361 enum iris_memory_zone memzone
,
368 struct iris_bo
*bo
= NULL
;
370 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
371 /* Try a little harder to find one that's already in the right memzone */
372 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
375 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
376 * either falling back to a non-matching memzone, or if that fails,
377 * allocating a fresh buffer.
379 if (iris_bo_busy(cur
))
382 list_del(&cur
->head
);
384 /* Tell the kernel we need this BO. If it still exists, we're done! */
385 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
390 /* This BO was purged, throw it out and keep looking. */
397 if (bo
->aux_map_address
) {
398 /* This buffer was associated with an aux-buffer range. We make sure
399 * that buffers are not reused from the cache while the buffer is (busy)
400 * being used by an executing batch. Since we are here, the buffer is no
401 * longer being used by a batch and the buffer was deleted (in order to
402 * end up in the cache). Therefore its old aux-buffer range can be
403 * removed from the aux-map.
405 if (bo
->bufmgr
->aux_map_ctx
)
406 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
408 bo
->aux_map_address
= 0;
411 /* If the cached BO isn't in the right memory zone, or the alignment
412 * isn't sufficient, free the old memory and assign it a new address.
414 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
) ||
415 bo
->gtt_offset
% alignment
!= 0) {
416 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
417 bo
->gtt_offset
= 0ull;
420 /* Zero the contents if necessary. If this fails, fall back to
421 * allocating a fresh BO, which will always be zeroed by the kernel.
423 if (flags
& BO_ALLOC_ZEROED
) {
424 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
426 memset(map
, 0, bo
->size
);
436 static struct iris_bo
*
437 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
439 struct iris_bo
*bo
= bo_calloc();
443 struct drm_i915_gem_create create
= { .size
= bo_size
};
445 /* All new BOs we get from the kernel are zeroed, so we don't need to
446 * worry about that here.
448 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
453 bo
->gem_handle
= create
.handle
;
457 bo
->tiling_mode
= I915_TILING_NONE
;
458 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
461 /* Calling set_domain() will allocate pages for the BO outside of the
462 * struct mutex lock in the kernel, which is more efficient than waiting
463 * to create them during the first execbuf that uses the BO.
465 struct drm_i915_gem_set_domain sd
= {
466 .handle
= bo
->gem_handle
,
467 .read_domains
= I915_GEM_DOMAIN_CPU
,
471 if (gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
479 static struct iris_bo
*
480 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
484 enum iris_memory_zone memzone
,
486 uint32_t tiling_mode
,
490 unsigned int page_size
= getpagesize();
491 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
493 /* Round the size up to the bucket size, or if we don't have caching
494 * at this size, a multiple of the page size.
497 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
499 mtx_lock(&bufmgr
->lock
);
501 /* Get a buffer out of the cache if available. First, we try to find
502 * one with a matching memory zone so we can avoid reallocating VMA.
504 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
, true);
506 /* If that fails, we try for any cached BO, without matching memzone. */
508 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
,
512 mtx_unlock(&bufmgr
->lock
);
515 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
520 if (bo
->gtt_offset
== 0ull) {
521 mtx_lock(&bufmgr
->lock
);
522 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, alignment
);
523 mtx_unlock(&bufmgr
->lock
);
525 if (bo
->gtt_offset
== 0ull)
529 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
533 p_atomic_set(&bo
->refcount
, 1);
534 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
535 bo
->cache_coherent
= bufmgr
->has_llc
;
537 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
539 /* By default, capture all driver-internal buffers like shader kernels,
540 * surface states, dynamic states, border colors, and so on.
542 if (memzone
< IRIS_MEMZONE_OTHER
)
543 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
545 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
546 struct drm_i915_gem_caching arg
= {
547 .handle
= bo
->gem_handle
,
550 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
551 bo
->cache_coherent
= true;
552 bo
->reusable
= false;
556 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
557 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
567 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
570 enum iris_memory_zone memzone
)
572 return bo_alloc_internal(bufmgr
, name
, size
, 1, memzone
,
573 0, I915_TILING_NONE
, 0);
577 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
578 uint64_t size
, uint32_t alignment
,
579 enum iris_memory_zone memzone
,
580 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
582 return bo_alloc_internal(bufmgr
, name
, size
, alignment
, memzone
,
583 flags
, tiling_mode
, pitch
);
587 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
588 void *ptr
, size_t size
,
589 enum iris_memory_zone memzone
)
597 struct drm_i915_gem_userptr arg
= {
598 .user_ptr
= (uintptr_t)ptr
,
601 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
603 bo
->gem_handle
= arg
.handle
;
605 /* Check the buffer for validity before we try and use it in a batch */
606 struct drm_i915_gem_set_domain sd
= {
607 .handle
= bo
->gem_handle
,
608 .read_domains
= I915_GEM_DOMAIN_CPU
,
610 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
618 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
620 mtx_lock(&bufmgr
->lock
);
621 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
622 mtx_unlock(&bufmgr
->lock
);
624 if (bo
->gtt_offset
== 0ull)
627 p_atomic_set(&bo
->refcount
, 1);
629 bo
->cache_coherent
= true;
636 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &bo
->gem_handle
);
643 * Returns a iris_bo wrapping the given buffer object handle.
645 * This can be used when one application needs to pass a buffer object
649 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
650 const char *name
, unsigned int handle
)
654 /* At the moment most applications only have a few named bo.
655 * For instance, in a DRI client only the render buffers passed
656 * between X and the client are named. And since X returns the
657 * alternating names for the front/back buffer a linear search
658 * provides a sufficiently fast match.
660 mtx_lock(&bufmgr
->lock
);
661 bo
= find_and_ref_external_bo(bufmgr
->name_table
, handle
);
665 struct drm_gem_open open_arg
= { .name
= handle
};
666 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
668 DBG("Couldn't reference %s handle 0x%08x: %s\n",
669 name
, handle
, strerror(errno
));
673 /* Now see if someone has used a prime handle to get this
674 * object from the kernel before by looking through the list
675 * again for a matching gem_handle
677 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, open_arg
.handle
);
685 p_atomic_set(&bo
->refcount
, 1);
687 bo
->size
= open_arg
.size
;
689 bo
->gem_handle
= open_arg
.handle
;
691 bo
->global_name
= handle
;
692 bo
->reusable
= false;
694 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
695 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
697 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
698 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
700 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
701 ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
705 bo
->tiling_mode
= get_tiling
.tiling_mode
;
706 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
707 /* XXX stride is unknown */
708 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
711 mtx_unlock(&bufmgr
->lock
);
716 mtx_unlock(&bufmgr
->lock
);
721 bo_close(struct iris_bo
*bo
)
723 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
726 struct hash_entry
*entry
;
728 if (bo
->global_name
) {
729 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
730 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
733 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
734 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
737 /* Close this object */
738 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
739 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
741 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
742 bo
->gem_handle
, bo
->name
, strerror(errno
));
745 if (bo
->aux_map_address
&& bo
->bufmgr
->aux_map_ctx
) {
746 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
750 /* Return the VMA for reuse */
751 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
757 bo_free(struct iris_bo
*bo
)
759 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
761 if (bo
->map_cpu
&& !bo
->userptr
) {
762 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
763 os_munmap(bo
->map_cpu
, bo
->size
);
766 VG_NOACCESS(bo
->map_wc
, bo
->size
);
767 os_munmap(bo
->map_wc
, bo
->size
);
770 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
771 os_munmap(bo
->map_gtt
, bo
->size
);
777 /* Defer closing the GEM BO and returning the VMA for reuse until the
778 * BO is idle. Just move it to the dead list for now.
780 list_addtail(&bo
->head
, &bufmgr
->zombie_list
);
784 /** Frees all cached buffers significantly older than @time. */
786 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
790 if (bufmgr
->time
== time
)
793 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
794 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
796 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
797 if (time
- bo
->free_time
<= 1)
806 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
807 /* Stop once we reach a busy BO - all others past this point were
808 * freed more recently so are likely also busy.
810 if (!bo
->idle
&& iris_bo_busy(bo
))
821 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
823 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
824 struct bo_cache_bucket
*bucket
;
826 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
830 bucket
= bucket_for_size(bufmgr
, bo
->size
);
831 /* Put the buffer into our internal cache for reuse if we can. */
832 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
833 bo
->free_time
= time
;
836 list_addtail(&bo
->head
, &bucket
->head
);
843 iris_bo_unreference(struct iris_bo
*bo
)
848 assert(p_atomic_read(&bo
->refcount
) > 0);
850 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
851 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
852 struct timespec time
;
854 clock_gettime(CLOCK_MONOTONIC
, &time
);
856 mtx_lock(&bufmgr
->lock
);
858 if (p_atomic_dec_zero(&bo
->refcount
)) {
859 bo_unreference_final(bo
, time
.tv_sec
);
860 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
863 mtx_unlock(&bufmgr
->lock
);
868 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
872 bool busy
= dbg
&& !bo
->idle
;
873 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
875 iris_bo_wait_rendering(bo
);
877 if (unlikely(busy
)) {
878 elapsed
+= get_time();
879 if (elapsed
> 1e-5) /* 0.01ms */ {
880 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
881 action
, bo
->name
, elapsed
* 1000);
887 print_flags(unsigned flags
)
889 if (flags
& MAP_READ
)
891 if (flags
& MAP_WRITE
)
893 if (flags
& MAP_ASYNC
)
895 if (flags
& MAP_PERSISTENT
)
897 if (flags
& MAP_COHERENT
)
905 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
906 struct iris_bo
*bo
, unsigned flags
)
908 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
910 /* We disallow CPU maps for writing to non-coherent buffers, as the
911 * CPU map can become invalidated when a batch is flushed out, which
912 * can happen at unpredictable times. You should use WC maps instead.
914 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
917 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
919 struct drm_i915_gem_mmap mmap_arg
= {
920 .handle
= bo
->gem_handle
,
923 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
925 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
926 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
929 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
930 VG_DEFINED(map
, bo
->size
);
932 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
933 VG_NOACCESS(map
, bo
->size
);
934 os_munmap(map
, bo
->size
);
939 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
943 if (!(flags
& MAP_ASYNC
)) {
944 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
947 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
948 /* If we're reusing an existing CPU mapping, the CPU caches may
949 * contain stale data from the last time we read from that mapping.
950 * (With the BO cache, it might even be data from a previous buffer!)
951 * Even if it's a brand new mapping, the kernel may have zeroed the
952 * buffer via CPU writes.
954 * We need to invalidate those cachelines so that we see the latest
955 * contents, and so long as we only read from the CPU mmap we do not
956 * need to write those cachelines back afterwards.
958 * On LLC, the emprical evidence suggests that writes from the GPU
959 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
960 * cachelines. (Other reads, such as the display engine, bypass the
961 * LLC entirely requiring us to keep dirty pixels for the scanout
964 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
971 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
972 struct iris_bo
*bo
, unsigned flags
)
974 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
977 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
979 struct drm_i915_gem_mmap mmap_arg
= {
980 .handle
= bo
->gem_handle
,
982 .flags
= I915_MMAP_WC
,
984 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
986 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
987 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
991 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
992 VG_DEFINED(map
, bo
->size
);
994 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
995 VG_NOACCESS(map
, bo
->size
);
996 os_munmap(map
, bo
->size
);
1001 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1004 if (!(flags
& MAP_ASYNC
)) {
1005 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
1012 * Perform an uncached mapping via the GTT.
1014 * Write access through the GTT is not quite fully coherent. On low power
1015 * systems especially, like modern Atoms, we can observe reads from RAM before
1016 * the write via GTT has landed. A write memory barrier that flushes the Write
1017 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1018 * read after the write as the GTT write suffers a small delay through the GTT
1019 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1020 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1021 * flushes prior to execbuf submission. However, if we are not informing the
1022 * kernel about our GTT writes, it will not flush before earlier access, such
1023 * as when using the cmdparser. Similarly, we need to be careful if we should
1024 * ever issue a CPU read immediately following a GTT write.
1026 * Telling the kernel about write access also has one more important
1027 * side-effect. Upon receiving notification about the write, it cancels any
1028 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1029 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1030 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1031 * tracking is handled on the buffer exchange instead.
1034 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1035 struct iris_bo
*bo
, unsigned flags
)
1037 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1039 /* Get a mapping of the buffer if we haven't before. */
1040 if (bo
->map_gtt
== NULL
) {
1041 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1043 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1045 /* Get the fake offset back... */
1046 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1048 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1049 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1054 void *map
= os_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1055 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1056 if (map
== MAP_FAILED
) {
1057 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1058 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1062 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1063 * already intercept this mmap call. However, for consistency between
1064 * all the mmap paths, we mark the pointer as defined now and mark it
1065 * as inaccessible afterwards.
1067 VG_DEFINED(map
, bo
->size
);
1069 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1070 VG_NOACCESS(map
, bo
->size
);
1071 os_munmap(map
, bo
->size
);
1074 assert(bo
->map_gtt
);
1076 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1079 if (!(flags
& MAP_ASYNC
)) {
1080 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1087 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1089 if (bo
->cache_coherent
)
1092 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1093 * an LLC platform reads always are coherent (as they are performed via the
1094 * central system agent). It is just the writes that we need to take special
1095 * care to ensure that land in main memory and not stick in the CPU cache.
1097 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1100 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1101 * across batch flushes where the kernel will change cache domains of the
1102 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1104 * Similarly, ASYNC typically means that the buffer will be accessed via
1105 * both the CPU and the GPU simultaneously. Batches may be executed that
1106 * use the BO even while it is mapped. While OpenGL technically disallows
1107 * most drawing while non-persistent mappings are active, we may still use
1108 * the GPU for blits or other operations, causing batches to happen at
1109 * inconvenient times.
1111 * If RAW is set, we expect the caller to be able to handle a WC buffer
1112 * more efficiently than the involuntary clflushes.
1114 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1117 return !(flags
& MAP_WRITE
);
1121 iris_bo_map(struct pipe_debug_callback
*dbg
,
1122 struct iris_bo
*bo
, unsigned flags
)
1124 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1125 return iris_bo_map_gtt(dbg
, bo
, flags
);
1129 if (can_map_cpu(bo
, flags
))
1130 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1132 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1134 /* Allow the attempt to fail by falling back to the GTT where necessary.
1136 * Not every buffer can be mmaped directly using the CPU (or WC), for
1137 * example buffers that wrap stolen memory or are imported from other
1138 * devices. For those, we have little choice but to use a GTT mmapping.
1139 * However, if we use a slow GTT mmapping for reads where we expected fast
1140 * access, that order of magnitude difference in throughput will be clearly
1141 * expressed by angry users.
1143 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1145 if (!map
&& !(flags
& MAP_RAW
)) {
1146 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1148 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1154 /** Waits for all GPU rendering with the object to have completed. */
1156 iris_bo_wait_rendering(struct iris_bo
*bo
)
1158 /* We require a kernel recent enough for WAIT_IOCTL support.
1159 * See intel_init_bufmgr()
1161 iris_bo_wait(bo
, -1);
1165 * Waits on a BO for the given amount of time.
1167 * @bo: buffer object to wait for
1168 * @timeout_ns: amount of time to wait in nanoseconds.
1169 * If value is less than 0, an infinite wait will occur.
1171 * Returns 0 if the wait was successful ie. the last batch referencing the
1172 * object has completed within the allotted time. Otherwise some negative return
1173 * value describes the error. Of particular interest is -ETIME when the wait has
1174 * failed to yield the desired result.
1176 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1177 * the operation to give up after a certain amount of time. Another subtle
1178 * difference is the internal locking semantics are different (this variant does
1179 * not hold the lock for the duration of the wait). This makes the wait subject
1180 * to a larger userspace race window.
1182 * The implementation shall wait until the object is no longer actively
1183 * referenced within a batch buffer at the time of the call. The wait will
1184 * not guarantee that the buffer is re-issued via another thread, or an flinked
1185 * handle. Userspace must make sure this race does not occur if such precision
1188 * Note that some kernels have broken the inifite wait for negative values
1189 * promise, upgrade to latest stable kernels if this is the case.
1192 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1194 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1196 /* If we know it's idle, don't bother with the kernel round trip */
1197 if (bo
->idle
&& !bo
->external
)
1200 struct drm_i915_gem_wait wait
= {
1201 .bo_handle
= bo
->gem_handle
,
1202 .timeout_ns
= timeout_ns
,
1204 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1214 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1216 /* Free aux-map buffers */
1217 gen_aux_map_finish(bufmgr
->aux_map_ctx
);
1219 /* bufmgr will no longer try to free VMA entries in the aux-map */
1220 bufmgr
->aux_map_ctx
= NULL
;
1222 mtx_destroy(&bufmgr
->lock
);
1224 /* Free any cached buffer objects we were going to reuse */
1225 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1226 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1228 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1229 list_del(&bo
->head
);
1235 /* Close any buffer objects on the dead list. */
1236 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
1237 list_del(&bo
->head
);
1241 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1242 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1244 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1245 if (z
!= IRIS_MEMZONE_BINDER
)
1246 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1255 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1258 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1259 struct drm_i915_gem_set_tiling set_tiling
;
1262 if (bo
->global_name
== 0 &&
1263 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1266 memset(&set_tiling
, 0, sizeof(set_tiling
));
1268 /* set_tiling is slightly broken and overwrites the
1269 * input on the error path, so we have to open code
1272 set_tiling
.handle
= bo
->gem_handle
;
1273 set_tiling
.tiling_mode
= tiling_mode
;
1274 set_tiling
.stride
= stride
;
1276 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1277 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1281 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1282 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1283 bo
->stride
= set_tiling
.stride
;
1288 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1289 uint32_t *swizzle_mode
)
1291 *tiling_mode
= bo
->tiling_mode
;
1292 *swizzle_mode
= bo
->swizzle_mode
;
1297 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
,
1298 uint32_t tiling
, uint32_t stride
)
1303 mtx_lock(&bufmgr
->lock
);
1304 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1306 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1308 mtx_unlock(&bufmgr
->lock
);
1313 * See if the kernel has already returned this buffer to us. Just as
1314 * for named buffers, we must not create two bo's pointing at the same
1317 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, handle
);
1325 p_atomic_set(&bo
->refcount
, 1);
1327 /* Determine size of bo. The fd-to-handle ioctl really should
1328 * return the size, but it doesn't. If we have kernel 3.12 or
1329 * later, we can lseek on the prime fd to get the size. Older
1330 * kernels will just fail, in which case we fall back to the
1331 * provided (estimated or guess size). */
1332 ret
= lseek(prime_fd
, 0, SEEK_END
);
1336 bo
->bufmgr
= bufmgr
;
1338 bo
->reusable
= false;
1339 bo
->external
= true;
1340 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1341 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1342 bo
->gem_handle
= handle
;
1343 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1345 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1346 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1349 if (get_tiling
.tiling_mode
== tiling
|| tiling
> I915_TILING_LAST
) {
1350 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1351 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1352 /* XXX stride is unknown */
1354 if (bo_set_tiling_internal(bo
, tiling
, stride
)) {
1360 mtx_unlock(&bufmgr
->lock
);
1365 mtx_unlock(&bufmgr
->lock
);
1370 iris_bo_make_external_locked(struct iris_bo
*bo
)
1372 if (!bo
->external
) {
1373 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1374 /* If a BO is going to be used externally, it could be sent to the
1375 * display HW. So make sure our CPU mappings don't assume cache
1376 * coherency since display is outside that cache.
1378 bo
->cache_coherent
= false;
1379 bo
->external
= true;
1380 bo
->reusable
= false;
1385 iris_bo_make_external(struct iris_bo
*bo
)
1387 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1390 assert(!bo
->reusable
);
1394 mtx_lock(&bufmgr
->lock
);
1395 iris_bo_make_external_locked(bo
);
1396 mtx_unlock(&bufmgr
->lock
);
1400 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1402 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1404 iris_bo_make_external(bo
);
1406 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1407 DRM_CLOEXEC
, prime_fd
) != 0)
1414 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1416 iris_bo_make_external(bo
);
1418 return bo
->gem_handle
;
1422 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1424 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1426 if (!bo
->global_name
) {
1427 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1429 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1432 mtx_lock(&bufmgr
->lock
);
1433 if (!bo
->global_name
) {
1434 iris_bo_make_external_locked(bo
);
1435 bo
->global_name
= flink
.name
;
1436 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1438 mtx_unlock(&bufmgr
->lock
);
1441 *name
= bo
->global_name
;
1446 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1448 unsigned int i
= bufmgr
->num_buckets
;
1450 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1452 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1453 bufmgr
->cache_bucket
[i
].size
= size
;
1454 bufmgr
->num_buckets
++;
1456 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1457 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1458 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1462 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1464 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1466 /* OK, so power of two buckets was too wasteful of memory.
1467 * Give 3 other sizes between each power of two, to hopefully
1468 * cover things accurately enough. (The alternative is
1469 * probably to just go for exact matching of sizes, and assume
1470 * that for things like composited window resize the tiled
1471 * width/height alignment and rounding of sizes to pages will
1472 * get us useful cache hit rates anyway)
1474 add_bucket(bufmgr
, PAGE_SIZE
);
1475 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1476 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1478 /* Initialize the linked lists for BO reuse cache. */
1479 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1480 add_bucket(bufmgr
, size
);
1482 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1483 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1484 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1489 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1491 struct drm_i915_gem_context_create create
= { };
1492 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1494 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1498 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1499 * back to the default logical HW state and attempt to continue on to
1500 * our next submitted batchbuffer. However, our render batches assume
1501 * the previous GPU state is preserved, and only emit commands needed
1502 * to incrementally change that state. In particular, we inherit the
1503 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1504 * With default base addresses, our next batches will almost certainly
1505 * cause more GPU hangs, leading to repeated hangs until we're banned
1506 * or the machine is dead.
1508 * Here we tell the kernel not to attempt to recover our context but
1509 * immediately (on the next batchbuffer submission) report that the
1510 * context is lost, and we will do the recovery ourselves. Ideally,
1511 * we'll have two lost batches instead of a continual stream of hangs.
1513 struct drm_i915_gem_context_param p
= {
1514 .ctx_id
= create
.ctx_id
,
1515 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1518 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1520 return create
.ctx_id
;
1524 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1526 struct drm_i915_gem_context_param p
= {
1528 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1530 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1531 return p
.value
; /* on error, return 0 i.e. default priority */
1535 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1539 struct drm_i915_gem_context_param p
= {
1541 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1547 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1554 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1556 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1559 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1560 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1567 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1569 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1572 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1573 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1579 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1581 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1582 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1584 *result
= reg_read
.val
;
1589 iris_gtt_size(int fd
)
1591 /* We use the default (already allocated) context to determine
1592 * the default configuration of the virtual address space.
1594 struct drm_i915_gem_context_param p
= {
1595 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1597 if (!gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1603 static struct gen_buffer
*
1604 gen_aux_map_buffer_alloc(void *driver_ctx
, uint32_t size
)
1606 struct gen_buffer
*buf
= malloc(sizeof(struct gen_buffer
));
1610 struct iris_bufmgr
*bufmgr
= (struct iris_bufmgr
*)driver_ctx
;
1612 struct iris_bo
*bo
=
1613 iris_bo_alloc_tiled(bufmgr
, "aux-map", size
, 64 * 1024,
1614 IRIS_MEMZONE_OTHER
, I915_TILING_NONE
, 0, 0);
1616 buf
->driver_bo
= bo
;
1617 buf
->gpu
= bo
->gtt_offset
;
1618 buf
->gpu_end
= buf
->gpu
+ bo
->size
;
1619 buf
->map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
1624 gen_aux_map_buffer_free(void *driver_ctx
, struct gen_buffer
*buffer
)
1626 iris_bo_unreference((struct iris_bo
*)buffer
->driver_bo
);
1630 static struct gen_mapped_pinned_buffer_alloc aux_map_allocator
= {
1631 .alloc
= gen_aux_map_buffer_alloc
,
1632 .free
= gen_aux_map_buffer_free
,
1636 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1637 * and manage map buffer objections.
1639 * \param fd File descriptor of the opened DRM device.
1641 static struct iris_bufmgr
*
1642 iris_bufmgr_create(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1644 uint64_t gtt_size
= iris_gtt_size(fd
);
1645 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1648 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1652 /* Handles to buffer objects belong to the device fd and are not
1653 * reference counted by the kernel. If the same fd is used by
1654 * multiple parties (threads sharing the same screen bufmgr, or
1655 * even worse the same device fd passed to multiple libraries)
1656 * ownership of those handles is shared by those independent parties.
1658 * Don't do this! Ensure that each library/bufmgr has its own device
1659 * fd so that its namespace does not clash with another.
1661 bufmgr
->fd
= dup(fd
);
1663 p_atomic_set(&bufmgr
->refcount
, 1);
1665 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1671 list_inithead(&bufmgr
->zombie_list
);
1673 bufmgr
->has_llc
= devinfo
->has_llc
;
1674 bufmgr
->bo_reuse
= bo_reuse
;
1676 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1677 const uint64_t _4GB
= 1ull << 32;
1678 const uint64_t _2GB
= 1ul << 31;
1680 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1681 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1683 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1684 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1685 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1686 IRIS_MEMZONE_SURFACE_START
,
1687 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1688 /* TODO: Why does limiting to 2GB help some state items on gen12?
1689 * - CC Viewport Pointer
1690 * - Blend State Pointer
1691 * - Color Calc State Pointer
1693 const uint64_t dynamic_pool_size
=
1694 (devinfo
->gen
>= 12 ? _2GB
: _4GB_minus_1
) - IRIS_BORDER_COLOR_POOL_SIZE
;
1695 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1696 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1699 /* Leave the last 4GB out of the high vma range, so that no state
1700 * base address + size can overflow 48 bits.
1702 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1703 IRIS_MEMZONE_OTHER_START
,
1704 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1706 init_cache_buckets(bufmgr
);
1708 bufmgr
->name_table
=
1709 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1710 bufmgr
->handle_table
=
1711 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1713 if (devinfo
->gen
>= 12) {
1714 bufmgr
->aux_map_ctx
= gen_aux_map_init(bufmgr
, &aux_map_allocator
,
1716 assert(bufmgr
->aux_map_ctx
);
1722 static struct iris_bufmgr
*
1723 iris_bufmgr_ref(struct iris_bufmgr
*bufmgr
)
1725 p_atomic_inc(&bufmgr
->refcount
);
1730 iris_bufmgr_unref(struct iris_bufmgr
*bufmgr
)
1732 mtx_lock(&global_bufmgr_list_mutex
);
1733 if (p_atomic_dec_zero(&bufmgr
->refcount
)) {
1734 list_del(&bufmgr
->link
);
1735 iris_bufmgr_destroy(bufmgr
);
1737 mtx_unlock(&global_bufmgr_list_mutex
);
1741 * Gets an already existing GEM buffer manager or create a new one.
1743 * \param fd File descriptor of the opened DRM device.
1745 struct iris_bufmgr
*
1746 iris_bufmgr_get_for_fd(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1753 struct iris_bufmgr
*bufmgr
= NULL
;
1755 mtx_lock(&global_bufmgr_list_mutex
);
1756 list_for_each_entry(struct iris_bufmgr
, iter_bufmgr
, &global_bufmgr_list
, link
) {
1757 struct stat iter_st
;
1758 if (fstat(iter_bufmgr
->fd
, &iter_st
))
1761 if (st
.st_rdev
== iter_st
.st_rdev
) {
1762 assert(iter_bufmgr
->bo_reuse
== bo_reuse
);
1763 bufmgr
= iris_bufmgr_ref(iter_bufmgr
);
1768 bufmgr
= iris_bufmgr_create(devinfo
, fd
, bo_reuse
);
1769 list_addtail(&bufmgr
->link
, &global_bufmgr_list
);
1772 mtx_unlock(&global_bufmgr_list_mutex
);
1778 iris_bufmgr_get_fd(struct iris_bufmgr
*bufmgr
)
1784 iris_bufmgr_get_aux_map_context(struct iris_bufmgr
*bufmgr
)
1786 return bufmgr
->aux_map_ctx
;