2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
49 #include <sys/types.h>
54 #include "common/gen_aux_map.h"
55 #include "common/gen_clflush.h"
56 #include "dev/gen_debug.h"
57 #include "common/gen_gem.h"
58 #include "dev/gen_device_info.h"
59 #include "main/macros.h"
60 #include "util/debug.h"
61 #include "util/macros.h"
62 #include "util/hash_table.h"
63 #include "util/list.h"
64 #include "util/u_dynarray.h"
66 #include "iris_bufmgr.h"
67 #include "iris_context.h"
70 #include "drm-uapi/i915_drm.h"
80 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
81 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
82 * leaked. All because it does not call VG(cli_free) from its
83 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
84 * and allocation, we mark it available for use upon mmapping and remove
87 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
88 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
90 #define PAGE_SIZE 4096
92 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
95 atomic_add_unless(int *v
, int add
, int unless
)
99 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
105 memzone_name(enum iris_memory_zone memzone
)
107 const char *names
[] = {
108 [IRIS_MEMZONE_SHADER
] = "shader",
109 [IRIS_MEMZONE_BINDER
] = "binder",
110 [IRIS_MEMZONE_SURFACE
] = "surface",
111 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
112 [IRIS_MEMZONE_OTHER
] = "other",
113 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
115 assert(memzone
< ARRAY_SIZE(names
));
116 return names
[memzone
];
119 struct bo_cache_bucket
{
120 /** List of cached BOs. */
121 struct list_head head
;
123 /** Size of this bucket, in bytes. */
132 /** Array of lists of cached gem objects of power-of-two sizes */
133 struct bo_cache_bucket cache_bucket
[14 * 4];
137 struct hash_table
*name_table
;
138 struct hash_table
*handle_table
;
141 * List of BOs which we've effectively freed, but are hanging on to
142 * until they're idle before closing and returning the VMA.
144 struct list_head zombie_list
;
146 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
151 struct gen_aux_map_context
*aux_map_ctx
;
154 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
157 static void bo_free(struct iris_bo
*bo
);
159 static uint64_t vma_alloc(struct iris_bufmgr
*bufmgr
,
160 enum iris_memory_zone memzone
,
161 uint64_t size
, uint64_t alignment
);
163 static struct iris_bo
*
164 find_and_ref_external_bo(struct hash_table
*ht
, unsigned int key
)
166 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
167 struct iris_bo
*bo
= entry
? entry
->data
: NULL
;
170 assert(bo
->external
);
171 assert(!bo
->reusable
);
173 /* Being non-reusable, the BO cannot be in the cache lists, but it
174 * may be in the zombie list if it had reached zero references, but
175 * we hadn't yet closed it...and then reimported the same BO. If it
176 * is, then remove it since it's now been resurrected.
178 if (bo
->head
.prev
|| bo
->head
.next
)
181 iris_bo_reference(bo
);
188 * This function finds the correct bucket fit for the input size.
189 * The function works with O(1) complexity when the requested size
190 * was queried instead of iterating the size through all the buckets.
192 static struct bo_cache_bucket
*
193 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
195 /* Calculating the pages and rounding up to the page size. */
196 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
198 /* Row Bucket sizes clz((x-1) | 3) Row Column
199 * in pages stride size
200 * 0: 1 2 3 4 -> 30 30 30 30 4 1
201 * 1: 5 6 7 8 -> 29 29 29 29 4 1
202 * 2: 10 12 14 16 -> 28 28 28 28 8 2
203 * 3: 20 24 28 32 -> 27 27 27 27 16 4
205 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
206 const unsigned row_max_pages
= 4 << row
;
208 /* The '& ~2' is the special case for row 1. In row 1, max pages /
209 * 2 is 2, but the previous row maximum is zero (because there is
210 * no previous row). All row maximum sizes are power of 2, so that
211 * is the only case where that bit will be set.
213 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
214 int col_size_log2
= row
- 1;
215 col_size_log2
+= (col_size_log2
< 0);
217 const unsigned col
= (pages
- prev_row_max_pages
+
218 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
220 /* Calculating the index based on the row and column. */
221 const unsigned index
= (row
* 4) + (col
- 1);
223 return (index
< bufmgr
->num_buckets
) ?
224 &bufmgr
->cache_bucket
[index
] : NULL
;
227 enum iris_memory_zone
228 iris_memzone_for_address(uint64_t address
)
230 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
231 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
232 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
233 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
234 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
236 if (address
>= IRIS_MEMZONE_OTHER_START
)
237 return IRIS_MEMZONE_OTHER
;
239 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
240 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
242 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
243 return IRIS_MEMZONE_DYNAMIC
;
245 if (address
>= IRIS_MEMZONE_SURFACE_START
)
246 return IRIS_MEMZONE_SURFACE
;
248 if (address
>= IRIS_MEMZONE_BINDER_START
)
249 return IRIS_MEMZONE_BINDER
;
251 return IRIS_MEMZONE_SHADER
;
255 * Allocate a section of virtual memory for a buffer, assigning an address.
257 * This uses either the bucket allocator for the given size, or the large
258 * object allocator (util_vma).
261 vma_alloc(struct iris_bufmgr
*bufmgr
,
262 enum iris_memory_zone memzone
,
266 /* Force alignment to be some number of pages */
267 alignment
= ALIGN(alignment
, PAGE_SIZE
);
269 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
270 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
272 /* The binder handles its own allocations. Return non-zero here. */
273 if (memzone
== IRIS_MEMZONE_BINDER
)
274 return IRIS_MEMZONE_BINDER_START
;
277 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
279 assert((addr
>> 48ull) == 0);
280 assert((addr
% alignment
) == 0);
282 return gen_canonical_address(addr
);
286 vma_free(struct iris_bufmgr
*bufmgr
,
290 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
293 /* Un-canonicalize the address. */
294 address
= gen_48b_address(address
);
299 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
301 /* The binder handles its own allocations. */
302 if (memzone
== IRIS_MEMZONE_BINDER
)
305 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
309 iris_bo_busy(struct iris_bo
*bo
)
311 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
312 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
314 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
316 bo
->idle
= !busy
.busy
;
323 iris_bo_madvise(struct iris_bo
*bo
, int state
)
325 struct drm_i915_gem_madvise madv
= {
326 .handle
= bo
->gem_handle
,
331 gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
333 return madv
.retained
;
336 static struct iris_bo
*
339 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
341 bo
->hash
= _mesa_hash_pointer(bo
);
346 static struct iris_bo
*
347 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
348 struct bo_cache_bucket
*bucket
,
350 enum iris_memory_zone memzone
,
357 struct iris_bo
*bo
= NULL
;
359 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
360 /* Try a little harder to find one that's already in the right memzone */
361 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
364 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
365 * either falling back to a non-matching memzone, or if that fails,
366 * allocating a fresh buffer.
368 if (iris_bo_busy(cur
))
371 list_del(&cur
->head
);
373 /* Tell the kernel we need this BO. If it still exists, we're done! */
374 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
379 /* This BO was purged, throw it out and keep looking. */
386 if (bo
->aux_map_address
) {
387 /* This buffer was associated with an aux-buffer range. We make sure
388 * that buffers are not reused from the cache while the buffer is (busy)
389 * being used by an executing batch. Since we are here, the buffer is no
390 * longer being used by a batch and the buffer was deleted (in order to
391 * end up in the cache). Therefore its old aux-buffer range can be
392 * removed from the aux-map.
394 if (bo
->bufmgr
->aux_map_ctx
)
395 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
397 bo
->aux_map_address
= 0;
400 /* If the cached BO isn't in the right memory zone, or the alignment
401 * isn't sufficient, free the old memory and assign it a new address.
403 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
) ||
404 bo
->gtt_offset
% alignment
!= 0) {
405 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
406 bo
->gtt_offset
= 0ull;
409 /* Zero the contents if necessary. If this fails, fall back to
410 * allocating a fresh BO, which will always be zeroed by the kernel.
412 if (flags
& BO_ALLOC_ZEROED
) {
413 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
415 memset(map
, 0, bo
->size
);
425 static struct iris_bo
*
426 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
428 struct iris_bo
*bo
= bo_calloc();
432 struct drm_i915_gem_create create
= { .size
= bo_size
};
434 /* All new BOs we get from the kernel are zeroed, so we don't need to
435 * worry about that here.
437 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
442 bo
->gem_handle
= create
.handle
;
446 bo
->tiling_mode
= I915_TILING_NONE
;
447 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
450 /* Calling set_domain() will allocate pages for the BO outside of the
451 * struct mutex lock in the kernel, which is more efficient than waiting
452 * to create them during the first execbuf that uses the BO.
454 struct drm_i915_gem_set_domain sd
= {
455 .handle
= bo
->gem_handle
,
456 .read_domains
= I915_GEM_DOMAIN_CPU
,
460 if (gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
468 static struct iris_bo
*
469 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
473 enum iris_memory_zone memzone
,
475 uint32_t tiling_mode
,
479 unsigned int page_size
= getpagesize();
480 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
482 /* Round the size up to the bucket size, or if we don't have caching
483 * at this size, a multiple of the page size.
486 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
488 mtx_lock(&bufmgr
->lock
);
490 /* Get a buffer out of the cache if available. First, we try to find
491 * one with a matching memory zone so we can avoid reallocating VMA.
493 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
, true);
495 /* If that fails, we try for any cached BO, without matching memzone. */
497 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
,
501 mtx_unlock(&bufmgr
->lock
);
504 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
509 if (bo
->gtt_offset
== 0ull) {
510 mtx_lock(&bufmgr
->lock
);
511 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, alignment
);
512 mtx_unlock(&bufmgr
->lock
);
514 if (bo
->gtt_offset
== 0ull)
518 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
522 p_atomic_set(&bo
->refcount
, 1);
523 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
524 bo
->cache_coherent
= bufmgr
->has_llc
;
526 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
528 /* By default, capture all driver-internal buffers like shader kernels,
529 * surface states, dynamic states, border colors, and so on.
531 if (memzone
< IRIS_MEMZONE_OTHER
)
532 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
534 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
535 struct drm_i915_gem_caching arg
= {
536 .handle
= bo
->gem_handle
,
539 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
540 bo
->cache_coherent
= true;
541 bo
->reusable
= false;
545 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
546 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
556 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
559 enum iris_memory_zone memzone
)
561 return bo_alloc_internal(bufmgr
, name
, size
, 1, memzone
,
562 0, I915_TILING_NONE
, 0);
566 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
567 uint64_t size
, uint32_t alignment
,
568 enum iris_memory_zone memzone
,
569 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
571 return bo_alloc_internal(bufmgr
, name
, size
, alignment
, memzone
,
572 flags
, tiling_mode
, pitch
);
576 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
577 void *ptr
, size_t size
,
578 enum iris_memory_zone memzone
)
586 struct drm_i915_gem_userptr arg
= {
587 .user_ptr
= (uintptr_t)ptr
,
590 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
592 bo
->gem_handle
= arg
.handle
;
594 /* Check the buffer for validity before we try and use it in a batch */
595 struct drm_i915_gem_set_domain sd
= {
596 .handle
= bo
->gem_handle
,
597 .read_domains
= I915_GEM_DOMAIN_CPU
,
599 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
607 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
609 mtx_lock(&bufmgr
->lock
);
610 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
611 mtx_unlock(&bufmgr
->lock
);
613 if (bo
->gtt_offset
== 0ull)
616 p_atomic_set(&bo
->refcount
, 1);
618 bo
->cache_coherent
= true;
625 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &bo
->gem_handle
);
632 * Returns a iris_bo wrapping the given buffer object handle.
634 * This can be used when one application needs to pass a buffer object
638 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
639 const char *name
, unsigned int handle
)
643 /* At the moment most applications only have a few named bo.
644 * For instance, in a DRI client only the render buffers passed
645 * between X and the client are named. And since X returns the
646 * alternating names for the front/back buffer a linear search
647 * provides a sufficiently fast match.
649 mtx_lock(&bufmgr
->lock
);
650 bo
= find_and_ref_external_bo(bufmgr
->name_table
, handle
);
654 struct drm_gem_open open_arg
= { .name
= handle
};
655 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
657 DBG("Couldn't reference %s handle 0x%08x: %s\n",
658 name
, handle
, strerror(errno
));
662 /* Now see if someone has used a prime handle to get this
663 * object from the kernel before by looking through the list
664 * again for a matching gem_handle
666 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, open_arg
.handle
);
674 p_atomic_set(&bo
->refcount
, 1);
676 bo
->size
= open_arg
.size
;
679 bo
->gem_handle
= open_arg
.handle
;
681 bo
->global_name
= handle
;
682 bo
->reusable
= false;
684 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
685 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
687 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
688 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
690 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
691 ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
695 bo
->tiling_mode
= get_tiling
.tiling_mode
;
696 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
697 /* XXX stride is unknown */
698 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
701 mtx_unlock(&bufmgr
->lock
);
706 mtx_unlock(&bufmgr
->lock
);
711 bo_close(struct iris_bo
*bo
)
713 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
716 struct hash_entry
*entry
;
718 if (bo
->global_name
) {
719 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
720 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
723 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
724 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
727 /* Close this object */
728 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
729 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
731 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
732 bo
->gem_handle
, bo
->name
, strerror(errno
));
735 if (bo
->aux_map_address
&& bo
->bufmgr
->aux_map_ctx
) {
736 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
740 /* Return the VMA for reuse */
741 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
747 bo_free(struct iris_bo
*bo
)
749 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
751 if (bo
->map_cpu
&& !bo
->userptr
) {
752 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
753 munmap(bo
->map_cpu
, bo
->size
);
756 VG_NOACCESS(bo
->map_wc
, bo
->size
);
757 munmap(bo
->map_wc
, bo
->size
);
760 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
761 munmap(bo
->map_gtt
, bo
->size
);
767 /* Defer closing the GEM BO and returning the VMA for reuse until the
768 * BO is idle. Just move it to the dead list for now.
770 list_addtail(&bo
->head
, &bufmgr
->zombie_list
);
774 /** Frees all cached buffers significantly older than @time. */
776 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
780 if (bufmgr
->time
== time
)
783 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
784 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
786 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
787 if (time
- bo
->free_time
<= 1)
796 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
797 /* Stop once we reach a busy BO - all others past this point were
798 * freed more recently so are likely also busy.
800 if (!bo
->idle
&& iris_bo_busy(bo
))
811 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
813 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
814 struct bo_cache_bucket
*bucket
;
816 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
820 bucket
= bucket_for_size(bufmgr
, bo
->size
);
821 /* Put the buffer into our internal cache for reuse if we can. */
822 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
823 bo
->free_time
= time
;
826 list_addtail(&bo
->head
, &bucket
->head
);
833 iris_bo_unreference(struct iris_bo
*bo
)
838 assert(p_atomic_read(&bo
->refcount
) > 0);
840 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
841 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
842 struct timespec time
;
844 clock_gettime(CLOCK_MONOTONIC
, &time
);
846 mtx_lock(&bufmgr
->lock
);
848 if (p_atomic_dec_zero(&bo
->refcount
)) {
849 bo_unreference_final(bo
, time
.tv_sec
);
850 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
853 mtx_unlock(&bufmgr
->lock
);
858 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
862 bool busy
= dbg
&& !bo
->idle
;
863 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
865 iris_bo_wait_rendering(bo
);
867 if (unlikely(busy
)) {
868 elapsed
+= get_time();
869 if (elapsed
> 1e-5) /* 0.01ms */ {
870 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
871 action
, bo
->name
, elapsed
* 1000);
877 print_flags(unsigned flags
)
879 if (flags
& MAP_READ
)
881 if (flags
& MAP_WRITE
)
883 if (flags
& MAP_ASYNC
)
885 if (flags
& MAP_PERSISTENT
)
887 if (flags
& MAP_COHERENT
)
895 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
896 struct iris_bo
*bo
, unsigned flags
)
898 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
900 /* We disallow CPU maps for writing to non-coherent buffers, as the
901 * CPU map can become invalidated when a batch is flushed out, which
902 * can happen at unpredictable times. You should use WC maps instead.
904 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
907 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
909 struct drm_i915_gem_mmap mmap_arg
= {
910 .handle
= bo
->gem_handle
,
913 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
915 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
916 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
919 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
920 VG_DEFINED(map
, bo
->size
);
922 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
923 VG_NOACCESS(map
, bo
->size
);
924 munmap(map
, bo
->size
);
929 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
933 if (!(flags
& MAP_ASYNC
)) {
934 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
937 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
938 /* If we're reusing an existing CPU mapping, the CPU caches may
939 * contain stale data from the last time we read from that mapping.
940 * (With the BO cache, it might even be data from a previous buffer!)
941 * Even if it's a brand new mapping, the kernel may have zeroed the
942 * buffer via CPU writes.
944 * We need to invalidate those cachelines so that we see the latest
945 * contents, and so long as we only read from the CPU mmap we do not
946 * need to write those cachelines back afterwards.
948 * On LLC, the emprical evidence suggests that writes from the GPU
949 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
950 * cachelines. (Other reads, such as the display engine, bypass the
951 * LLC entirely requiring us to keep dirty pixels for the scanout
954 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
961 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
962 struct iris_bo
*bo
, unsigned flags
)
964 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
967 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
969 struct drm_i915_gem_mmap mmap_arg
= {
970 .handle
= bo
->gem_handle
,
972 .flags
= I915_MMAP_WC
,
974 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
976 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
977 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
981 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
982 VG_DEFINED(map
, bo
->size
);
984 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
985 VG_NOACCESS(map
, bo
->size
);
986 munmap(map
, bo
->size
);
991 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
994 if (!(flags
& MAP_ASYNC
)) {
995 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
1002 * Perform an uncached mapping via the GTT.
1004 * Write access through the GTT is not quite fully coherent. On low power
1005 * systems especially, like modern Atoms, we can observe reads from RAM before
1006 * the write via GTT has landed. A write memory barrier that flushes the Write
1007 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1008 * read after the write as the GTT write suffers a small delay through the GTT
1009 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1010 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1011 * flushes prior to execbuf submission. However, if we are not informing the
1012 * kernel about our GTT writes, it will not flush before earlier access, such
1013 * as when using the cmdparser. Similarly, we need to be careful if we should
1014 * ever issue a CPU read immediately following a GTT write.
1016 * Telling the kernel about write access also has one more important
1017 * side-effect. Upon receiving notification about the write, it cancels any
1018 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1019 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1020 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1021 * tracking is handled on the buffer exchange instead.
1024 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1025 struct iris_bo
*bo
, unsigned flags
)
1027 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1029 /* Get a mapping of the buffer if we haven't before. */
1030 if (bo
->map_gtt
== NULL
) {
1031 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1033 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1035 /* Get the fake offset back... */
1036 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1038 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1039 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1044 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1045 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1046 if (map
== MAP_FAILED
) {
1047 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1048 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1052 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1053 * already intercept this mmap call. However, for consistency between
1054 * all the mmap paths, we mark the pointer as defined now and mark it
1055 * as inaccessible afterwards.
1057 VG_DEFINED(map
, bo
->size
);
1059 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1060 VG_NOACCESS(map
, bo
->size
);
1061 munmap(map
, bo
->size
);
1064 assert(bo
->map_gtt
);
1066 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1069 if (!(flags
& MAP_ASYNC
)) {
1070 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1077 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1079 if (bo
->cache_coherent
)
1082 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1083 * an LLC platform reads always are coherent (as they are performed via the
1084 * central system agent). It is just the writes that we need to take special
1085 * care to ensure that land in main memory and not stick in the CPU cache.
1087 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1090 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1091 * across batch flushes where the kernel will change cache domains of the
1092 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1094 * Similarly, ASYNC typically means that the buffer will be accessed via
1095 * both the CPU and the GPU simultaneously. Batches may be executed that
1096 * use the BO even while it is mapped. While OpenGL technically disallows
1097 * most drawing while non-persistent mappings are active, we may still use
1098 * the GPU for blits or other operations, causing batches to happen at
1099 * inconvenient times.
1101 * If RAW is set, we expect the caller to be able to handle a WC buffer
1102 * more efficiently than the involuntary clflushes.
1104 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1107 return !(flags
& MAP_WRITE
);
1111 iris_bo_map(struct pipe_debug_callback
*dbg
,
1112 struct iris_bo
*bo
, unsigned flags
)
1114 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1115 return iris_bo_map_gtt(dbg
, bo
, flags
);
1119 if (can_map_cpu(bo
, flags
))
1120 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1122 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1124 /* Allow the attempt to fail by falling back to the GTT where necessary.
1126 * Not every buffer can be mmaped directly using the CPU (or WC), for
1127 * example buffers that wrap stolen memory or are imported from other
1128 * devices. For those, we have little choice but to use a GTT mmapping.
1129 * However, if we use a slow GTT mmapping for reads where we expected fast
1130 * access, that order of magnitude difference in throughput will be clearly
1131 * expressed by angry users.
1133 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1135 if (!map
&& !(flags
& MAP_RAW
)) {
1136 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1138 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1144 /** Waits for all GPU rendering with the object to have completed. */
1146 iris_bo_wait_rendering(struct iris_bo
*bo
)
1148 /* We require a kernel recent enough for WAIT_IOCTL support.
1149 * See intel_init_bufmgr()
1151 iris_bo_wait(bo
, -1);
1155 * Waits on a BO for the given amount of time.
1157 * @bo: buffer object to wait for
1158 * @timeout_ns: amount of time to wait in nanoseconds.
1159 * If value is less than 0, an infinite wait will occur.
1161 * Returns 0 if the wait was successful ie. the last batch referencing the
1162 * object has completed within the allotted time. Otherwise some negative return
1163 * value describes the error. Of particular interest is -ETIME when the wait has
1164 * failed to yield the desired result.
1166 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1167 * the operation to give up after a certain amount of time. Another subtle
1168 * difference is the internal locking semantics are different (this variant does
1169 * not hold the lock for the duration of the wait). This makes the wait subject
1170 * to a larger userspace race window.
1172 * The implementation shall wait until the object is no longer actively
1173 * referenced within a batch buffer at the time of the call. The wait will
1174 * not guarantee that the buffer is re-issued via another thread, or an flinked
1175 * handle. Userspace must make sure this race does not occur if such precision
1178 * Note that some kernels have broken the inifite wait for negative values
1179 * promise, upgrade to latest stable kernels if this is the case.
1182 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1184 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1186 /* If we know it's idle, don't bother with the kernel round trip */
1187 if (bo
->idle
&& !bo
->external
)
1190 struct drm_i915_gem_wait wait
= {
1191 .bo_handle
= bo
->gem_handle
,
1192 .timeout_ns
= timeout_ns
,
1194 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1204 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1206 /* Free aux-map buffers */
1207 gen_aux_map_finish(bufmgr
->aux_map_ctx
);
1209 /* bufmgr will no longer try to free VMA entries in the aux-map */
1210 bufmgr
->aux_map_ctx
= NULL
;
1212 mtx_destroy(&bufmgr
->lock
);
1214 /* Free any cached buffer objects we were going to reuse */
1215 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1216 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1218 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1219 list_del(&bo
->head
);
1225 /* Close any buffer objects on the dead list. */
1226 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
1227 list_del(&bo
->head
);
1231 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1232 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1234 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1235 if (z
!= IRIS_MEMZONE_BINDER
)
1236 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1243 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1246 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1247 struct drm_i915_gem_set_tiling set_tiling
;
1250 if (bo
->global_name
== 0 &&
1251 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1254 memset(&set_tiling
, 0, sizeof(set_tiling
));
1256 /* set_tiling is slightly broken and overwrites the
1257 * input on the error path, so we have to open code
1260 set_tiling
.handle
= bo
->gem_handle
;
1261 set_tiling
.tiling_mode
= tiling_mode
;
1262 set_tiling
.stride
= stride
;
1264 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1265 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1269 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1270 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1271 bo
->stride
= set_tiling
.stride
;
1276 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1277 uint32_t *swizzle_mode
)
1279 *tiling_mode
= bo
->tiling_mode
;
1280 *swizzle_mode
= bo
->swizzle_mode
;
1285 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
,
1286 uint32_t tiling
, uint32_t stride
)
1291 mtx_lock(&bufmgr
->lock
);
1292 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1294 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1296 mtx_unlock(&bufmgr
->lock
);
1301 * See if the kernel has already returned this buffer to us. Just as
1302 * for named buffers, we must not create two bo's pointing at the same
1305 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, handle
);
1313 p_atomic_set(&bo
->refcount
, 1);
1315 /* Determine size of bo. The fd-to-handle ioctl really should
1316 * return the size, but it doesn't. If we have kernel 3.12 or
1317 * later, we can lseek on the prime fd to get the size. Older
1318 * kernels will just fail, in which case we fall back to the
1319 * provided (estimated or guess size). */
1320 ret
= lseek(prime_fd
, 0, SEEK_END
);
1324 bo
->bufmgr
= bufmgr
;
1326 bo
->reusable
= false;
1327 bo
->external
= true;
1328 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1329 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1330 bo
->gem_handle
= handle
;
1331 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1333 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1334 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1337 if (get_tiling
.tiling_mode
== tiling
|| tiling
> I915_TILING_LAST
) {
1338 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1339 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1340 /* XXX stride is unknown */
1342 if (bo_set_tiling_internal(bo
, tiling
, stride
)) {
1348 mtx_unlock(&bufmgr
->lock
);
1353 mtx_unlock(&bufmgr
->lock
);
1358 iris_bo_make_external_locked(struct iris_bo
*bo
)
1360 if (!bo
->external
) {
1361 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1362 bo
->external
= true;
1363 bo
->reusable
= false;
1368 iris_bo_make_external(struct iris_bo
*bo
)
1370 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1373 assert(!bo
->reusable
);
1377 mtx_lock(&bufmgr
->lock
);
1378 iris_bo_make_external_locked(bo
);
1379 mtx_unlock(&bufmgr
->lock
);
1383 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1385 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1387 iris_bo_make_external(bo
);
1389 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1390 DRM_CLOEXEC
, prime_fd
) != 0)
1397 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1399 iris_bo_make_external(bo
);
1401 return bo
->gem_handle
;
1405 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1407 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1409 if (!bo
->global_name
) {
1410 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1412 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1415 mtx_lock(&bufmgr
->lock
);
1416 if (!bo
->global_name
) {
1417 iris_bo_make_external_locked(bo
);
1418 bo
->global_name
= flink
.name
;
1419 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1421 mtx_unlock(&bufmgr
->lock
);
1424 *name
= bo
->global_name
;
1429 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1431 unsigned int i
= bufmgr
->num_buckets
;
1433 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1435 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1436 bufmgr
->cache_bucket
[i
].size
= size
;
1437 bufmgr
->num_buckets
++;
1439 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1440 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1441 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1445 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1447 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1449 /* OK, so power of two buckets was too wasteful of memory.
1450 * Give 3 other sizes between each power of two, to hopefully
1451 * cover things accurately enough. (The alternative is
1452 * probably to just go for exact matching of sizes, and assume
1453 * that for things like composited window resize the tiled
1454 * width/height alignment and rounding of sizes to pages will
1455 * get us useful cache hit rates anyway)
1457 add_bucket(bufmgr
, PAGE_SIZE
);
1458 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1459 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1461 /* Initialize the linked lists for BO reuse cache. */
1462 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1463 add_bucket(bufmgr
, size
);
1465 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1466 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1467 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1472 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1474 struct drm_i915_gem_context_create create
= { };
1475 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1477 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1481 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1482 * back to the default logical HW state and attempt to continue on to
1483 * our next submitted batchbuffer. However, our render batches assume
1484 * the previous GPU state is preserved, and only emit commands needed
1485 * to incrementally change that state. In particular, we inherit the
1486 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1487 * With default base addresses, our next batches will almost certainly
1488 * cause more GPU hangs, leading to repeated hangs until we're banned
1489 * or the machine is dead.
1491 * Here we tell the kernel not to attempt to recover our context but
1492 * immediately (on the next batchbuffer submission) report that the
1493 * context is lost, and we will do the recovery ourselves. Ideally,
1494 * we'll have two lost batches instead of a continual stream of hangs.
1496 struct drm_i915_gem_context_param p
= {
1497 .ctx_id
= create
.ctx_id
,
1498 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1501 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1503 return create
.ctx_id
;
1507 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1509 struct drm_i915_gem_context_param p
= {
1511 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1513 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1514 return p
.value
; /* on error, return 0 i.e. default priority */
1518 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1522 struct drm_i915_gem_context_param p
= {
1524 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1530 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1537 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1539 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1542 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1543 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1550 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1552 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1555 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1556 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1562 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1564 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1565 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1567 *result
= reg_read
.val
;
1572 iris_gtt_size(int fd
)
1574 /* We use the default (already allocated) context to determine
1575 * the default configuration of the virtual address space.
1577 struct drm_i915_gem_context_param p
= {
1578 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1580 if (!gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1586 static struct gen_buffer
*
1587 gen_aux_map_buffer_alloc(void *driver_ctx
, uint32_t size
)
1589 struct gen_buffer
*buf
= malloc(sizeof(struct gen_buffer
));
1593 struct iris_bufmgr
*bufmgr
= (struct iris_bufmgr
*)driver_ctx
;
1595 struct iris_bo
*bo
=
1596 iris_bo_alloc_tiled(bufmgr
, "aux-map", size
, 64 * 1024,
1597 IRIS_MEMZONE_OTHER
, I915_TILING_NONE
, 0, 0);
1599 buf
->driver_bo
= bo
;
1600 buf
->gpu
= bo
->gtt_offset
;
1601 buf
->gpu_end
= buf
->gpu
+ bo
->size
;
1602 buf
->map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
1607 gen_aux_map_buffer_free(void *driver_ctx
, struct gen_buffer
*buffer
)
1609 iris_bo_unreference((struct iris_bo
*)buffer
->driver_bo
);
1613 static struct gen_mapped_pinned_buffer_alloc aux_map_allocator
= {
1614 .alloc
= gen_aux_map_buffer_alloc
,
1615 .free
= gen_aux_map_buffer_free
,
1619 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1620 * and manage map buffer objections.
1622 * \param fd File descriptor of the opened DRM device.
1624 struct iris_bufmgr
*
1625 iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1627 uint64_t gtt_size
= iris_gtt_size(fd
);
1628 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1631 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1635 /* Handles to buffer objects belong to the device fd and are not
1636 * reference counted by the kernel. If the same fd is used by
1637 * multiple parties (threads sharing the same screen bufmgr, or
1638 * even worse the same device fd passed to multiple libraries)
1639 * ownership of those handles is shared by those independent parties.
1641 * Don't do this! Ensure that each library/bufmgr has its own device
1642 * fd so that its namespace does not clash with another.
1646 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1651 list_inithead(&bufmgr
->zombie_list
);
1653 bufmgr
->has_llc
= devinfo
->has_llc
;
1654 bufmgr
->bo_reuse
= bo_reuse
;
1656 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1657 const uint64_t _4GB
= 1ull << 32;
1658 const uint64_t _2GB
= 1ul << 31;
1660 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1661 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1663 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1664 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1665 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1666 IRIS_MEMZONE_SURFACE_START
,
1667 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1668 /* TODO: Why does limiting to 2GB help some state items on gen12?
1669 * - CC Viewport Pointer
1670 * - Blend State Pointer
1671 * - Color Calc State Pointer
1673 const uint64_t dynamic_pool_size
=
1674 (devinfo
->gen
>= 12 ? _2GB
: _4GB_minus_1
) - IRIS_BORDER_COLOR_POOL_SIZE
;
1675 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1676 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1679 /* Leave the last 4GB out of the high vma range, so that no state
1680 * base address + size can overflow 48 bits.
1682 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1683 IRIS_MEMZONE_OTHER_START
,
1684 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1686 init_cache_buckets(bufmgr
);
1688 bufmgr
->name_table
=
1689 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1690 bufmgr
->handle_table
=
1691 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1693 if (devinfo
->gen
>= 12) {
1694 bufmgr
->aux_map_ctx
= gen_aux_map_init(bufmgr
, &aux_map_allocator
,
1696 assert(bufmgr
->aux_map_ctx
);
1703 iris_bufmgr_get_aux_map_context(struct iris_bufmgr
*bufmgr
)
1705 return bufmgr
->aux_map_ctx
;