2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include <util/u_atomic.h>
36 #include <sys/ioctl.h>
39 #include <sys/types.h>
45 #define ETIME ETIMEDOUT
47 #include "common/gen_clflush.h"
48 #include "common/gen_debug.h"
49 #include "dev/gen_device_info.h"
50 #include "main/macros.h"
51 #include "util/macros.h"
52 #include "util/hash_table.h"
53 #include "util/list.h"
54 #include "util/u_dynarray.h"
56 #include "iris_bufmgr.h"
57 #include "iris_context.h"
60 #include "drm-uapi/i915_drm.h"
70 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
71 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
72 * leaked. All because it does not call VG(cli_free) from its
73 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
74 * and allocation, we mark it available for use upon mmapping and remove
77 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
78 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
80 #define PAGE_SIZE 4096
82 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
85 * Call ioctl, restarting if it is interupted
88 drm_ioctl(int fd
, unsigned long request
, void *arg
)
93 ret
= ioctl(fd
, request
, arg
);
94 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
99 atomic_add_unless(int *v
, int add
, int unless
)
102 c
= p_atomic_read(v
);
103 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
111 * Have a bitmap-allocator for each BO cache bucket size. Because bo_alloc
112 * rounds up allocations to the bucket size anyway, we can make 1 bit in the
113 * bitmap represent N pages of memory, where N = <bucket size / page size>.
114 * Allocations and frees always set/unset a single bit. Because ffsll only
115 * works on uint64_t, use a tree(?) of those.
117 * Nodes contain a starting address and a uint64_t bitmap. (pair-of-uint64_t)
118 * Bitmap uses 1 for a free block, 0 for in-use.
122 * Dynamic array of nodes. (pointer, two ints)
125 struct vma_bucket_node
{
126 uint64_t start_address
;
130 struct bo_cache_bucket
{
131 /** List of cached BOs. */
132 struct list_head head
;
134 /** Size of this bucket, in bytes. */
137 /** List of vma_bucket_nodes */
138 struct util_dynarray vma_list
[IRIS_MEMZONE_COUNT
];
146 /** Array of lists of cached gem objects of power-of-two sizes */
147 struct bo_cache_bucket cache_bucket
[14 * 4];
151 struct hash_table
*name_table
;
152 struct hash_table
*handle_table
;
154 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
160 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
163 static void bo_free(struct iris_bo
*bo
);
165 static uint64_t __vma_alloc(struct iris_bufmgr
*bufmgr
,
166 enum iris_memory_zone memzone
,
167 uint64_t size
, uint64_t alignment
);
170 key_hash_uint(const void *key
)
172 return _mesa_hash_data(key
, 4);
176 key_uint_equal(const void *a
, const void *b
)
178 return *((unsigned *) a
) == *((unsigned *) b
);
181 static struct iris_bo
*
182 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
184 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
185 return entry
? (struct iris_bo
*) entry
->data
: NULL
;
189 * This function finds the correct bucket fit for the input size.
190 * The function works with O(1) complexity when the requested size
191 * was queried instead of iterating the size through all the buckets.
193 static struct bo_cache_bucket
*
194 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
196 /* Calculating the pages and rounding up to the page size. */
197 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
199 /* Row Bucket sizes clz((x-1) | 3) Row Column
200 * in pages stride size
201 * 0: 1 2 3 4 -> 30 30 30 30 4 1
202 * 1: 5 6 7 8 -> 29 29 29 29 4 1
203 * 2: 10 12 14 16 -> 28 28 28 28 8 2
204 * 3: 20 24 28 32 -> 27 27 27 27 16 4
206 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
207 const unsigned row_max_pages
= 4 << row
;
209 /* The '& ~2' is the special case for row 1. In row 1, max pages /
210 * 2 is 2, but the previous row maximum is zero (because there is
211 * no previous row). All row maximum sizes are power of 2, so that
212 * is the only case where that bit will be set.
214 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
215 int col_size_log2
= row
- 1;
216 col_size_log2
+= (col_size_log2
< 0);
218 const unsigned col
= (pages
- prev_row_max_pages
+
219 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
221 /* Calculating the index based on the row and column. */
222 const unsigned index
= (row
* 4) + (col
- 1);
224 return (index
< bufmgr
->num_buckets
) ?
225 &bufmgr
->cache_bucket
[index
] : NULL
;
228 static enum iris_memory_zone
229 memzone_for_address(uint64_t address
)
231 const uint64_t _4GB
= 1ull << 32;
233 if (address
>= 3 * _4GB
)
234 return IRIS_MEMZONE_OTHER
;
236 if (address
>= 2 * _4GB
)
237 return IRIS_MEMZONE_DYNAMIC
;
239 if (address
> 1 * _4GB
)
240 return IRIS_MEMZONE_SURFACE
;
242 /* The binder isn't in any memory zone. */
243 if (address
== 1 * _4GB
)
244 return IRIS_MEMZONE_BINDER
;
246 return IRIS_MEMZONE_SHADER
;
250 bucket_vma_alloc(struct iris_bufmgr
*bufmgr
,
251 struct bo_cache_bucket
*bucket
,
252 enum iris_memory_zone memzone
)
254 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
255 struct vma_bucket_node
*node
;
257 if (vma_list
->size
== 0) {
258 /* This bucket allocator is out of space - allocate a new block of
259 * memory from a larger allocator (either another bucket or util_vma).
261 * Set the first bit used, and return the start address.
263 uint64_t node_size
= 64ull * bucket
->size
;
264 node
= util_dynarray_grow(vma_list
, sizeof(struct vma_bucket_node
));
265 node
->start_address
= __vma_alloc(bufmgr
, memzone
, node_size
, node_size
);
266 node
->bitmap
= ~1ull;
267 return node
->start_address
;
270 /* Pick any bit from any node - they're all the right size and free. */
271 node
= util_dynarray_top_ptr(vma_list
, struct vma_bucket_node
);
272 int bit
= ffsll(node
->bitmap
) - 1;
273 assert(bit
>= 0 && bit
<= 63);
275 /* Reserve the memory by clearing the bit. */
276 assert((node
->bitmap
& (1ull << bit
)) != 0ull);
277 node
->bitmap
&= ~(1ull << bit
);
279 /* If this node is now completely full, remove it from the free list. */
280 if (node
->bitmap
== 0ull) {
281 (void) util_dynarray_pop(vma_list
, struct vma_bucket_node
);
284 return node
->start_address
+ bit
* bucket
->size
;
288 bucket_vma_free(struct bo_cache_bucket
*bucket
,
292 enum iris_memory_zone memzone
= memzone_for_address(address
);
293 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
294 const uint64_t node_bytes
= 64ull * bucket
->size
;
295 struct vma_bucket_node
*node
= NULL
;
297 uint64_t start
= (address
/ node_bytes
) * node_bytes
;
298 int bit
= (address
- start
) / bucket
->size
;
300 assert(start
+ bit
* bucket
->size
== address
);
302 util_dynarray_foreach(vma_list
, struct vma_bucket_node
, cur
) {
303 if (cur
->start_address
== start
) {
310 node
= util_dynarray_grow(vma_list
, sizeof(struct vma_bucket_node
));
311 node
->start_address
= start
;
315 /* Set the bit to return the memory. */
316 assert((node
->bitmap
& (1ull << bit
)) != 0ull);
317 node
->bitmap
|= 1ull << bit
;
319 /* The block might be entirely free now, and if so, we could return it
320 * to the larger allocator. But we may as well hang on to it, in case
321 * we get more allocations at this block size.
325 static struct bo_cache_bucket
*
326 get_bucket_allocator(struct iris_bufmgr
*bufmgr
, uint64_t size
)
328 /* Skip using the bucket allocator for very large sizes, as it allocates
329 * 64 of them and this can balloon rather quickly.
331 if (size
> 1024 * PAGE_SIZE
)
334 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
336 if (bucket
&& bucket
->size
== size
)
342 /** Like vma_alloc, but returns a non-canonicalized address. */
344 __vma_alloc(struct iris_bufmgr
*bufmgr
,
345 enum iris_memory_zone memzone
,
349 if (memzone
== IRIS_MEMZONE_BINDER
)
352 struct bo_cache_bucket
*bucket
= get_bucket_allocator(bufmgr
, size
);
356 addr
= bucket_vma_alloc(bufmgr
, bucket
, memzone
);
358 addr
= util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
,
362 assert((addr
>> 48ull) == 0);
367 * Allocate a section of virtual memory for a buffer, assigning an address.
369 * This uses either the bucket allocator for the given size, or the large
370 * object allocator (util_vma).
373 vma_alloc(struct iris_bufmgr
*bufmgr
,
374 enum iris_memory_zone memzone
,
378 uint64_t addr
= __vma_alloc(bufmgr
, memzone
, size
, alignment
);
380 /* Canonicalize the address.
382 * The Broadwell PRM Vol. 2a, MI_LOAD_REGISTER_MEM::MemoryAddress says:
384 * "This field specifies the address of the memory location where the
385 * register value specified in the DWord above will read from. The
386 * address specifies the DWord location of the data. Range =
387 * GraphicsVirtualAddress[63:2] for a DWord register GraphicsAddress
388 * [63:48] are ignored by the HW and assumed to be in correct
389 * canonical form [63:48] == [47]."
391 const int shift
= 63 - 47;
392 addr
= (((int64_t) addr
) << shift
) >> shift
;
398 vma_free(struct iris_bufmgr
*bufmgr
,
402 /* Un-canonicalize the address; our allocators expect 0 in the high bits */
403 address
&= (1ull << 48) - 1;
405 struct bo_cache_bucket
*bucket
= get_bucket_allocator(bufmgr
, size
);
408 bucket_vma_free(bucket
, address
, size
);
410 enum iris_memory_zone memzone
= memzone_for_address(address
);
411 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
416 iris_bo_busy(struct iris_bo
*bo
)
418 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
419 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
421 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
423 bo
->idle
= !busy
.busy
;
430 iris_bo_madvise(struct iris_bo
*bo
, int state
)
432 struct drm_i915_gem_madvise madv
= {
433 .handle
= bo
->gem_handle
,
438 drm_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
440 return madv
.retained
;
443 /* drop the oldest entries that have been purged by the kernel */
445 iris_bo_cache_purge_bucket(struct iris_bufmgr
*bufmgr
,
446 struct bo_cache_bucket
*bucket
)
448 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
449 if (iris_bo_madvise(bo
, I915_MADV_DONTNEED
))
457 static struct iris_bo
*
458 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
461 enum iris_memory_zone memzone
,
463 uint32_t tiling_mode
,
467 unsigned int page_size
= getpagesize();
469 struct bo_cache_bucket
*bucket
;
470 bool alloc_from_cache
;
474 if (flags
& BO_ALLOC_ZEROED
)
477 /* Round the allocated size up to a power of two number of pages. */
478 bucket
= bucket_for_size(bufmgr
, size
);
480 /* If we don't have caching at this size, don't actually round the
483 if (bucket
== NULL
) {
485 if (bo_size
< page_size
)
488 bo_size
= bucket
->size
;
491 mtx_lock(&bufmgr
->lock
);
492 /* Get a buffer out of the cache if available */
494 alloc_from_cache
= false;
495 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
496 /* If the last BO in the cache is idle, then reuse it. Otherwise,
497 * allocate a fresh buffer to avoid stalling.
499 bo
= LIST_ENTRY(struct iris_bo
, bucket
->head
.next
, head
);
500 if (!iris_bo_busy(bo
)) {
501 alloc_from_cache
= true;
505 if (alloc_from_cache
) {
506 if (!iris_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
508 iris_bo_cache_purge_bucket(bufmgr
, bucket
);
512 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
518 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
523 memset(map
, 0, bo_size
);
528 if (alloc_from_cache
) {
529 /* If the cached BO isn't in the right memory zone, free the old
530 * memory and assign it a new address.
532 if (memzone
!= memzone_for_address(bo
->gtt_offset
)) {
533 vma_free(bufmgr
, bo
->gtt_offset
, bo_size
);
534 bo
->gtt_offset
= 0ull;
537 bo
= calloc(1, sizeof(*bo
));
544 struct drm_i915_gem_create create
= { .size
= bo_size
};
546 /* All new BOs we get from the kernel are zeroed, so we don't need to
547 * worry about that here.
549 ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
555 bo
->gem_handle
= create
.handle
;
558 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
560 bo
->tiling_mode
= I915_TILING_NONE
;
561 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
564 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
567 /* Calling set_domain() will allocate pages for the BO outside of the
568 * struct mutex lock in the kernel, which is more efficient than waiting
569 * to create them during the first execbuf that uses the BO.
571 struct drm_i915_gem_set_domain sd
= {
572 .handle
= bo
->gem_handle
,
573 .read_domains
= I915_GEM_DOMAIN_CPU
,
577 if (drm_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0)
581 if (bo
->gtt_offset
== 0ull) {
582 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, 1);
584 if (bo
->gtt_offset
== 0ull)
589 p_atomic_set(&bo
->refcount
, 1);
591 bo
->cache_coherent
= bufmgr
->has_llc
;
594 mtx_unlock(&bufmgr
->lock
);
596 DBG("bo_create: buf %d (%s) %llub\n", bo
->gem_handle
, bo
->name
,
597 (unsigned long long) size
);
604 mtx_unlock(&bufmgr
->lock
);
609 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
612 enum iris_memory_zone memzone
)
614 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
615 0, I915_TILING_NONE
, 0);
619 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
620 uint64_t size
, enum iris_memory_zone memzone
,
621 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
623 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
624 flags
, tiling_mode
, pitch
);
628 * Returns a iris_bo wrapping the given buffer object handle.
630 * This can be used when one application needs to pass a buffer object
634 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
635 const char *name
, unsigned int handle
)
639 /* At the moment most applications only have a few named bo.
640 * For instance, in a DRI client only the render buffers passed
641 * between X and the client are named. And since X returns the
642 * alternating names for the front/back buffer a linear search
643 * provides a sufficiently fast match.
645 mtx_lock(&bufmgr
->lock
);
646 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
648 iris_bo_reference(bo
);
652 struct drm_gem_open open_arg
= { .name
= handle
};
653 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
655 DBG("Couldn't reference %s handle 0x%08x: %s\n",
656 name
, handle
, strerror(errno
));
660 /* Now see if someone has used a prime handle to get this
661 * object from the kernel before by looking through the list
662 * again for a matching gem_handle
664 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
666 iris_bo_reference(bo
);
670 bo
= calloc(1, sizeof(*bo
));
674 p_atomic_set(&bo
->refcount
, 1);
676 bo
->size
= open_arg
.size
;
679 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
680 bo
->gem_handle
= open_arg
.handle
;
682 bo
->global_name
= handle
;
683 bo
->reusable
= false;
685 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
687 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
688 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
690 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
691 ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
695 bo
->tiling_mode
= get_tiling
.tiling_mode
;
696 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
697 /* XXX stride is unknown */
698 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
701 mtx_unlock(&bufmgr
->lock
);
706 mtx_unlock(&bufmgr
->lock
);
711 bo_free(struct iris_bo
*bo
)
713 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
716 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
717 munmap(bo
->map_cpu
, bo
->size
);
720 VG_NOACCESS(bo
->map_wc
, bo
->size
);
721 munmap(bo
->map_wc
, bo
->size
);
724 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
725 munmap(bo
->map_gtt
, bo
->size
);
729 struct hash_entry
*entry
;
731 if (bo
->global_name
) {
732 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
733 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
736 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
737 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
740 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
742 /* Close this object */
743 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
744 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
746 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
747 bo
->gem_handle
, bo
->name
, strerror(errno
));
752 /** Frees all cached buffers significantly older than @time. */
754 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
758 if (bufmgr
->time
== time
)
761 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
762 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
764 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
765 if (time
- bo
->free_time
<= 1)
778 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
780 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
781 struct bo_cache_bucket
*bucket
;
783 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
785 bucket
= bucket_for_size(bufmgr
, bo
->size
);
786 /* Put the buffer into our internal cache for reuse if we can. */
787 if (bufmgr
->bo_reuse
&& bo
->reusable
&& bucket
!= NULL
&&
788 iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
789 bo
->free_time
= time
;
792 list_addtail(&bo
->head
, &bucket
->head
);
799 iris_bo_unreference(struct iris_bo
*bo
)
804 assert(p_atomic_read(&bo
->refcount
) > 0);
806 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
807 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
808 struct timespec time
;
810 clock_gettime(CLOCK_MONOTONIC
, &time
);
812 mtx_lock(&bufmgr
->lock
);
814 if (p_atomic_dec_zero(&bo
->refcount
)) {
815 bo_unreference_final(bo
, time
.tv_sec
);
816 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
819 mtx_unlock(&bufmgr
->lock
);
824 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
828 bool busy
= dbg
&& !bo
->idle
;
829 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
831 iris_bo_wait_rendering(bo
);
833 if (unlikely(busy
)) {
834 elapsed
+= get_time();
835 if (elapsed
> 1e-5) /* 0.01ms */ {
836 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
837 action
, bo
->name
, elapsed
* 1000);
843 print_flags(unsigned flags
)
845 if (flags
& MAP_READ
)
847 if (flags
& MAP_WRITE
)
849 if (flags
& MAP_ASYNC
)
851 if (flags
& MAP_PERSISTENT
)
853 if (flags
& MAP_COHERENT
)
861 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
862 struct iris_bo
*bo
, unsigned flags
)
864 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
866 /* We disallow CPU maps for writing to non-coherent buffers, as the
867 * CPU map can become invalidated when a batch is flushed out, which
868 * can happen at unpredictable times. You should use WC maps instead.
870 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
873 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
875 struct drm_i915_gem_mmap mmap_arg
= {
876 .handle
= bo
->gem_handle
,
879 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
882 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
883 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
886 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
887 VG_DEFINED(map
, bo
->size
);
889 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
890 VG_NOACCESS(map
, bo
->size
);
891 munmap(map
, bo
->size
);
896 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
900 if (!(flags
& MAP_ASYNC
)) {
901 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
904 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
905 /* If we're reusing an existing CPU mapping, the CPU caches may
906 * contain stale data from the last time we read from that mapping.
907 * (With the BO cache, it might even be data from a previous buffer!)
908 * Even if it's a brand new mapping, the kernel may have zeroed the
909 * buffer via CPU writes.
911 * We need to invalidate those cachelines so that we see the latest
912 * contents, and so long as we only read from the CPU mmap we do not
913 * need to write those cachelines back afterwards.
915 * On LLC, the emprical evidence suggests that writes from the GPU
916 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
917 * cachelines. (Other reads, such as the display engine, bypass the
918 * LLC entirely requiring us to keep dirty pixels for the scanout
921 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
928 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
929 struct iris_bo
*bo
, unsigned flags
)
931 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
934 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
936 struct drm_i915_gem_mmap mmap_arg
= {
937 .handle
= bo
->gem_handle
,
939 .flags
= I915_MMAP_WC
,
941 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
944 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
945 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
949 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
950 VG_DEFINED(map
, bo
->size
);
952 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
953 VG_NOACCESS(map
, bo
->size
);
954 munmap(map
, bo
->size
);
959 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
962 if (!(flags
& MAP_ASYNC
)) {
963 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
970 * Perform an uncached mapping via the GTT.
972 * Write access through the GTT is not quite fully coherent. On low power
973 * systems especially, like modern Atoms, we can observe reads from RAM before
974 * the write via GTT has landed. A write memory barrier that flushes the Write
975 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
976 * read after the write as the GTT write suffers a small delay through the GTT
977 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
978 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
979 * flushes prior to execbuf submission. However, if we are not informing the
980 * kernel about our GTT writes, it will not flush before earlier access, such
981 * as when using the cmdparser. Similarly, we need to be careful if we should
982 * ever issue a CPU read immediately following a GTT write.
984 * Telling the kernel about write access also has one more important
985 * side-effect. Upon receiving notification about the write, it cancels any
986 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
987 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
988 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
989 * tracking is handled on the buffer exchange instead.
992 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
993 struct iris_bo
*bo
, unsigned flags
)
995 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
997 /* Get a mapping of the buffer if we haven't before. */
998 if (bo
->map_gtt
== NULL
) {
999 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1001 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1003 /* Get the fake offset back... */
1004 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1006 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1007 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1012 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1013 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1014 if (map
== MAP_FAILED
) {
1015 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1016 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1020 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1021 * already intercept this mmap call. However, for consistency between
1022 * all the mmap paths, we mark the pointer as defined now and mark it
1023 * as inaccessible afterwards.
1025 VG_DEFINED(map
, bo
->size
);
1027 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1028 VG_NOACCESS(map
, bo
->size
);
1029 munmap(map
, bo
->size
);
1032 assert(bo
->map_gtt
);
1034 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1037 if (!(flags
& MAP_ASYNC
)) {
1038 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1045 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1047 if (bo
->cache_coherent
)
1050 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1051 * an LLC platform reads always are coherent (as they are performed via the
1052 * central system agent). It is just the writes that we need to take special
1053 * care to ensure that land in main memory and not stick in the CPU cache.
1055 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1058 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1059 * across batch flushes where the kernel will change cache domains of the
1060 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1062 * Similarly, ASYNC typically means that the buffer will be accessed via
1063 * both the CPU and the GPU simultaneously. Batches may be executed that
1064 * use the BO even while it is mapped. While OpenGL technically disallows
1065 * most drawing while non-persistent mappings are active, we may still use
1066 * the GPU for blits or other operations, causing batches to happen at
1067 * inconvenient times.
1069 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
))
1072 return !(flags
& MAP_WRITE
);
1076 iris_bo_map(struct pipe_debug_callback
*dbg
,
1077 struct iris_bo
*bo
, unsigned flags
)
1079 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1080 return iris_bo_map_gtt(dbg
, bo
, flags
);
1084 if (can_map_cpu(bo
, flags
))
1085 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1087 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1089 /* Allow the attempt to fail by falling back to the GTT where necessary.
1091 * Not every buffer can be mmaped directly using the CPU (or WC), for
1092 * example buffers that wrap stolen memory or are imported from other
1093 * devices. For those, we have little choice but to use a GTT mmapping.
1094 * However, if we use a slow GTT mmapping for reads where we expected fast
1095 * access, that order of magnitude difference in throughput will be clearly
1096 * expressed by angry users.
1098 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1100 if (!map
&& !(flags
& MAP_RAW
)) {
1101 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1103 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1110 iris_bo_subdata(struct iris_bo
*bo
, uint64_t offset
,
1111 uint64_t size
, const void *data
)
1113 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1115 struct drm_i915_gem_pwrite pwrite
= {
1116 .handle
= bo
->gem_handle
,
1119 .data_ptr
= (uint64_t) (uintptr_t) data
,
1122 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PWRITE
, &pwrite
);
1125 DBG("%s:%d: Error writing data to buffer %d: "
1126 "(%"PRIu64
" %"PRIu64
") %s .\n",
1127 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
1133 /** Waits for all GPU rendering with the object to have completed. */
1135 iris_bo_wait_rendering(struct iris_bo
*bo
)
1137 /* We require a kernel recent enough for WAIT_IOCTL support.
1138 * See intel_init_bufmgr()
1140 iris_bo_wait(bo
, -1);
1144 * Waits on a BO for the given amount of time.
1146 * @bo: buffer object to wait for
1147 * @timeout_ns: amount of time to wait in nanoseconds.
1148 * If value is less than 0, an infinite wait will occur.
1150 * Returns 0 if the wait was successful ie. the last batch referencing the
1151 * object has completed within the allotted time. Otherwise some negative return
1152 * value describes the error. Of particular interest is -ETIME when the wait has
1153 * failed to yield the desired result.
1155 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1156 * the operation to give up after a certain amount of time. Another subtle
1157 * difference is the internal locking semantics are different (this variant does
1158 * not hold the lock for the duration of the wait). This makes the wait subject
1159 * to a larger userspace race window.
1161 * The implementation shall wait until the object is no longer actively
1162 * referenced within a batch buffer at the time of the call. The wait will
1163 * not guarantee that the buffer is re-issued via another thread, or an flinked
1164 * handle. Userspace must make sure this race does not occur if such precision
1167 * Note that some kernels have broken the inifite wait for negative values
1168 * promise, upgrade to latest stable kernels if this is the case.
1171 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1173 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1175 /* If we know it's idle, don't bother with the kernel round trip */
1176 if (bo
->idle
&& !bo
->external
)
1179 struct drm_i915_gem_wait wait
= {
1180 .bo_handle
= bo
->gem_handle
,
1181 .timeout_ns
= timeout_ns
,
1183 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1193 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1195 mtx_destroy(&bufmgr
->lock
);
1197 /* Free any cached buffer objects we were going to reuse */
1198 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1199 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1201 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1202 list_del(&bo
->head
);
1207 for (int i
= 0; i
< IRIS_MEMZONE_COUNT
; i
++)
1208 util_dynarray_fini(&bucket
->vma_list
[i
]);
1211 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1212 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1218 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1221 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1222 struct drm_i915_gem_set_tiling set_tiling
;
1225 if (bo
->global_name
== 0 &&
1226 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1229 memset(&set_tiling
, 0, sizeof(set_tiling
));
1231 /* set_tiling is slightly broken and overwrites the
1232 * input on the error path, so we have to open code
1235 set_tiling
.handle
= bo
->gem_handle
;
1236 set_tiling
.tiling_mode
= tiling_mode
;
1237 set_tiling
.stride
= stride
;
1239 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1240 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1244 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1245 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1246 bo
->stride
= set_tiling
.stride
;
1251 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1252 uint32_t *swizzle_mode
)
1254 *tiling_mode
= bo
->tiling_mode
;
1255 *swizzle_mode
= bo
->swizzle_mode
;
1260 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
)
1265 mtx_lock(&bufmgr
->lock
);
1266 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1268 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1270 mtx_unlock(&bufmgr
->lock
);
1275 * See if the kernel has already returned this buffer to us. Just as
1276 * for named buffers, we must not create two bo's pointing at the same
1279 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1281 iris_bo_reference(bo
);
1285 bo
= calloc(1, sizeof(*bo
));
1289 p_atomic_set(&bo
->refcount
, 1);
1291 /* Determine size of bo. The fd-to-handle ioctl really should
1292 * return the size, but it doesn't. If we have kernel 3.12 or
1293 * later, we can lseek on the prime fd to get the size. Older
1294 * kernels will just fail, in which case we fall back to the
1295 * provided (estimated or guess size). */
1296 ret
= lseek(prime_fd
, 0, SEEK_END
);
1300 bo
->bufmgr
= bufmgr
;
1301 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1303 bo
->gem_handle
= handle
;
1304 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1307 bo
->reusable
= false;
1308 bo
->external
= true;
1309 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1311 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1312 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1315 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1316 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1317 /* XXX stride is unknown */
1320 mtx_unlock(&bufmgr
->lock
);
1325 mtx_unlock(&bufmgr
->lock
);
1330 iris_bo_make_external(struct iris_bo
*bo
)
1332 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1334 if (!bo
->external
) {
1335 mtx_lock(&bufmgr
->lock
);
1336 if (!bo
->external
) {
1337 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1338 bo
->external
= true;
1340 mtx_unlock(&bufmgr
->lock
);
1345 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1347 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1349 iris_bo_make_external(bo
);
1351 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1352 DRM_CLOEXEC
, prime_fd
) != 0)
1355 bo
->reusable
= false;
1361 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1363 iris_bo_make_external(bo
);
1365 return bo
->gem_handle
;
1369 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1371 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1373 if (!bo
->global_name
) {
1374 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1376 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1379 iris_bo_make_external(bo
);
1380 mtx_lock(&bufmgr
->lock
);
1381 if (!bo
->global_name
) {
1382 bo
->global_name
= flink
.name
;
1383 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1385 mtx_unlock(&bufmgr
->lock
);
1387 bo
->reusable
= false;
1390 *name
= bo
->global_name
;
1395 * Enables unlimited caching of buffer objects for reuse.
1397 * This is potentially very memory expensive, as the cache at each bucket
1398 * size is only bounded by how many buffers of that size we've managed to have
1399 * in flight at once.
1402 iris_bufmgr_enable_reuse(struct iris_bufmgr
*bufmgr
)
1404 bufmgr
->bo_reuse
= true;
1408 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1410 unsigned int i
= bufmgr
->num_buckets
;
1412 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1414 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1415 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++)
1416 util_dynarray_init(&bufmgr
->cache_bucket
[i
].vma_list
[z
], NULL
);
1417 bufmgr
->cache_bucket
[i
].size
= size
;
1418 bufmgr
->num_buckets
++;
1420 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1421 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1422 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1426 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1428 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1430 /* OK, so power of two buckets was too wasteful of memory.
1431 * Give 3 other sizes between each power of two, to hopefully
1432 * cover things accurately enough. (The alternative is
1433 * probably to just go for exact matching of sizes, and assume
1434 * that for things like composited window resize the tiled
1435 * width/height alignment and rounding of sizes to pages will
1436 * get us useful cache hit rates anyway)
1438 add_bucket(bufmgr
, PAGE_SIZE
);
1439 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1440 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1442 /* Initialize the linked lists for BO reuse cache. */
1443 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1444 add_bucket(bufmgr
, size
);
1446 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1447 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1448 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1453 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1455 struct drm_i915_gem_context_create create
= { };
1456 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1458 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1462 return create
.ctx_id
;
1466 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1470 struct drm_i915_gem_context_param p
= {
1472 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1478 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1485 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1487 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1490 drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1491 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1497 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1499 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1500 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1502 *result
= reg_read
.val
;
1507 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1508 * and manage map buffer objections.
1510 * \param fd File descriptor of the opened DRM device.
1512 struct iris_bufmgr
*
1513 iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
)
1515 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1519 /* Handles to buffer objects belong to the device fd and are not
1520 * reference counted by the kernel. If the same fd is used by
1521 * multiple parties (threads sharing the same screen bufmgr, or
1522 * even worse the same device fd passed to multiple libraries)
1523 * ownership of those handles is shared by those independent parties.
1525 * Don't do this! Ensure that each library/bufmgr has its own device
1526 * fd so that its namespace does not clash with another.
1530 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1535 bufmgr
->has_llc
= devinfo
->has_llc
;
1537 const uint64_t _4GB
= 1ull << 32;
1539 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1541 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1543 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1545 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1546 3 * _4GB
, (1ull << 48) - 3 * _4GB
);
1548 init_cache_buckets(bufmgr
);
1550 bufmgr
->name_table
=
1551 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1552 bufmgr
->handle_table
=
1553 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);