2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
35 #include <util/u_atomic.h>
42 #include <sys/ioctl.h>
45 #include <sys/types.h>
51 #include "common/gen_aux_map.h"
52 #include "common/gen_clflush.h"
53 #include "dev/gen_debug.h"
54 #include "common/gen_gem.h"
55 #include "dev/gen_device_info.h"
56 #include "main/macros.h"
57 #include "os/os_mman.h"
58 #include "util/debug.h"
59 #include "util/macros.h"
60 #include "util/hash_table.h"
61 #include "util/list.h"
62 #include "util/os_file.h"
63 #include "util/u_dynarray.h"
65 #include "iris_bufmgr.h"
66 #include "iris_context.h"
69 #include "drm-uapi/i915_drm.h"
79 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
80 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
81 * leaked. All because it does not call VG(cli_free) from its
82 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
83 * and allocation, we mark it available for use upon mmapping and remove
86 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
87 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
89 #define PAGE_SIZE 4096
91 #define WARN_ONCE(cond, fmt...) do { \
92 if (unlikely(cond)) { \
93 static bool _warned = false; \
95 fprintf(stderr, "WARNING: "); \
96 fprintf(stderr, fmt); \
102 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
105 atomic_add_unless(int *v
, int add
, int unless
)
108 c
= p_atomic_read(v
);
109 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
115 memzone_name(enum iris_memory_zone memzone
)
117 const char *names
[] = {
118 [IRIS_MEMZONE_SHADER
] = "shader",
119 [IRIS_MEMZONE_BINDER
] = "binder",
120 [IRIS_MEMZONE_SURFACE
] = "surface",
121 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
122 [IRIS_MEMZONE_OTHER
] = "other",
123 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
125 assert(memzone
< ARRAY_SIZE(names
));
126 return names
[memzone
];
129 struct bo_cache_bucket
{
130 /** List of cached BOs. */
131 struct list_head head
;
133 /** Size of this bucket, in bytes. */
138 /** File descriptor associated with a handle export. */
141 /** GEM handle in drm_fd */
144 struct list_head link
;
149 * List into the list of bufmgr.
151 struct list_head link
;
159 /** Array of lists of cached gem objects of power-of-two sizes */
160 struct bo_cache_bucket cache_bucket
[14 * 4];
164 struct hash_table
*name_table
;
165 struct hash_table
*handle_table
;
168 * List of BOs which we've effectively freed, but are hanging on to
169 * until they're idle before closing and returning the VMA.
171 struct list_head zombie_list
;
173 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
176 bool has_mmap_offset
:1;
177 bool has_tiling_uapi
:1;
180 struct gen_aux_map_context
*aux_map_ctx
;
183 static mtx_t global_bufmgr_list_mutex
= _MTX_INITIALIZER_NP
;
184 static struct list_head global_bufmgr_list
= {
185 .next
= &global_bufmgr_list
,
186 .prev
= &global_bufmgr_list
,
189 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
192 static void bo_free(struct iris_bo
*bo
);
194 static struct iris_bo
*
195 find_and_ref_external_bo(struct hash_table
*ht
, unsigned int key
)
197 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
198 struct iris_bo
*bo
= entry
? entry
->data
: NULL
;
201 assert(bo
->external
);
202 assert(!bo
->reusable
);
204 /* Being non-reusable, the BO cannot be in the cache lists, but it
205 * may be in the zombie list if it had reached zero references, but
206 * we hadn't yet closed it...and then reimported the same BO. If it
207 * is, then remove it since it's now been resurrected.
209 if (bo
->head
.prev
|| bo
->head
.next
)
212 iris_bo_reference(bo
);
219 * This function finds the correct bucket fit for the input size.
220 * The function works with O(1) complexity when the requested size
221 * was queried instead of iterating the size through all the buckets.
223 static struct bo_cache_bucket
*
224 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
226 /* Calculating the pages and rounding up to the page size. */
227 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
229 /* Row Bucket sizes clz((x-1) | 3) Row Column
230 * in pages stride size
231 * 0: 1 2 3 4 -> 30 30 30 30 4 1
232 * 1: 5 6 7 8 -> 29 29 29 29 4 1
233 * 2: 10 12 14 16 -> 28 28 28 28 8 2
234 * 3: 20 24 28 32 -> 27 27 27 27 16 4
236 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
237 const unsigned row_max_pages
= 4 << row
;
239 /* The '& ~2' is the special case for row 1. In row 1, max pages /
240 * 2 is 2, but the previous row maximum is zero (because there is
241 * no previous row). All row maximum sizes are power of 2, so that
242 * is the only case where that bit will be set.
244 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
245 int col_size_log2
= row
- 1;
246 col_size_log2
+= (col_size_log2
< 0);
248 const unsigned col
= (pages
- prev_row_max_pages
+
249 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
251 /* Calculating the index based on the row and column. */
252 const unsigned index
= (row
* 4) + (col
- 1);
254 return (index
< bufmgr
->num_buckets
) ?
255 &bufmgr
->cache_bucket
[index
] : NULL
;
258 enum iris_memory_zone
259 iris_memzone_for_address(uint64_t address
)
261 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
262 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
263 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
264 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
265 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
267 if (address
>= IRIS_MEMZONE_OTHER_START
)
268 return IRIS_MEMZONE_OTHER
;
270 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
271 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
273 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
274 return IRIS_MEMZONE_DYNAMIC
;
276 if (address
>= IRIS_MEMZONE_SURFACE_START
)
277 return IRIS_MEMZONE_SURFACE
;
279 if (address
>= IRIS_MEMZONE_BINDER_START
)
280 return IRIS_MEMZONE_BINDER
;
282 return IRIS_MEMZONE_SHADER
;
286 * Allocate a section of virtual memory for a buffer, assigning an address.
288 * This uses either the bucket allocator for the given size, or the large
289 * object allocator (util_vma).
292 vma_alloc(struct iris_bufmgr
*bufmgr
,
293 enum iris_memory_zone memzone
,
297 /* Force alignment to be some number of pages */
298 alignment
= ALIGN(alignment
, PAGE_SIZE
);
300 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
301 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
303 /* The binder handles its own allocations. Return non-zero here. */
304 if (memzone
== IRIS_MEMZONE_BINDER
)
305 return IRIS_MEMZONE_BINDER_START
;
308 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
310 assert((addr
>> 48ull) == 0);
311 assert((addr
% alignment
) == 0);
313 return gen_canonical_address(addr
);
317 vma_free(struct iris_bufmgr
*bufmgr
,
321 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
324 /* Un-canonicalize the address. */
325 address
= gen_48b_address(address
);
330 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
332 /* The binder handles its own allocations. */
333 if (memzone
== IRIS_MEMZONE_BINDER
)
336 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
340 iris_bo_busy(struct iris_bo
*bo
)
342 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
343 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
345 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
347 bo
->idle
= !busy
.busy
;
354 iris_bo_madvise(struct iris_bo
*bo
, int state
)
356 struct drm_i915_gem_madvise madv
= {
357 .handle
= bo
->gem_handle
,
362 gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
364 return madv
.retained
;
367 static struct iris_bo
*
370 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
374 list_inithead(&bo
->exports
);
376 bo
->hash
= _mesa_hash_pointer(bo
);
381 static struct iris_bo
*
382 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
383 struct bo_cache_bucket
*bucket
,
385 enum iris_memory_zone memzone
,
392 struct iris_bo
*bo
= NULL
;
394 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
395 /* Try a little harder to find one that's already in the right memzone */
396 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
399 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
400 * either falling back to a non-matching memzone, or if that fails,
401 * allocating a fresh buffer.
403 if (iris_bo_busy(cur
))
406 list_del(&cur
->head
);
408 /* Tell the kernel we need this BO. If it still exists, we're done! */
409 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
414 /* This BO was purged, throw it out and keep looking. */
421 if (bo
->aux_map_address
) {
422 /* This buffer was associated with an aux-buffer range. We make sure
423 * that buffers are not reused from the cache while the buffer is (busy)
424 * being used by an executing batch. Since we are here, the buffer is no
425 * longer being used by a batch and the buffer was deleted (in order to
426 * end up in the cache). Therefore its old aux-buffer range can be
427 * removed from the aux-map.
429 if (bo
->bufmgr
->aux_map_ctx
)
430 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
432 bo
->aux_map_address
= 0;
435 /* If the cached BO isn't in the right memory zone, or the alignment
436 * isn't sufficient, free the old memory and assign it a new address.
438 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
) ||
439 bo
->gtt_offset
% alignment
!= 0) {
440 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
441 bo
->gtt_offset
= 0ull;
444 /* Zero the contents if necessary. If this fails, fall back to
445 * allocating a fresh BO, which will always be zeroed by the kernel.
447 if (flags
& BO_ALLOC_ZEROED
) {
448 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
450 memset(map
, 0, bo
->size
);
460 static struct iris_bo
*
461 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
463 struct iris_bo
*bo
= bo_calloc();
467 struct drm_i915_gem_create create
= { .size
= bo_size
};
469 /* All new BOs we get from the kernel are zeroed, so we don't need to
470 * worry about that here.
472 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
477 bo
->gem_handle
= create
.handle
;
481 bo
->tiling_mode
= I915_TILING_NONE
;
484 /* Calling set_domain() will allocate pages for the BO outside of the
485 * struct mutex lock in the kernel, which is more efficient than waiting
486 * to create them during the first execbuf that uses the BO.
488 struct drm_i915_gem_set_domain sd
= {
489 .handle
= bo
->gem_handle
,
490 .read_domains
= I915_GEM_DOMAIN_CPU
,
494 if (gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
502 static struct iris_bo
*
503 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
507 enum iris_memory_zone memzone
,
509 uint32_t tiling_mode
,
513 unsigned int page_size
= getpagesize();
514 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
516 /* Round the size up to the bucket size, or if we don't have caching
517 * at this size, a multiple of the page size.
520 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
522 mtx_lock(&bufmgr
->lock
);
524 /* Get a buffer out of the cache if available. First, we try to find
525 * one with a matching memory zone so we can avoid reallocating VMA.
527 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
, true);
529 /* If that fails, we try for any cached BO, without matching memzone. */
531 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
,
535 mtx_unlock(&bufmgr
->lock
);
538 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
543 if (bo
->gtt_offset
== 0ull) {
544 mtx_lock(&bufmgr
->lock
);
545 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, alignment
);
546 mtx_unlock(&bufmgr
->lock
);
548 if (bo
->gtt_offset
== 0ull)
552 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
556 p_atomic_set(&bo
->refcount
, 1);
557 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
558 bo
->cache_coherent
= bufmgr
->has_llc
;
560 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
562 /* By default, capture all driver-internal buffers like shader kernels,
563 * surface states, dynamic states, border colors, and so on.
565 if (memzone
< IRIS_MEMZONE_OTHER
)
566 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
568 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
569 struct drm_i915_gem_caching arg
= {
570 .handle
= bo
->gem_handle
,
573 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
574 bo
->cache_coherent
= true;
575 bo
->reusable
= false;
579 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
580 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
590 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
593 enum iris_memory_zone memzone
)
595 return bo_alloc_internal(bufmgr
, name
, size
, 1, memzone
,
596 0, I915_TILING_NONE
, 0);
600 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
601 uint64_t size
, uint32_t alignment
,
602 enum iris_memory_zone memzone
,
603 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
605 return bo_alloc_internal(bufmgr
, name
, size
, alignment
, memzone
,
606 flags
, tiling_mode
, pitch
);
610 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
611 void *ptr
, size_t size
,
612 enum iris_memory_zone memzone
)
614 struct drm_gem_close close
= { 0, };
621 struct drm_i915_gem_userptr arg
= {
622 .user_ptr
= (uintptr_t)ptr
,
625 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
627 bo
->gem_handle
= arg
.handle
;
629 /* Check the buffer for validity before we try and use it in a batch */
630 struct drm_i915_gem_set_domain sd
= {
631 .handle
= bo
->gem_handle
,
632 .read_domains
= I915_GEM_DOMAIN_CPU
,
634 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
642 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
644 mtx_lock(&bufmgr
->lock
);
645 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
646 mtx_unlock(&bufmgr
->lock
);
648 if (bo
->gtt_offset
== 0ull)
651 p_atomic_set(&bo
->refcount
, 1);
653 bo
->cache_coherent
= true;
660 close
.handle
= bo
->gem_handle
;
661 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
668 * Returns a iris_bo wrapping the given buffer object handle.
670 * This can be used when one application needs to pass a buffer object
674 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
675 const char *name
, unsigned int handle
)
679 /* At the moment most applications only have a few named bo.
680 * For instance, in a DRI client only the render buffers passed
681 * between X and the client are named. And since X returns the
682 * alternating names for the front/back buffer a linear search
683 * provides a sufficiently fast match.
685 mtx_lock(&bufmgr
->lock
);
686 bo
= find_and_ref_external_bo(bufmgr
->name_table
, handle
);
690 struct drm_gem_open open_arg
= { .name
= handle
};
691 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
693 DBG("Couldn't reference %s handle 0x%08x: %s\n",
694 name
, handle
, strerror(errno
));
698 /* Now see if someone has used a prime handle to get this
699 * object from the kernel before by looking through the list
700 * again for a matching gem_handle
702 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, open_arg
.handle
);
710 p_atomic_set(&bo
->refcount
, 1);
712 bo
->size
= open_arg
.size
;
714 bo
->gem_handle
= open_arg
.handle
;
716 bo
->global_name
= handle
;
717 bo
->reusable
= false;
719 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
720 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
722 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
723 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
725 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
726 ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
730 bo
->tiling_mode
= get_tiling
.tiling_mode
;
732 /* XXX stride is unknown */
733 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
736 mtx_unlock(&bufmgr
->lock
);
741 mtx_unlock(&bufmgr
->lock
);
746 bo_close(struct iris_bo
*bo
)
748 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
751 struct hash_entry
*entry
;
753 if (bo
->global_name
) {
754 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
755 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
758 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
759 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
761 list_for_each_entry_safe(struct bo_export
, export
, &bo
->exports
, link
) {
762 struct drm_gem_close close
= { .handle
= export
->gem_handle
};
763 gen_ioctl(export
->drm_fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
765 list_del(&export
->link
);
769 assert(list_is_empty(&bo
->exports
));
772 /* Close this object */
773 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
774 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
776 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
777 bo
->gem_handle
, bo
->name
, strerror(errno
));
780 if (bo
->aux_map_address
&& bo
->bufmgr
->aux_map_ctx
) {
781 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
785 /* Return the VMA for reuse */
786 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
792 bo_free(struct iris_bo
*bo
)
794 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
796 if (bo
->map_cpu
&& !bo
->userptr
) {
797 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
798 os_munmap(bo
->map_cpu
, bo
->size
);
801 VG_NOACCESS(bo
->map_wc
, bo
->size
);
802 os_munmap(bo
->map_wc
, bo
->size
);
805 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
806 os_munmap(bo
->map_gtt
, bo
->size
);
812 /* Defer closing the GEM BO and returning the VMA for reuse until the
813 * BO is idle. Just move it to the dead list for now.
815 list_addtail(&bo
->head
, &bufmgr
->zombie_list
);
819 /** Frees all cached buffers significantly older than @time. */
821 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
825 if (bufmgr
->time
== time
)
828 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
829 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
831 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
832 if (time
- bo
->free_time
<= 1)
841 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
842 /* Stop once we reach a busy BO - all others past this point were
843 * freed more recently so are likely also busy.
845 if (!bo
->idle
&& iris_bo_busy(bo
))
856 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
858 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
859 struct bo_cache_bucket
*bucket
;
861 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
865 bucket
= bucket_for_size(bufmgr
, bo
->size
);
866 /* Put the buffer into our internal cache for reuse if we can. */
867 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
868 bo
->free_time
= time
;
871 list_addtail(&bo
->head
, &bucket
->head
);
878 iris_bo_unreference(struct iris_bo
*bo
)
883 assert(p_atomic_read(&bo
->refcount
) > 0);
885 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
886 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
887 struct timespec time
;
889 clock_gettime(CLOCK_MONOTONIC
, &time
);
891 mtx_lock(&bufmgr
->lock
);
893 if (p_atomic_dec_zero(&bo
->refcount
)) {
894 bo_unreference_final(bo
, time
.tv_sec
);
895 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
898 mtx_unlock(&bufmgr
->lock
);
903 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
907 bool busy
= dbg
&& !bo
->idle
;
908 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
910 iris_bo_wait_rendering(bo
);
912 if (unlikely(busy
)) {
913 elapsed
+= get_time();
914 if (elapsed
> 1e-5) /* 0.01ms */ {
915 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
916 action
, bo
->name
, elapsed
* 1000);
922 print_flags(unsigned flags
)
924 if (flags
& MAP_READ
)
926 if (flags
& MAP_WRITE
)
928 if (flags
& MAP_ASYNC
)
930 if (flags
& MAP_PERSISTENT
)
932 if (flags
& MAP_COHERENT
)
940 iris_bo_gem_mmap_legacy(struct pipe_debug_callback
*dbg
,
941 struct iris_bo
*bo
, bool wc
)
943 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
945 struct drm_i915_gem_mmap mmap_arg
= {
946 .handle
= bo
->gem_handle
,
948 .flags
= wc
? I915_MMAP_WC
: 0,
951 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
953 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
954 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
957 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
963 iris_bo_gem_mmap_offset(struct pipe_debug_callback
*dbg
, struct iris_bo
*bo
,
966 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
968 struct drm_i915_gem_mmap_offset mmap_arg
= {
969 .handle
= bo
->gem_handle
,
970 .flags
= wc
? I915_MMAP_OFFSET_WC
: I915_MMAP_OFFSET_WB
,
973 /* Get the fake offset back */
974 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_OFFSET
, &mmap_arg
);
976 DBG("%s:%d: Error preparing buffer %d (%s): %s .\n",
977 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
982 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
, MAP_SHARED
,
983 bufmgr
->fd
, mmap_arg
.offset
);
984 if (map
== MAP_FAILED
) {
985 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
986 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
994 iris_bo_gem_mmap(struct pipe_debug_callback
*dbg
, struct iris_bo
*bo
, bool wc
)
996 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
998 if (bufmgr
->has_mmap_offset
)
999 return iris_bo_gem_mmap_offset(dbg
, bo
, wc
);
1001 return iris_bo_gem_mmap_legacy(dbg
, bo
, wc
);
1005 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
1006 struct iris_bo
*bo
, unsigned flags
)
1008 /* We disallow CPU maps for writing to non-coherent buffers, as the
1009 * CPU map can become invalidated when a batch is flushed out, which
1010 * can happen at unpredictable times. You should use WC maps instead.
1012 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
1015 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1016 void *map
= iris_bo_gem_mmap(dbg
, bo
, false);
1021 VG_DEFINED(map
, bo
->size
);
1023 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
1024 VG_NOACCESS(map
, bo
->size
);
1025 os_munmap(map
, bo
->size
);
1028 assert(bo
->map_cpu
);
1030 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
1034 if (!(flags
& MAP_ASYNC
)) {
1035 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
1038 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
1039 /* If we're reusing an existing CPU mapping, the CPU caches may
1040 * contain stale data from the last time we read from that mapping.
1041 * (With the BO cache, it might even be data from a previous buffer!)
1042 * Even if it's a brand new mapping, the kernel may have zeroed the
1043 * buffer via CPU writes.
1045 * We need to invalidate those cachelines so that we see the latest
1046 * contents, and so long as we only read from the CPU mmap we do not
1047 * need to write those cachelines back afterwards.
1049 * On LLC, the emprical evidence suggests that writes from the GPU
1050 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
1051 * cachelines. (Other reads, such as the display engine, bypass the
1052 * LLC entirely requiring us to keep dirty pixels for the scanout
1053 * out of any cache.)
1055 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
1062 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
1063 struct iris_bo
*bo
, unsigned flags
)
1066 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1067 void *map
= iris_bo_gem_mmap(dbg
, bo
, true);
1072 VG_DEFINED(map
, bo
->size
);
1074 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
1075 VG_NOACCESS(map
, bo
->size
);
1076 os_munmap(map
, bo
->size
);
1081 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1084 if (!(flags
& MAP_ASYNC
)) {
1085 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
1092 * Perform an uncached mapping via the GTT.
1094 * Write access through the GTT is not quite fully coherent. On low power
1095 * systems especially, like modern Atoms, we can observe reads from RAM before
1096 * the write via GTT has landed. A write memory barrier that flushes the Write
1097 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1098 * read after the write as the GTT write suffers a small delay through the GTT
1099 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1100 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1101 * flushes prior to execbuf submission. However, if we are not informing the
1102 * kernel about our GTT writes, it will not flush before earlier access, such
1103 * as when using the cmdparser. Similarly, we need to be careful if we should
1104 * ever issue a CPU read immediately following a GTT write.
1106 * Telling the kernel about write access also has one more important
1107 * side-effect. Upon receiving notification about the write, it cancels any
1108 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1109 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1110 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1111 * tracking is handled on the buffer exchange instead.
1114 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1115 struct iris_bo
*bo
, unsigned flags
)
1117 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1119 /* If we don't support get/set_tiling, there's no support for GTT mapping
1120 * either (it won't do any de-tiling for us).
1122 assert(bufmgr
->has_tiling_uapi
);
1124 /* Get a mapping of the buffer if we haven't before. */
1125 if (bo
->map_gtt
== NULL
) {
1126 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1128 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1130 /* Get the fake offset back... */
1131 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1133 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1134 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1139 void *map
= os_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1140 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1141 if (map
== MAP_FAILED
) {
1142 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1143 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1147 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1148 * already intercept this mmap call. However, for consistency between
1149 * all the mmap paths, we mark the pointer as defined now and mark it
1150 * as inaccessible afterwards.
1152 VG_DEFINED(map
, bo
->size
);
1154 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1155 VG_NOACCESS(map
, bo
->size
);
1156 os_munmap(map
, bo
->size
);
1159 assert(bo
->map_gtt
);
1161 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1164 if (!(flags
& MAP_ASYNC
)) {
1165 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1172 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1174 if (bo
->cache_coherent
)
1177 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1178 * an LLC platform reads always are coherent (as they are performed via the
1179 * central system agent). It is just the writes that we need to take special
1180 * care to ensure that land in main memory and not stick in the CPU cache.
1182 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1185 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1186 * across batch flushes where the kernel will change cache domains of the
1187 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1189 * Similarly, ASYNC typically means that the buffer will be accessed via
1190 * both the CPU and the GPU simultaneously. Batches may be executed that
1191 * use the BO even while it is mapped. While OpenGL technically disallows
1192 * most drawing while non-persistent mappings are active, we may still use
1193 * the GPU for blits or other operations, causing batches to happen at
1194 * inconvenient times.
1196 * If RAW is set, we expect the caller to be able to handle a WC buffer
1197 * more efficiently than the involuntary clflushes.
1199 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1202 return !(flags
& MAP_WRITE
);
1206 iris_bo_map(struct pipe_debug_callback
*dbg
,
1207 struct iris_bo
*bo
, unsigned flags
)
1209 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1210 return iris_bo_map_gtt(dbg
, bo
, flags
);
1214 if (can_map_cpu(bo
, flags
))
1215 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1217 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1219 /* Allow the attempt to fail by falling back to the GTT where necessary.
1221 * Not every buffer can be mmaped directly using the CPU (or WC), for
1222 * example buffers that wrap stolen memory or are imported from other
1223 * devices. For those, we have little choice but to use a GTT mmapping.
1224 * However, if we use a slow GTT mmapping for reads where we expected fast
1225 * access, that order of magnitude difference in throughput will be clearly
1226 * expressed by angry users.
1228 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1230 if (!map
&& !(flags
& MAP_RAW
)) {
1231 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1233 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1239 /** Waits for all GPU rendering with the object to have completed. */
1241 iris_bo_wait_rendering(struct iris_bo
*bo
)
1243 /* We require a kernel recent enough for WAIT_IOCTL support.
1244 * See intel_init_bufmgr()
1246 iris_bo_wait(bo
, -1);
1250 * Waits on a BO for the given amount of time.
1252 * @bo: buffer object to wait for
1253 * @timeout_ns: amount of time to wait in nanoseconds.
1254 * If value is less than 0, an infinite wait will occur.
1256 * Returns 0 if the wait was successful ie. the last batch referencing the
1257 * object has completed within the allotted time. Otherwise some negative return
1258 * value describes the error. Of particular interest is -ETIME when the wait has
1259 * failed to yield the desired result.
1261 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1262 * the operation to give up after a certain amount of time. Another subtle
1263 * difference is the internal locking semantics are different (this variant does
1264 * not hold the lock for the duration of the wait). This makes the wait subject
1265 * to a larger userspace race window.
1267 * The implementation shall wait until the object is no longer actively
1268 * referenced within a batch buffer at the time of the call. The wait will
1269 * not guarantee that the buffer is re-issued via another thread, or an flinked
1270 * handle. Userspace must make sure this race does not occur if such precision
1273 * Note that some kernels have broken the inifite wait for negative values
1274 * promise, upgrade to latest stable kernels if this is the case.
1277 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1279 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1281 /* If we know it's idle, don't bother with the kernel round trip */
1282 if (bo
->idle
&& !bo
->external
)
1285 struct drm_i915_gem_wait wait
= {
1286 .bo_handle
= bo
->gem_handle
,
1287 .timeout_ns
= timeout_ns
,
1289 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1299 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1301 /* Free aux-map buffers */
1302 gen_aux_map_finish(bufmgr
->aux_map_ctx
);
1304 /* bufmgr will no longer try to free VMA entries in the aux-map */
1305 bufmgr
->aux_map_ctx
= NULL
;
1307 mtx_destroy(&bufmgr
->lock
);
1309 /* Free any cached buffer objects we were going to reuse */
1310 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1311 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1313 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1314 list_del(&bo
->head
);
1320 /* Close any buffer objects on the dead list. */
1321 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
1322 list_del(&bo
->head
);
1326 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1327 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1329 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1330 if (z
!= IRIS_MEMZONE_BINDER
)
1331 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1340 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1343 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1344 struct drm_i915_gem_set_tiling set_tiling
;
1347 if (bo
->global_name
== 0 &&
1348 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1351 /* If we can't do map_gtt, the set/get_tiling API isn't useful. And it's
1352 * actually not supported by the kernel in those cases.
1354 if (!bufmgr
->has_tiling_uapi
) {
1355 bo
->tiling_mode
= tiling_mode
;
1356 bo
->stride
= stride
;
1360 memset(&set_tiling
, 0, sizeof(set_tiling
));
1362 /* set_tiling is slightly broken and overwrites the
1363 * input on the error path, so we have to open code
1366 set_tiling
.handle
= bo
->gem_handle
;
1367 set_tiling
.tiling_mode
= tiling_mode
;
1368 set_tiling
.stride
= stride
;
1370 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1371 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1375 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1376 bo
->stride
= set_tiling
.stride
;
1381 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
,
1382 int tiling
, uint32_t stride
)
1387 mtx_lock(&bufmgr
->lock
);
1388 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1390 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1392 mtx_unlock(&bufmgr
->lock
);
1397 * See if the kernel has already returned this buffer to us. Just as
1398 * for named buffers, we must not create two bo's pointing at the same
1401 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, handle
);
1409 p_atomic_set(&bo
->refcount
, 1);
1411 /* Determine size of bo. The fd-to-handle ioctl really should
1412 * return the size, but it doesn't. If we have kernel 3.12 or
1413 * later, we can lseek on the prime fd to get the size. Older
1414 * kernels will just fail, in which case we fall back to the
1415 * provided (estimated or guess size). */
1416 ret
= lseek(prime_fd
, 0, SEEK_END
);
1420 bo
->bufmgr
= bufmgr
;
1422 bo
->reusable
= false;
1423 bo
->external
= true;
1424 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1426 /* From the Bspec, Memory Compression - Gen12:
1428 * The base address for the surface has to be 64K page aligned and the
1429 * surface is expected to be padded in the virtual domain to be 4 4K
1432 * The dmabuf may contain a compressed surface. Align the BO to 64KB just
1433 * in case. We always align to 64KB even on platforms where we don't need
1434 * to, because it's a fairly reasonable thing to do anyway.
1437 vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 64 * 1024);
1439 bo
->gem_handle
= handle
;
1440 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1442 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1443 if (!bufmgr
->has_tiling_uapi
)
1444 get_tiling
.tiling_mode
= I915_TILING_NONE
;
1445 else if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1449 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1450 /* XXX stride is unknown */
1452 /* Modifiers path */
1453 if (get_tiling
.tiling_mode
== tiling
|| !bufmgr
->has_tiling_uapi
) {
1454 bo
->tiling_mode
= tiling
;
1455 bo
->stride
= stride
;
1456 } else if (bo_set_tiling_internal(bo
, tiling
, stride
)) {
1462 mtx_unlock(&bufmgr
->lock
);
1467 mtx_unlock(&bufmgr
->lock
);
1472 iris_bo_make_external_locked(struct iris_bo
*bo
)
1474 if (!bo
->external
) {
1475 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1476 /* If a BO is going to be used externally, it could be sent to the
1477 * display HW. So make sure our CPU mappings don't assume cache
1478 * coherency since display is outside that cache.
1480 bo
->cache_coherent
= false;
1481 bo
->external
= true;
1482 bo
->reusable
= false;
1487 iris_bo_make_external(struct iris_bo
*bo
)
1489 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1492 assert(!bo
->reusable
);
1496 mtx_lock(&bufmgr
->lock
);
1497 iris_bo_make_external_locked(bo
);
1498 mtx_unlock(&bufmgr
->lock
);
1502 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1504 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1506 iris_bo_make_external(bo
);
1508 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1509 DRM_CLOEXEC
, prime_fd
) != 0)
1516 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1518 iris_bo_make_external(bo
);
1520 return bo
->gem_handle
;
1524 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1526 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1528 if (!bo
->global_name
) {
1529 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1531 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1534 mtx_lock(&bufmgr
->lock
);
1535 if (!bo
->global_name
) {
1536 iris_bo_make_external_locked(bo
);
1537 bo
->global_name
= flink
.name
;
1538 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1540 mtx_unlock(&bufmgr
->lock
);
1543 *name
= bo
->global_name
;
1548 iris_bo_export_gem_handle_for_device(struct iris_bo
*bo
, int drm_fd
,
1549 uint32_t *out_handle
)
1551 /* Only add the new GEM handle to the list of export if it belongs to a
1552 * different GEM device. Otherwise we might close the same buffer multiple
1555 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1556 int ret
= os_same_file_description(drm_fd
, bufmgr
->fd
);
1558 "Kernel has no file descriptor comparison support: %s\n",
1561 *out_handle
= iris_bo_export_gem_handle(bo
);
1565 struct bo_export
*export
= calloc(1, sizeof(*export
));
1569 export
->drm_fd
= drm_fd
;
1572 int err
= iris_bo_export_dmabuf(bo
, &dmabuf_fd
);
1578 mtx_lock(&bufmgr
->lock
);
1579 err
= drmPrimeFDToHandle(drm_fd
, dmabuf_fd
, &export
->gem_handle
);
1582 mtx_unlock(&bufmgr
->lock
);
1588 list_for_each_entry(struct bo_export
, iter
, &bo
->exports
, link
) {
1589 if (iter
->drm_fd
!= drm_fd
)
1591 /* Here we assume that for a given DRM fd, we'll always get back the
1592 * same GEM handle for a given buffer.
1594 assert(iter
->gem_handle
== export
->gem_handle
);
1601 list_addtail(&export
->link
, &bo
->exports
);
1603 mtx_unlock(&bufmgr
->lock
);
1605 *out_handle
= export
->gem_handle
;
1611 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1613 unsigned int i
= bufmgr
->num_buckets
;
1615 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1617 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1618 bufmgr
->cache_bucket
[i
].size
= size
;
1619 bufmgr
->num_buckets
++;
1621 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1622 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1623 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1627 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1629 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1631 /* OK, so power of two buckets was too wasteful of memory.
1632 * Give 3 other sizes between each power of two, to hopefully
1633 * cover things accurately enough. (The alternative is
1634 * probably to just go for exact matching of sizes, and assume
1635 * that for things like composited window resize the tiled
1636 * width/height alignment and rounding of sizes to pages will
1637 * get us useful cache hit rates anyway)
1639 add_bucket(bufmgr
, PAGE_SIZE
);
1640 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1641 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1643 /* Initialize the linked lists for BO reuse cache. */
1644 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1645 add_bucket(bufmgr
, size
);
1647 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1648 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1649 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1654 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1656 struct drm_i915_gem_context_create create
= { };
1657 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1659 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1663 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1664 * back to the default logical HW state and attempt to continue on to
1665 * our next submitted batchbuffer. However, our render batches assume
1666 * the previous GPU state is preserved, and only emit commands needed
1667 * to incrementally change that state. In particular, we inherit the
1668 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1669 * With default base addresses, our next batches will almost certainly
1670 * cause more GPU hangs, leading to repeated hangs until we're banned
1671 * or the machine is dead.
1673 * Here we tell the kernel not to attempt to recover our context but
1674 * immediately (on the next batchbuffer submission) report that the
1675 * context is lost, and we will do the recovery ourselves. Ideally,
1676 * we'll have two lost batches instead of a continual stream of hangs.
1678 struct drm_i915_gem_context_param p
= {
1679 .ctx_id
= create
.ctx_id
,
1680 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1683 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1685 return create
.ctx_id
;
1689 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1691 struct drm_i915_gem_context_param p
= {
1693 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1695 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1696 return p
.value
; /* on error, return 0 i.e. default priority */
1700 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1704 struct drm_i915_gem_context_param p
= {
1706 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1712 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1719 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1721 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1724 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1725 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1732 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1734 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1737 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1738 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1744 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1746 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1747 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1749 *result
= reg_read
.val
;
1754 iris_gtt_size(int fd
)
1756 /* We use the default (already allocated) context to determine
1757 * the default configuration of the virtual address space.
1759 struct drm_i915_gem_context_param p
= {
1760 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1762 if (!gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1768 static struct gen_buffer
*
1769 gen_aux_map_buffer_alloc(void *driver_ctx
, uint32_t size
)
1771 struct gen_buffer
*buf
= malloc(sizeof(struct gen_buffer
));
1775 struct iris_bufmgr
*bufmgr
= (struct iris_bufmgr
*)driver_ctx
;
1777 struct iris_bo
*bo
=
1778 iris_bo_alloc_tiled(bufmgr
, "aux-map", size
, 64 * 1024,
1779 IRIS_MEMZONE_OTHER
, I915_TILING_NONE
, 0, 0);
1781 buf
->driver_bo
= bo
;
1782 buf
->gpu
= bo
->gtt_offset
;
1783 buf
->gpu_end
= buf
->gpu
+ bo
->size
;
1784 buf
->map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
1789 gen_aux_map_buffer_free(void *driver_ctx
, struct gen_buffer
*buffer
)
1791 iris_bo_unreference((struct iris_bo
*)buffer
->driver_bo
);
1795 static struct gen_mapped_pinned_buffer_alloc aux_map_allocator
= {
1796 .alloc
= gen_aux_map_buffer_alloc
,
1797 .free
= gen_aux_map_buffer_free
,
1801 gem_param(int fd
, int name
)
1803 int v
= -1; /* No param uses (yet) the sign bit, reserve it for errors */
1805 struct drm_i915_getparam gp
= { .param
= name
, .value
= &v
};
1806 if (gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
))
1813 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1814 * and manage map buffer objections.
1816 * \param fd File descriptor of the opened DRM device.
1818 static struct iris_bufmgr
*
1819 iris_bufmgr_create(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1821 uint64_t gtt_size
= iris_gtt_size(fd
);
1822 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1825 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1829 /* Handles to buffer objects belong to the device fd and are not
1830 * reference counted by the kernel. If the same fd is used by
1831 * multiple parties (threads sharing the same screen bufmgr, or
1832 * even worse the same device fd passed to multiple libraries)
1833 * ownership of those handles is shared by those independent parties.
1835 * Don't do this! Ensure that each library/bufmgr has its own device
1836 * fd so that its namespace does not clash with another.
1838 bufmgr
->fd
= os_dupfd_cloexec(fd
);
1840 p_atomic_set(&bufmgr
->refcount
, 1);
1842 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1848 list_inithead(&bufmgr
->zombie_list
);
1850 bufmgr
->has_llc
= devinfo
->has_llc
;
1851 bufmgr
->has_tiling_uapi
= devinfo
->has_tiling_uapi
;
1852 bufmgr
->bo_reuse
= bo_reuse
;
1853 bufmgr
->has_mmap_offset
= gem_param(fd
, I915_PARAM_MMAP_GTT_VERSION
) >= 4;
1855 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1856 const uint64_t _4GB
= 1ull << 32;
1857 const uint64_t _2GB
= 1ul << 31;
1859 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1860 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1862 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1863 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1864 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1865 IRIS_MEMZONE_SURFACE_START
,
1866 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1867 /* TODO: Why does limiting to 2GB help some state items on gen12?
1868 * - CC Viewport Pointer
1869 * - Blend State Pointer
1870 * - Color Calc State Pointer
1872 const uint64_t dynamic_pool_size
=
1873 (devinfo
->gen
>= 12 ? _2GB
: _4GB_minus_1
) - IRIS_BORDER_COLOR_POOL_SIZE
;
1874 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1875 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1878 /* Leave the last 4GB out of the high vma range, so that no state
1879 * base address + size can overflow 48 bits.
1881 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1882 IRIS_MEMZONE_OTHER_START
,
1883 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1885 init_cache_buckets(bufmgr
);
1887 bufmgr
->name_table
=
1888 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1889 bufmgr
->handle_table
=
1890 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1892 if (devinfo
->has_aux_map
) {
1893 bufmgr
->aux_map_ctx
= gen_aux_map_init(bufmgr
, &aux_map_allocator
,
1895 assert(bufmgr
->aux_map_ctx
);
1901 static struct iris_bufmgr
*
1902 iris_bufmgr_ref(struct iris_bufmgr
*bufmgr
)
1904 p_atomic_inc(&bufmgr
->refcount
);
1909 iris_bufmgr_unref(struct iris_bufmgr
*bufmgr
)
1911 mtx_lock(&global_bufmgr_list_mutex
);
1912 if (p_atomic_dec_zero(&bufmgr
->refcount
)) {
1913 list_del(&bufmgr
->link
);
1914 iris_bufmgr_destroy(bufmgr
);
1916 mtx_unlock(&global_bufmgr_list_mutex
);
1920 * Gets an already existing GEM buffer manager or create a new one.
1922 * \param fd File descriptor of the opened DRM device.
1924 struct iris_bufmgr
*
1925 iris_bufmgr_get_for_fd(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1932 struct iris_bufmgr
*bufmgr
= NULL
;
1934 mtx_lock(&global_bufmgr_list_mutex
);
1935 list_for_each_entry(struct iris_bufmgr
, iter_bufmgr
, &global_bufmgr_list
, link
) {
1936 struct stat iter_st
;
1937 if (fstat(iter_bufmgr
->fd
, &iter_st
))
1940 if (st
.st_rdev
== iter_st
.st_rdev
) {
1941 assert(iter_bufmgr
->bo_reuse
== bo_reuse
);
1942 bufmgr
= iris_bufmgr_ref(iter_bufmgr
);
1947 bufmgr
= iris_bufmgr_create(devinfo
, fd
, bo_reuse
);
1948 list_addtail(&bufmgr
->link
, &global_bufmgr_list
);
1951 mtx_unlock(&global_bufmgr_list_mutex
);
1957 iris_bufmgr_get_fd(struct iris_bufmgr
*bufmgr
)
1963 iris_bufmgr_get_aux_map_context(struct iris_bufmgr
*bufmgr
)
1965 return bufmgr
->aux_map_ctx
;