2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
49 #include <sys/types.h>
55 #define ETIME ETIMEDOUT
57 #include "common/gen_clflush.h"
58 #include "common/gen_debug.h"
59 #include "common/gen_gem.h"
60 #include "dev/gen_device_info.h"
61 #include "main/macros.h"
62 #include "util/debug.h"
63 #include "util/macros.h"
64 #include "util/hash_table.h"
65 #include "util/list.h"
66 #include "util/u_dynarray.h"
68 #include "iris_bufmgr.h"
69 #include "iris_context.h"
72 #include "drm-uapi/i915_drm.h"
82 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
83 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
84 * leaked. All because it does not call VG(cli_free) from its
85 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
86 * and allocation, we mark it available for use upon mmapping and remove
89 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
90 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
92 #define PAGE_SIZE 4096
94 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
97 * Call ioctl, restarting if it is interupted
100 drm_ioctl(int fd
, unsigned long request
, void *arg
)
105 ret
= ioctl(fd
, request
, arg
);
106 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
111 atomic_add_unless(int *v
, int add
, int unless
)
114 c
= p_atomic_read(v
);
115 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
121 * Iris fixed-size bucketing VMA allocator.
123 * The BO cache maintains "cache buckets" for buffers of various sizes.
124 * All buffers in a given bucket are identically sized - when allocating,
125 * we always round up to the bucket size. This means that virtually all
126 * allocations are fixed-size; only buffers which are too large to fit in
127 * a bucket can be variably-sized.
129 * We create an allocator for each bucket. Each contains a free-list, where
130 * each node contains a <starting address, 64-bit bitmap> pair. Each bit
131 * represents a bucket-sized block of memory. (At the first level, each
132 * bit corresponds to a page. For the second bucket, bits correspond to
133 * two pages, and so on.) 1 means a block is free, and 0 means it's in-use.
134 * The lowest bit in the bitmap is for the first block.
136 * This makes allocations cheap - any bit of any node will do. We can pick
137 * the head of the list and use ffs() to find a free block. If there are
138 * none, we allocate 64 blocks from a larger allocator - either a bigger
139 * bucketing allocator, or a fallback top-level allocator for large objects.
141 struct vma_bucket_node
{
142 uint64_t start_address
;
146 struct bo_cache_bucket
{
147 /** List of cached BOs. */
148 struct list_head head
;
150 /** Size of this bucket, in bytes. */
153 /** List of vma_bucket_nodes. */
154 struct util_dynarray vma_list
[IRIS_MEMZONE_COUNT
];
162 /** Array of lists of cached gem objects of power-of-two sizes */
163 struct bo_cache_bucket cache_bucket
[14 * 4];
167 struct hash_table
*name_table
;
168 struct hash_table
*handle_table
;
170 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
176 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
179 static void bo_free(struct iris_bo
*bo
);
181 static uint64_t vma_alloc(struct iris_bufmgr
*bufmgr
,
182 enum iris_memory_zone memzone
,
183 uint64_t size
, uint64_t alignment
);
186 key_hash_uint(const void *key
)
188 return _mesa_hash_data(key
, 4);
192 key_uint_equal(const void *a
, const void *b
)
194 return *((unsigned *) a
) == *((unsigned *) b
);
197 static struct iris_bo
*
198 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
200 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
201 return entry
? (struct iris_bo
*) entry
->data
: NULL
;
205 * This function finds the correct bucket fit for the input size.
206 * The function works with O(1) complexity when the requested size
207 * was queried instead of iterating the size through all the buckets.
209 static struct bo_cache_bucket
*
210 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
212 /* Calculating the pages and rounding up to the page size. */
213 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
215 /* Row Bucket sizes clz((x-1) | 3) Row Column
216 * in pages stride size
217 * 0: 1 2 3 4 -> 30 30 30 30 4 1
218 * 1: 5 6 7 8 -> 29 29 29 29 4 1
219 * 2: 10 12 14 16 -> 28 28 28 28 8 2
220 * 3: 20 24 28 32 -> 27 27 27 27 16 4
222 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
223 const unsigned row_max_pages
= 4 << row
;
225 /* The '& ~2' is the special case for row 1. In row 1, max pages /
226 * 2 is 2, but the previous row maximum is zero (because there is
227 * no previous row). All row maximum sizes are power of 2, so that
228 * is the only case where that bit will be set.
230 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
231 int col_size_log2
= row
- 1;
232 col_size_log2
+= (col_size_log2
< 0);
234 const unsigned col
= (pages
- prev_row_max_pages
+
235 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
237 /* Calculating the index based on the row and column. */
238 const unsigned index
= (row
* 4) + (col
- 1);
240 return (index
< bufmgr
->num_buckets
) ?
241 &bufmgr
->cache_bucket
[index
] : NULL
;
244 static enum iris_memory_zone
245 memzone_for_address(uint64_t address
)
247 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
248 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
249 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
250 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
251 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
253 if (address
>= IRIS_MEMZONE_OTHER_START
)
254 return IRIS_MEMZONE_OTHER
;
256 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
257 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
259 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
260 return IRIS_MEMZONE_DYNAMIC
;
262 if (address
>= IRIS_MEMZONE_SURFACE_START
)
263 return IRIS_MEMZONE_SURFACE
;
265 if (address
>= IRIS_MEMZONE_BINDER_START
)
266 return IRIS_MEMZONE_BINDER
;
268 return IRIS_MEMZONE_SHADER
;
272 bucket_vma_alloc(struct iris_bufmgr
*bufmgr
,
273 struct bo_cache_bucket
*bucket
,
274 enum iris_memory_zone memzone
)
276 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
277 struct vma_bucket_node
*node
;
279 if (vma_list
->size
== 0) {
280 /* This bucket allocator is out of space - allocate a new block of
281 * memory for 64 blocks from a larger allocator (either a larger
282 * bucket or util_vma).
284 * We align the address to the node size (64 blocks) so that
285 * bucket_vma_free can easily compute the starting address of this
286 * block by rounding any address we return down to the node size.
288 * Set the first bit used, and return the start address.
290 const uint64_t node_size
= 64ull * bucket
->size
;
291 node
= util_dynarray_grow(vma_list
, sizeof(struct vma_bucket_node
));
296 uint64_t addr
= vma_alloc(bufmgr
, memzone
, node_size
, node_size
);
297 node
->start_address
= gen_48b_address(addr
);
298 node
->bitmap
= ~1ull;
299 return node
->start_address
;
302 /* Pick any bit from any node - they're all the right size and free. */
303 node
= util_dynarray_top_ptr(vma_list
, struct vma_bucket_node
);
304 int bit
= ffsll(node
->bitmap
) - 1;
305 assert(bit
>= 0 && bit
<= 63);
307 /* Reserve the memory by clearing the bit. */
308 assert((node
->bitmap
& (1ull << bit
)) != 0ull);
309 node
->bitmap
&= ~(1ull << bit
);
311 uint64_t addr
= node
->start_address
+ bit
* bucket
->size
;
313 /* If this node is now completely full, remove it from the free list. */
314 if (node
->bitmap
== 0ull) {
315 (void) util_dynarray_pop(vma_list
, struct vma_bucket_node
);
322 bucket_vma_free(struct bo_cache_bucket
*bucket
, uint64_t address
)
324 enum iris_memory_zone memzone
= memzone_for_address(address
);
325 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
326 const uint64_t node_bytes
= 64ull * bucket
->size
;
327 struct vma_bucket_node
*node
= NULL
;
329 /* bucket_vma_alloc allocates 64 blocks at a time, and aligns it to
330 * that 64 block size. So, we can round down to get the starting address.
332 uint64_t start
= (address
/ node_bytes
) * node_bytes
;
334 /* Dividing the offset from start by bucket size gives us the bit index. */
335 int bit
= (address
- start
) / bucket
->size
;
337 assert(start
+ bit
* bucket
->size
== address
);
339 util_dynarray_foreach(vma_list
, struct vma_bucket_node
, cur
) {
340 if (cur
->start_address
== start
) {
347 /* No node - the whole group of 64 blocks must have been in-use. */
348 node
= util_dynarray_grow(vma_list
, sizeof(struct vma_bucket_node
));
351 return; /* bogus, leaks some GPU VMA, but nothing we can do... */
353 node
->start_address
= start
;
357 /* Set the bit to return the memory. */
358 assert((node
->bitmap
& (1ull << bit
)) == 0ull);
359 node
->bitmap
|= 1ull << bit
;
361 /* The block might be entirely free now, and if so, we could return it
362 * to the larger allocator. But we may as well hang on to it, in case
363 * we get more allocations at this block size.
367 static struct bo_cache_bucket
*
368 get_bucket_allocator(struct iris_bufmgr
*bufmgr
,
369 enum iris_memory_zone memzone
,
372 /* Skip using the bucket allocator for very large sizes, as it allocates
373 * 64 of them and this can balloon rather quickly.
375 if (size
> 1024 * PAGE_SIZE
)
378 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
380 if (bucket
&& bucket
->size
== size
)
387 * Allocate a section of virtual memory for a buffer, assigning an address.
389 * This uses either the bucket allocator for the given size, or the large
390 * object allocator (util_vma).
393 vma_alloc(struct iris_bufmgr
*bufmgr
,
394 enum iris_memory_zone memzone
,
398 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
399 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
401 /* The binder handles its own allocations. Return non-zero here. */
402 if (memzone
== IRIS_MEMZONE_BINDER
)
403 return IRIS_MEMZONE_BINDER_START
;
405 struct bo_cache_bucket
*bucket
=
406 get_bucket_allocator(bufmgr
, memzone
, size
);
410 addr
= bucket_vma_alloc(bufmgr
, bucket
, memzone
);
412 addr
= util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
,
416 assert((addr
>> 48ull) == 0);
417 assert((addr
% alignment
) == 0);
419 return gen_canonical_address(addr
);
423 vma_free(struct iris_bufmgr
*bufmgr
,
427 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
430 /* Un-canonicalize the address. */
431 address
= gen_48b_address(address
);
436 enum iris_memory_zone memzone
= memzone_for_address(address
);
438 /* The binder handles its own allocations. */
439 if (memzone
== IRIS_MEMZONE_BINDER
)
442 struct bo_cache_bucket
*bucket
=
443 get_bucket_allocator(bufmgr
, memzone
, size
);
446 bucket_vma_free(bucket
, address
);
448 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
453 iris_bo_busy(struct iris_bo
*bo
)
455 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
456 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
458 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
460 bo
->idle
= !busy
.busy
;
467 iris_bo_madvise(struct iris_bo
*bo
, int state
)
469 struct drm_i915_gem_madvise madv
= {
470 .handle
= bo
->gem_handle
,
475 drm_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
477 return madv
.retained
;
480 /* drop the oldest entries that have been purged by the kernel */
482 iris_bo_cache_purge_bucket(struct iris_bufmgr
*bufmgr
,
483 struct bo_cache_bucket
*bucket
)
485 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
486 if (iris_bo_madvise(bo
, I915_MADV_DONTNEED
))
494 static struct iris_bo
*
497 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
499 bo
->hash
= _mesa_hash_pointer(bo
);
504 static struct iris_bo
*
505 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
508 enum iris_memory_zone memzone
,
510 uint32_t tiling_mode
,
514 unsigned int page_size
= getpagesize();
516 struct bo_cache_bucket
*bucket
;
517 bool alloc_from_cache
;
521 if (flags
& BO_ALLOC_ZEROED
)
524 if ((flags
& BO_ALLOC_COHERENT
) && !bufmgr
->has_llc
) {
525 bo_size
= MAX2(ALIGN(size
, page_size
), page_size
);
530 /* Round the allocated size up to a power of two number of pages. */
531 bucket
= bucket_for_size(bufmgr
, size
);
533 /* If we don't have caching at this size, don't actually round the
536 if (bucket
== NULL
) {
537 bo_size
= MAX2(ALIGN(size
, page_size
), page_size
);
539 bo_size
= bucket
->size
;
542 mtx_lock(&bufmgr
->lock
);
543 /* Get a buffer out of the cache if available */
545 alloc_from_cache
= false;
546 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
547 /* If the last BO in the cache is idle, then reuse it. Otherwise,
548 * allocate a fresh buffer to avoid stalling.
550 bo
= LIST_ENTRY(struct iris_bo
, bucket
->head
.next
, head
);
551 if (!iris_bo_busy(bo
)) {
552 alloc_from_cache
= true;
556 if (alloc_from_cache
) {
557 if (!iris_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
559 iris_bo_cache_purge_bucket(bufmgr
, bucket
);
563 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
569 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
574 memset(map
, 0, bo_size
);
579 if (alloc_from_cache
) {
580 /* If the cached BO isn't in the right memory zone, free the old
581 * memory and assign it a new address.
583 if (memzone
!= memzone_for_address(bo
->gtt_offset
)) {
584 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
585 bo
->gtt_offset
= 0ull;
596 struct drm_i915_gem_create create
= { .size
= bo_size
};
598 /* All new BOs we get from the kernel are zeroed, so we don't need to
599 * worry about that here.
601 ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
607 bo
->gem_handle
= create
.handle
;
611 bo
->tiling_mode
= I915_TILING_NONE
;
612 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
615 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
618 /* Calling set_domain() will allocate pages for the BO outside of the
619 * struct mutex lock in the kernel, which is more efficient than waiting
620 * to create them during the first execbuf that uses the BO.
622 struct drm_i915_gem_set_domain sd
= {
623 .handle
= bo
->gem_handle
,
624 .read_domains
= I915_GEM_DOMAIN_CPU
,
628 if (drm_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0)
633 p_atomic_set(&bo
->refcount
, 1);
634 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
635 bo
->cache_coherent
= bufmgr
->has_llc
;
637 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
639 /* By default, capture all driver-internal buffers like shader kernels,
640 * surface states, dynamic states, border colors, and so on.
642 if (memzone
< IRIS_MEMZONE_OTHER
)
643 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
645 if (bo
->gtt_offset
== 0ull) {
646 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, 1);
648 if (bo
->gtt_offset
== 0ull)
652 mtx_unlock(&bufmgr
->lock
);
654 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
655 struct drm_i915_gem_caching arg
= {
656 .handle
= bo
->gem_handle
,
659 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
660 bo
->cache_coherent
= true;
661 bo
->reusable
= false;
665 DBG("bo_create: buf %d (%s) %llub\n", bo
->gem_handle
, bo
->name
,
666 (unsigned long long) size
);
673 mtx_unlock(&bufmgr
->lock
);
678 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
681 enum iris_memory_zone memzone
)
683 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
684 0, I915_TILING_NONE
, 0);
688 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
689 uint64_t size
, enum iris_memory_zone memzone
,
690 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
692 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
693 flags
, tiling_mode
, pitch
);
697 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
698 void *ptr
, size_t size
,
699 enum iris_memory_zone memzone
)
707 struct drm_i915_gem_userptr arg
= {
708 .user_ptr
= (uintptr_t)ptr
,
711 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
713 bo
->gem_handle
= arg
.handle
;
715 /* Check the buffer for validity before we try and use it in a batch */
716 struct drm_i915_gem_set_domain sd
= {
717 .handle
= bo
->gem_handle
,
718 .read_domains
= I915_GEM_DOMAIN_CPU
,
720 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
728 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
729 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
730 if (bo
->gtt_offset
== 0ull)
733 p_atomic_set(&bo
->refcount
, 1);
735 bo
->cache_coherent
= true;
742 drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &bo
->gem_handle
);
749 * Returns a iris_bo wrapping the given buffer object handle.
751 * This can be used when one application needs to pass a buffer object
755 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
756 const char *name
, unsigned int handle
)
760 /* At the moment most applications only have a few named bo.
761 * For instance, in a DRI client only the render buffers passed
762 * between X and the client are named. And since X returns the
763 * alternating names for the front/back buffer a linear search
764 * provides a sufficiently fast match.
766 mtx_lock(&bufmgr
->lock
);
767 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
769 iris_bo_reference(bo
);
773 struct drm_gem_open open_arg
= { .name
= handle
};
774 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
776 DBG("Couldn't reference %s handle 0x%08x: %s\n",
777 name
, handle
, strerror(errno
));
781 /* Now see if someone has used a prime handle to get this
782 * object from the kernel before by looking through the list
783 * again for a matching gem_handle
785 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
787 iris_bo_reference(bo
);
795 p_atomic_set(&bo
->refcount
, 1);
797 bo
->size
= open_arg
.size
;
800 bo
->gem_handle
= open_arg
.handle
;
802 bo
->global_name
= handle
;
803 bo
->reusable
= false;
805 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
806 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
808 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
809 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
811 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
812 ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
816 bo
->tiling_mode
= get_tiling
.tiling_mode
;
817 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
818 /* XXX stride is unknown */
819 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
822 mtx_unlock(&bufmgr
->lock
);
827 mtx_unlock(&bufmgr
->lock
);
832 bo_free(struct iris_bo
*bo
)
834 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
836 if (bo
->map_cpu
&& !bo
->userptr
) {
837 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
838 munmap(bo
->map_cpu
, bo
->size
);
841 VG_NOACCESS(bo
->map_wc
, bo
->size
);
842 munmap(bo
->map_wc
, bo
->size
);
845 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
846 munmap(bo
->map_gtt
, bo
->size
);
850 struct hash_entry
*entry
;
852 if (bo
->global_name
) {
853 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
854 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
857 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
858 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
861 /* Close this object */
862 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
863 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
865 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
866 bo
->gem_handle
, bo
->name
, strerror(errno
));
869 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
874 /** Frees all cached buffers significantly older than @time. */
876 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
880 if (bufmgr
->time
== time
)
883 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
884 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
886 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
887 if (time
- bo
->free_time
<= 1)
900 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
902 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
903 struct bo_cache_bucket
*bucket
;
905 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
909 bucket
= bucket_for_size(bufmgr
, bo
->size
);
910 /* Put the buffer into our internal cache for reuse if we can. */
911 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
912 bo
->free_time
= time
;
915 list_addtail(&bo
->head
, &bucket
->head
);
922 iris_bo_unreference(struct iris_bo
*bo
)
927 assert(p_atomic_read(&bo
->refcount
) > 0);
929 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
930 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
931 struct timespec time
;
933 clock_gettime(CLOCK_MONOTONIC
, &time
);
935 mtx_lock(&bufmgr
->lock
);
937 if (p_atomic_dec_zero(&bo
->refcount
)) {
938 bo_unreference_final(bo
, time
.tv_sec
);
939 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
942 mtx_unlock(&bufmgr
->lock
);
947 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
951 bool busy
= dbg
&& !bo
->idle
;
952 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
954 iris_bo_wait_rendering(bo
);
956 if (unlikely(busy
)) {
957 elapsed
+= get_time();
958 if (elapsed
> 1e-5) /* 0.01ms */ {
959 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
960 action
, bo
->name
, elapsed
* 1000);
966 print_flags(unsigned flags
)
968 if (flags
& MAP_READ
)
970 if (flags
& MAP_WRITE
)
972 if (flags
& MAP_ASYNC
)
974 if (flags
& MAP_PERSISTENT
)
976 if (flags
& MAP_COHERENT
)
984 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
985 struct iris_bo
*bo
, unsigned flags
)
987 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
989 /* We disallow CPU maps for writing to non-coherent buffers, as the
990 * CPU map can become invalidated when a batch is flushed out, which
991 * can happen at unpredictable times. You should use WC maps instead.
993 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
996 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
998 struct drm_i915_gem_mmap mmap_arg
= {
999 .handle
= bo
->gem_handle
,
1002 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
1004 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1005 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1008 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
1009 VG_DEFINED(map
, bo
->size
);
1011 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
1012 VG_NOACCESS(map
, bo
->size
);
1013 munmap(map
, bo
->size
);
1016 assert(bo
->map_cpu
);
1018 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
1022 if (!(flags
& MAP_ASYNC
)) {
1023 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
1026 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
1027 /* If we're reusing an existing CPU mapping, the CPU caches may
1028 * contain stale data from the last time we read from that mapping.
1029 * (With the BO cache, it might even be data from a previous buffer!)
1030 * Even if it's a brand new mapping, the kernel may have zeroed the
1031 * buffer via CPU writes.
1033 * We need to invalidate those cachelines so that we see the latest
1034 * contents, and so long as we only read from the CPU mmap we do not
1035 * need to write those cachelines back afterwards.
1037 * On LLC, the emprical evidence suggests that writes from the GPU
1038 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
1039 * cachelines. (Other reads, such as the display engine, bypass the
1040 * LLC entirely requiring us to keep dirty pixels for the scanout
1041 * out of any cache.)
1043 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
1050 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
1051 struct iris_bo
*bo
, unsigned flags
)
1053 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1056 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1058 struct drm_i915_gem_mmap mmap_arg
= {
1059 .handle
= bo
->gem_handle
,
1061 .flags
= I915_MMAP_WC
,
1063 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
1065 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1066 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1070 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
1071 VG_DEFINED(map
, bo
->size
);
1073 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
1074 VG_NOACCESS(map
, bo
->size
);
1075 munmap(map
, bo
->size
);
1080 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1083 if (!(flags
& MAP_ASYNC
)) {
1084 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
1091 * Perform an uncached mapping via the GTT.
1093 * Write access through the GTT is not quite fully coherent. On low power
1094 * systems especially, like modern Atoms, we can observe reads from RAM before
1095 * the write via GTT has landed. A write memory barrier that flushes the Write
1096 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1097 * read after the write as the GTT write suffers a small delay through the GTT
1098 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1099 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1100 * flushes prior to execbuf submission. However, if we are not informing the
1101 * kernel about our GTT writes, it will not flush before earlier access, such
1102 * as when using the cmdparser. Similarly, we need to be careful if we should
1103 * ever issue a CPU read immediately following a GTT write.
1105 * Telling the kernel about write access also has one more important
1106 * side-effect. Upon receiving notification about the write, it cancels any
1107 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1108 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1109 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1110 * tracking is handled on the buffer exchange instead.
1113 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1114 struct iris_bo
*bo
, unsigned flags
)
1116 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1118 /* Get a mapping of the buffer if we haven't before. */
1119 if (bo
->map_gtt
== NULL
) {
1120 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1122 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1124 /* Get the fake offset back... */
1125 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1127 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1128 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1133 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1134 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1135 if (map
== MAP_FAILED
) {
1136 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1137 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1141 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1142 * already intercept this mmap call. However, for consistency between
1143 * all the mmap paths, we mark the pointer as defined now and mark it
1144 * as inaccessible afterwards.
1146 VG_DEFINED(map
, bo
->size
);
1148 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1149 VG_NOACCESS(map
, bo
->size
);
1150 munmap(map
, bo
->size
);
1153 assert(bo
->map_gtt
);
1155 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1158 if (!(flags
& MAP_ASYNC
)) {
1159 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1166 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1168 if (bo
->cache_coherent
)
1171 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1172 * an LLC platform reads always are coherent (as they are performed via the
1173 * central system agent). It is just the writes that we need to take special
1174 * care to ensure that land in main memory and not stick in the CPU cache.
1176 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1179 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1180 * across batch flushes where the kernel will change cache domains of the
1181 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1183 * Similarly, ASYNC typically means that the buffer will be accessed via
1184 * both the CPU and the GPU simultaneously. Batches may be executed that
1185 * use the BO even while it is mapped. While OpenGL technically disallows
1186 * most drawing while non-persistent mappings are active, we may still use
1187 * the GPU for blits or other operations, causing batches to happen at
1188 * inconvenient times.
1190 * If RAW is set, we expect the caller to be able to handle a WC buffer
1191 * more efficiently than the involuntary clflushes.
1193 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1196 return !(flags
& MAP_WRITE
);
1200 iris_bo_map(struct pipe_debug_callback
*dbg
,
1201 struct iris_bo
*bo
, unsigned flags
)
1203 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1204 return iris_bo_map_gtt(dbg
, bo
, flags
);
1208 if (can_map_cpu(bo
, flags
))
1209 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1211 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1213 /* Allow the attempt to fail by falling back to the GTT where necessary.
1215 * Not every buffer can be mmaped directly using the CPU (or WC), for
1216 * example buffers that wrap stolen memory or are imported from other
1217 * devices. For those, we have little choice but to use a GTT mmapping.
1218 * However, if we use a slow GTT mmapping for reads where we expected fast
1219 * access, that order of magnitude difference in throughput will be clearly
1220 * expressed by angry users.
1222 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1224 if (!map
&& !(flags
& MAP_RAW
)) {
1225 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1227 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1233 /** Waits for all GPU rendering with the object to have completed. */
1235 iris_bo_wait_rendering(struct iris_bo
*bo
)
1237 /* We require a kernel recent enough for WAIT_IOCTL support.
1238 * See intel_init_bufmgr()
1240 iris_bo_wait(bo
, -1);
1244 * Waits on a BO for the given amount of time.
1246 * @bo: buffer object to wait for
1247 * @timeout_ns: amount of time to wait in nanoseconds.
1248 * If value is less than 0, an infinite wait will occur.
1250 * Returns 0 if the wait was successful ie. the last batch referencing the
1251 * object has completed within the allotted time. Otherwise some negative return
1252 * value describes the error. Of particular interest is -ETIME when the wait has
1253 * failed to yield the desired result.
1255 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1256 * the operation to give up after a certain amount of time. Another subtle
1257 * difference is the internal locking semantics are different (this variant does
1258 * not hold the lock for the duration of the wait). This makes the wait subject
1259 * to a larger userspace race window.
1261 * The implementation shall wait until the object is no longer actively
1262 * referenced within a batch buffer at the time of the call. The wait will
1263 * not guarantee that the buffer is re-issued via another thread, or an flinked
1264 * handle. Userspace must make sure this race does not occur if such precision
1267 * Note that some kernels have broken the inifite wait for negative values
1268 * promise, upgrade to latest stable kernels if this is the case.
1271 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1273 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1275 /* If we know it's idle, don't bother with the kernel round trip */
1276 if (bo
->idle
&& !bo
->external
)
1279 struct drm_i915_gem_wait wait
= {
1280 .bo_handle
= bo
->gem_handle
,
1281 .timeout_ns
= timeout_ns
,
1283 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1293 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1295 mtx_destroy(&bufmgr
->lock
);
1297 /* Free any cached buffer objects we were going to reuse */
1298 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1299 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1301 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1302 list_del(&bo
->head
);
1307 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++)
1308 util_dynarray_fini(&bucket
->vma_list
[z
]);
1311 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1312 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1314 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1315 if (z
!= IRIS_MEMZONE_BINDER
)
1316 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1323 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1326 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1327 struct drm_i915_gem_set_tiling set_tiling
;
1330 if (bo
->global_name
== 0 &&
1331 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1334 memset(&set_tiling
, 0, sizeof(set_tiling
));
1336 /* set_tiling is slightly broken and overwrites the
1337 * input on the error path, so we have to open code
1340 set_tiling
.handle
= bo
->gem_handle
;
1341 set_tiling
.tiling_mode
= tiling_mode
;
1342 set_tiling
.stride
= stride
;
1344 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1345 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1349 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1350 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1351 bo
->stride
= set_tiling
.stride
;
1356 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1357 uint32_t *swizzle_mode
)
1359 *tiling_mode
= bo
->tiling_mode
;
1360 *swizzle_mode
= bo
->swizzle_mode
;
1365 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
)
1370 mtx_lock(&bufmgr
->lock
);
1371 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1373 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1375 mtx_unlock(&bufmgr
->lock
);
1380 * See if the kernel has already returned this buffer to us. Just as
1381 * for named buffers, we must not create two bo's pointing at the same
1384 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1386 iris_bo_reference(bo
);
1394 p_atomic_set(&bo
->refcount
, 1);
1396 /* Determine size of bo. The fd-to-handle ioctl really should
1397 * return the size, but it doesn't. If we have kernel 3.12 or
1398 * later, we can lseek on the prime fd to get the size. Older
1399 * kernels will just fail, in which case we fall back to the
1400 * provided (estimated or guess size). */
1401 ret
= lseek(prime_fd
, 0, SEEK_END
);
1405 bo
->bufmgr
= bufmgr
;
1407 bo
->gem_handle
= handle
;
1408 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1411 bo
->reusable
= false;
1412 bo
->external
= true;
1413 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1414 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1416 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1417 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1420 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1421 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1422 /* XXX stride is unknown */
1425 mtx_unlock(&bufmgr
->lock
);
1430 mtx_unlock(&bufmgr
->lock
);
1435 iris_bo_make_external_locked(struct iris_bo
*bo
)
1437 if (!bo
->external
) {
1438 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1439 bo
->external
= true;
1444 iris_bo_make_external(struct iris_bo
*bo
)
1446 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1451 mtx_lock(&bufmgr
->lock
);
1452 iris_bo_make_external_locked(bo
);
1453 mtx_unlock(&bufmgr
->lock
);
1457 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1459 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1461 iris_bo_make_external(bo
);
1463 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1464 DRM_CLOEXEC
, prime_fd
) != 0)
1467 bo
->reusable
= false;
1473 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1475 iris_bo_make_external(bo
);
1477 return bo
->gem_handle
;
1481 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1483 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1485 if (!bo
->global_name
) {
1486 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1488 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1491 mtx_lock(&bufmgr
->lock
);
1492 if (!bo
->global_name
) {
1493 iris_bo_make_external_locked(bo
);
1494 bo
->global_name
= flink
.name
;
1495 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1497 mtx_unlock(&bufmgr
->lock
);
1499 bo
->reusable
= false;
1502 *name
= bo
->global_name
;
1507 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1509 unsigned int i
= bufmgr
->num_buckets
;
1511 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1513 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1514 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++)
1515 util_dynarray_init(&bufmgr
->cache_bucket
[i
].vma_list
[z
], NULL
);
1516 bufmgr
->cache_bucket
[i
].size
= size
;
1517 bufmgr
->num_buckets
++;
1519 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1520 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1521 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1525 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1527 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1529 /* OK, so power of two buckets was too wasteful of memory.
1530 * Give 3 other sizes between each power of two, to hopefully
1531 * cover things accurately enough. (The alternative is
1532 * probably to just go for exact matching of sizes, and assume
1533 * that for things like composited window resize the tiled
1534 * width/height alignment and rounding of sizes to pages will
1535 * get us useful cache hit rates anyway)
1537 add_bucket(bufmgr
, PAGE_SIZE
);
1538 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1539 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1541 /* Initialize the linked lists for BO reuse cache. */
1542 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1543 add_bucket(bufmgr
, size
);
1545 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1546 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1547 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1552 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1554 struct drm_i915_gem_context_create create
= { };
1555 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1557 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1561 return create
.ctx_id
;
1565 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1569 struct drm_i915_gem_context_param p
= {
1571 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1577 if (drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1584 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1586 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1589 drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1590 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1596 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1598 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1599 int ret
= drm_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1601 *result
= reg_read
.val
;
1606 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1607 * and manage map buffer objections.
1609 * \param fd File descriptor of the opened DRM device.
1611 struct iris_bufmgr
*
1612 iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
)
1614 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1618 /* Handles to buffer objects belong to the device fd and are not
1619 * reference counted by the kernel. If the same fd is used by
1620 * multiple parties (threads sharing the same screen bufmgr, or
1621 * even worse the same device fd passed to multiple libraries)
1622 * ownership of those handles is shared by those independent parties.
1624 * Don't do this! Ensure that each library/bufmgr has its own device
1625 * fd so that its namespace does not clash with another.
1629 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1634 bufmgr
->has_llc
= devinfo
->has_llc
;
1636 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1637 const uint64_t _4GB
= 1ull << 32;
1639 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1640 PAGE_SIZE
, _4GB
- PAGE_SIZE
);
1641 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1642 IRIS_MEMZONE_SURFACE_START
,
1643 _4GB
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1644 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1645 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1646 _4GB
- IRIS_BORDER_COLOR_POOL_SIZE
);
1647 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1648 IRIS_MEMZONE_OTHER_START
,
1649 (1ull << 48) - IRIS_MEMZONE_OTHER_START
);
1652 bufmgr
->bo_reuse
= env_var_as_boolean("bo_reuse", true);
1654 init_cache_buckets(bufmgr
);
1656 bufmgr
->name_table
=
1657 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1658 bufmgr
->handle_table
=
1659 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);