2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
35 #include <util/u_atomic.h>
42 #include <sys/ioctl.h>
45 #include <sys/types.h>
51 #include "common/gen_aux_map.h"
52 #include "common/gen_clflush.h"
53 #include "dev/gen_debug.h"
54 #include "common/gen_gem.h"
55 #include "dev/gen_device_info.h"
56 #include "main/macros.h"
57 #include "os/os_mman.h"
58 #include "util/debug.h"
59 #include "util/macros.h"
60 #include "util/hash_table.h"
61 #include "util/list.h"
62 #include "util/os_file.h"
63 #include "util/u_dynarray.h"
65 #include "iris_bufmgr.h"
66 #include "iris_context.h"
69 #include "drm-uapi/i915_drm.h"
79 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
80 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
81 * leaked. All because it does not call VG(cli_free) from its
82 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
83 * and allocation, we mark it available for use upon mmapping and remove
86 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
87 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
89 #define PAGE_SIZE 4096
91 #define WARN_ONCE(cond, fmt...) do { \
92 if (unlikely(cond)) { \
93 static bool _warned = false; \
95 fprintf(stderr, "WARNING: "); \
96 fprintf(stderr, fmt); \
102 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
105 atomic_add_unless(int *v
, int add
, int unless
)
108 c
= p_atomic_read(v
);
109 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
115 memzone_name(enum iris_memory_zone memzone
)
117 const char *names
[] = {
118 [IRIS_MEMZONE_SHADER
] = "shader",
119 [IRIS_MEMZONE_BINDER
] = "binder",
120 [IRIS_MEMZONE_SURFACE
] = "surface",
121 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
122 [IRIS_MEMZONE_OTHER
] = "other",
123 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
125 assert(memzone
< ARRAY_SIZE(names
));
126 return names
[memzone
];
129 struct bo_cache_bucket
{
130 /** List of cached BOs. */
131 struct list_head head
;
133 /** Size of this bucket, in bytes. */
138 /** File descriptor associated with a handle export. */
141 /** GEM handle in drm_fd */
144 struct list_head link
;
149 * List into the list of bufmgr.
151 struct list_head link
;
159 /** Array of lists of cached gem objects of power-of-two sizes */
160 struct bo_cache_bucket cache_bucket
[14 * 4];
164 struct hash_table
*name_table
;
165 struct hash_table
*handle_table
;
168 * List of BOs which we've effectively freed, but are hanging on to
169 * until they're idle before closing and returning the VMA.
171 struct list_head zombie_list
;
173 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
176 bool has_mmap_offset
:1;
179 struct gen_aux_map_context
*aux_map_ctx
;
182 static mtx_t global_bufmgr_list_mutex
= _MTX_INITIALIZER_NP
;
183 static struct list_head global_bufmgr_list
= {
184 .next
= &global_bufmgr_list
,
185 .prev
= &global_bufmgr_list
,
188 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
191 static void bo_free(struct iris_bo
*bo
);
193 static struct iris_bo
*
194 find_and_ref_external_bo(struct hash_table
*ht
, unsigned int key
)
196 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
197 struct iris_bo
*bo
= entry
? entry
->data
: NULL
;
200 assert(bo
->external
);
201 assert(!bo
->reusable
);
203 /* Being non-reusable, the BO cannot be in the cache lists, but it
204 * may be in the zombie list if it had reached zero references, but
205 * we hadn't yet closed it...and then reimported the same BO. If it
206 * is, then remove it since it's now been resurrected.
208 if (bo
->head
.prev
|| bo
->head
.next
)
211 iris_bo_reference(bo
);
218 * This function finds the correct bucket fit for the input size.
219 * The function works with O(1) complexity when the requested size
220 * was queried instead of iterating the size through all the buckets.
222 static struct bo_cache_bucket
*
223 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
225 /* Calculating the pages and rounding up to the page size. */
226 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
228 /* Row Bucket sizes clz((x-1) | 3) Row Column
229 * in pages stride size
230 * 0: 1 2 3 4 -> 30 30 30 30 4 1
231 * 1: 5 6 7 8 -> 29 29 29 29 4 1
232 * 2: 10 12 14 16 -> 28 28 28 28 8 2
233 * 3: 20 24 28 32 -> 27 27 27 27 16 4
235 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
236 const unsigned row_max_pages
= 4 << row
;
238 /* The '& ~2' is the special case for row 1. In row 1, max pages /
239 * 2 is 2, but the previous row maximum is zero (because there is
240 * no previous row). All row maximum sizes are power of 2, so that
241 * is the only case where that bit will be set.
243 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
244 int col_size_log2
= row
- 1;
245 col_size_log2
+= (col_size_log2
< 0);
247 const unsigned col
= (pages
- prev_row_max_pages
+
248 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
250 /* Calculating the index based on the row and column. */
251 const unsigned index
= (row
* 4) + (col
- 1);
253 return (index
< bufmgr
->num_buckets
) ?
254 &bufmgr
->cache_bucket
[index
] : NULL
;
257 enum iris_memory_zone
258 iris_memzone_for_address(uint64_t address
)
260 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
261 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
262 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
263 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
264 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
266 if (address
>= IRIS_MEMZONE_OTHER_START
)
267 return IRIS_MEMZONE_OTHER
;
269 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
270 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
272 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
273 return IRIS_MEMZONE_DYNAMIC
;
275 if (address
>= IRIS_MEMZONE_SURFACE_START
)
276 return IRIS_MEMZONE_SURFACE
;
278 if (address
>= IRIS_MEMZONE_BINDER_START
)
279 return IRIS_MEMZONE_BINDER
;
281 return IRIS_MEMZONE_SHADER
;
285 * Allocate a section of virtual memory for a buffer, assigning an address.
287 * This uses either the bucket allocator for the given size, or the large
288 * object allocator (util_vma).
291 vma_alloc(struct iris_bufmgr
*bufmgr
,
292 enum iris_memory_zone memzone
,
296 /* Force alignment to be some number of pages */
297 alignment
= ALIGN(alignment
, PAGE_SIZE
);
299 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
300 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
302 /* The binder handles its own allocations. Return non-zero here. */
303 if (memzone
== IRIS_MEMZONE_BINDER
)
304 return IRIS_MEMZONE_BINDER_START
;
307 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
309 assert((addr
>> 48ull) == 0);
310 assert((addr
% alignment
) == 0);
312 return gen_canonical_address(addr
);
316 vma_free(struct iris_bufmgr
*bufmgr
,
320 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
323 /* Un-canonicalize the address. */
324 address
= gen_48b_address(address
);
329 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
331 /* The binder handles its own allocations. */
332 if (memzone
== IRIS_MEMZONE_BINDER
)
335 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
339 iris_bo_busy(struct iris_bo
*bo
)
341 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
342 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
344 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
346 bo
->idle
= !busy
.busy
;
353 iris_bo_madvise(struct iris_bo
*bo
, int state
)
355 struct drm_i915_gem_madvise madv
= {
356 .handle
= bo
->gem_handle
,
361 gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
363 return madv
.retained
;
366 static struct iris_bo
*
369 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
373 list_inithead(&bo
->exports
);
375 bo
->hash
= _mesa_hash_pointer(bo
);
380 static struct iris_bo
*
381 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
382 struct bo_cache_bucket
*bucket
,
384 enum iris_memory_zone memzone
,
391 struct iris_bo
*bo
= NULL
;
393 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
394 /* Try a little harder to find one that's already in the right memzone */
395 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
398 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
399 * either falling back to a non-matching memzone, or if that fails,
400 * allocating a fresh buffer.
402 if (iris_bo_busy(cur
))
405 list_del(&cur
->head
);
407 /* Tell the kernel we need this BO. If it still exists, we're done! */
408 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
413 /* This BO was purged, throw it out and keep looking. */
420 if (bo
->aux_map_address
) {
421 /* This buffer was associated with an aux-buffer range. We make sure
422 * that buffers are not reused from the cache while the buffer is (busy)
423 * being used by an executing batch. Since we are here, the buffer is no
424 * longer being used by a batch and the buffer was deleted (in order to
425 * end up in the cache). Therefore its old aux-buffer range can be
426 * removed from the aux-map.
428 if (bo
->bufmgr
->aux_map_ctx
)
429 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
431 bo
->aux_map_address
= 0;
434 /* If the cached BO isn't in the right memory zone, or the alignment
435 * isn't sufficient, free the old memory and assign it a new address.
437 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
) ||
438 bo
->gtt_offset
% alignment
!= 0) {
439 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
440 bo
->gtt_offset
= 0ull;
443 /* Zero the contents if necessary. If this fails, fall back to
444 * allocating a fresh BO, which will always be zeroed by the kernel.
446 if (flags
& BO_ALLOC_ZEROED
) {
447 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
449 memset(map
, 0, bo
->size
);
459 static struct iris_bo
*
460 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
462 struct iris_bo
*bo
= bo_calloc();
466 struct drm_i915_gem_create create
= { .size
= bo_size
};
468 /* All new BOs we get from the kernel are zeroed, so we don't need to
469 * worry about that here.
471 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
476 bo
->gem_handle
= create
.handle
;
480 bo
->tiling_mode
= I915_TILING_NONE
;
483 /* Calling set_domain() will allocate pages for the BO outside of the
484 * struct mutex lock in the kernel, which is more efficient than waiting
485 * to create them during the first execbuf that uses the BO.
487 struct drm_i915_gem_set_domain sd
= {
488 .handle
= bo
->gem_handle
,
489 .read_domains
= I915_GEM_DOMAIN_CPU
,
493 if (gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
501 static struct iris_bo
*
502 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
506 enum iris_memory_zone memzone
,
508 uint32_t tiling_mode
,
512 unsigned int page_size
= getpagesize();
513 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
515 /* Round the size up to the bucket size, or if we don't have caching
516 * at this size, a multiple of the page size.
519 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
521 mtx_lock(&bufmgr
->lock
);
523 /* Get a buffer out of the cache if available. First, we try to find
524 * one with a matching memory zone so we can avoid reallocating VMA.
526 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
, true);
528 /* If that fails, we try for any cached BO, without matching memzone. */
530 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
,
534 mtx_unlock(&bufmgr
->lock
);
537 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
542 if (bo
->gtt_offset
== 0ull) {
543 mtx_lock(&bufmgr
->lock
);
544 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, alignment
);
545 mtx_unlock(&bufmgr
->lock
);
547 if (bo
->gtt_offset
== 0ull)
551 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
555 p_atomic_set(&bo
->refcount
, 1);
556 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
557 bo
->cache_coherent
= bufmgr
->has_llc
;
559 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
561 /* By default, capture all driver-internal buffers like shader kernels,
562 * surface states, dynamic states, border colors, and so on.
564 if (memzone
< IRIS_MEMZONE_OTHER
)
565 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
567 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
568 struct drm_i915_gem_caching arg
= {
569 .handle
= bo
->gem_handle
,
572 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
573 bo
->cache_coherent
= true;
574 bo
->reusable
= false;
578 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
579 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
589 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
592 enum iris_memory_zone memzone
)
594 return bo_alloc_internal(bufmgr
, name
, size
, 1, memzone
,
595 0, I915_TILING_NONE
, 0);
599 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
600 uint64_t size
, uint32_t alignment
,
601 enum iris_memory_zone memzone
,
602 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
604 return bo_alloc_internal(bufmgr
, name
, size
, alignment
, memzone
,
605 flags
, tiling_mode
, pitch
);
609 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
610 void *ptr
, size_t size
,
611 enum iris_memory_zone memzone
)
613 struct drm_gem_close close
= { 0, };
620 struct drm_i915_gem_userptr arg
= {
621 .user_ptr
= (uintptr_t)ptr
,
624 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
626 bo
->gem_handle
= arg
.handle
;
628 /* Check the buffer for validity before we try and use it in a batch */
629 struct drm_i915_gem_set_domain sd
= {
630 .handle
= bo
->gem_handle
,
631 .read_domains
= I915_GEM_DOMAIN_CPU
,
633 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
641 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
643 mtx_lock(&bufmgr
->lock
);
644 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
645 mtx_unlock(&bufmgr
->lock
);
647 if (bo
->gtt_offset
== 0ull)
650 p_atomic_set(&bo
->refcount
, 1);
652 bo
->cache_coherent
= true;
659 close
.handle
= bo
->gem_handle
;
660 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
667 * Returns a iris_bo wrapping the given buffer object handle.
669 * This can be used when one application needs to pass a buffer object
673 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
674 const char *name
, unsigned int handle
)
678 /* At the moment most applications only have a few named bo.
679 * For instance, in a DRI client only the render buffers passed
680 * between X and the client are named. And since X returns the
681 * alternating names for the front/back buffer a linear search
682 * provides a sufficiently fast match.
684 mtx_lock(&bufmgr
->lock
);
685 bo
= find_and_ref_external_bo(bufmgr
->name_table
, handle
);
689 struct drm_gem_open open_arg
= { .name
= handle
};
690 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
692 DBG("Couldn't reference %s handle 0x%08x: %s\n",
693 name
, handle
, strerror(errno
));
697 /* Now see if someone has used a prime handle to get this
698 * object from the kernel before by looking through the list
699 * again for a matching gem_handle
701 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, open_arg
.handle
);
709 p_atomic_set(&bo
->refcount
, 1);
711 bo
->size
= open_arg
.size
;
713 bo
->gem_handle
= open_arg
.handle
;
715 bo
->global_name
= handle
;
716 bo
->reusable
= false;
718 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
719 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
721 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
722 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
724 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
725 ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
729 bo
->tiling_mode
= get_tiling
.tiling_mode
;
731 /* XXX stride is unknown */
732 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
735 mtx_unlock(&bufmgr
->lock
);
740 mtx_unlock(&bufmgr
->lock
);
745 bo_close(struct iris_bo
*bo
)
747 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
750 struct hash_entry
*entry
;
752 if (bo
->global_name
) {
753 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
754 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
757 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
758 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
760 list_for_each_entry_safe(struct bo_export
, export
, &bo
->exports
, link
) {
761 struct drm_gem_close close
= { .handle
= export
->gem_handle
};
762 gen_ioctl(export
->drm_fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
764 list_del(&export
->link
);
768 assert(list_is_empty(&bo
->exports
));
771 /* Close this object */
772 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
773 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
775 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
776 bo
->gem_handle
, bo
->name
, strerror(errno
));
779 if (bo
->aux_map_address
&& bo
->bufmgr
->aux_map_ctx
) {
780 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
784 /* Return the VMA for reuse */
785 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
791 bo_free(struct iris_bo
*bo
)
793 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
795 if (bo
->map_cpu
&& !bo
->userptr
) {
796 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
797 os_munmap(bo
->map_cpu
, bo
->size
);
800 VG_NOACCESS(bo
->map_wc
, bo
->size
);
801 os_munmap(bo
->map_wc
, bo
->size
);
804 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
805 os_munmap(bo
->map_gtt
, bo
->size
);
811 /* Defer closing the GEM BO and returning the VMA for reuse until the
812 * BO is idle. Just move it to the dead list for now.
814 list_addtail(&bo
->head
, &bufmgr
->zombie_list
);
818 /** Frees all cached buffers significantly older than @time. */
820 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
824 if (bufmgr
->time
== time
)
827 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
828 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
830 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
831 if (time
- bo
->free_time
<= 1)
840 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
841 /* Stop once we reach a busy BO - all others past this point were
842 * freed more recently so are likely also busy.
844 if (!bo
->idle
&& iris_bo_busy(bo
))
855 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
857 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
858 struct bo_cache_bucket
*bucket
;
860 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
864 bucket
= bucket_for_size(bufmgr
, bo
->size
);
865 /* Put the buffer into our internal cache for reuse if we can. */
866 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
867 bo
->free_time
= time
;
870 list_addtail(&bo
->head
, &bucket
->head
);
877 iris_bo_unreference(struct iris_bo
*bo
)
882 assert(p_atomic_read(&bo
->refcount
) > 0);
884 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
885 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
886 struct timespec time
;
888 clock_gettime(CLOCK_MONOTONIC
, &time
);
890 mtx_lock(&bufmgr
->lock
);
892 if (p_atomic_dec_zero(&bo
->refcount
)) {
893 bo_unreference_final(bo
, time
.tv_sec
);
894 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
897 mtx_unlock(&bufmgr
->lock
);
902 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
906 bool busy
= dbg
&& !bo
->idle
;
907 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
909 iris_bo_wait_rendering(bo
);
911 if (unlikely(busy
)) {
912 elapsed
+= get_time();
913 if (elapsed
> 1e-5) /* 0.01ms */ {
914 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
915 action
, bo
->name
, elapsed
* 1000);
921 print_flags(unsigned flags
)
923 if (flags
& MAP_READ
)
925 if (flags
& MAP_WRITE
)
927 if (flags
& MAP_ASYNC
)
929 if (flags
& MAP_PERSISTENT
)
931 if (flags
& MAP_COHERENT
)
939 iris_bo_gem_mmap_legacy(struct pipe_debug_callback
*dbg
,
940 struct iris_bo
*bo
, bool wc
)
942 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
944 struct drm_i915_gem_mmap mmap_arg
= {
945 .handle
= bo
->gem_handle
,
947 .flags
= wc
? I915_MMAP_WC
: 0,
950 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
952 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
953 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
956 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
962 iris_bo_gem_mmap_offset(struct pipe_debug_callback
*dbg
, struct iris_bo
*bo
,
965 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
967 struct drm_i915_gem_mmap_offset mmap_arg
= {
968 .handle
= bo
->gem_handle
,
969 .flags
= wc
? I915_MMAP_OFFSET_WC
: I915_MMAP_OFFSET_WB
,
972 /* Get the fake offset back */
973 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_OFFSET
, &mmap_arg
);
975 DBG("%s:%d: Error preparing buffer %d (%s): %s .\n",
976 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
981 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
, MAP_SHARED
,
982 bufmgr
->fd
, mmap_arg
.offset
);
983 if (map
== MAP_FAILED
) {
984 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
985 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
993 iris_bo_gem_mmap(struct pipe_debug_callback
*dbg
, struct iris_bo
*bo
, bool wc
)
995 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
997 if (bufmgr
->has_mmap_offset
)
998 return iris_bo_gem_mmap_offset(dbg
, bo
, wc
);
1000 return iris_bo_gem_mmap_legacy(dbg
, bo
, wc
);
1004 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
1005 struct iris_bo
*bo
, unsigned flags
)
1007 /* We disallow CPU maps for writing to non-coherent buffers, as the
1008 * CPU map can become invalidated when a batch is flushed out, which
1009 * can happen at unpredictable times. You should use WC maps instead.
1011 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
1014 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1015 void *map
= iris_bo_gem_mmap(dbg
, bo
, false);
1020 VG_DEFINED(map
, bo
->size
);
1022 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
1023 VG_NOACCESS(map
, bo
->size
);
1024 os_munmap(map
, bo
->size
);
1027 assert(bo
->map_cpu
);
1029 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
1033 if (!(flags
& MAP_ASYNC
)) {
1034 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
1037 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
1038 /* If we're reusing an existing CPU mapping, the CPU caches may
1039 * contain stale data from the last time we read from that mapping.
1040 * (With the BO cache, it might even be data from a previous buffer!)
1041 * Even if it's a brand new mapping, the kernel may have zeroed the
1042 * buffer via CPU writes.
1044 * We need to invalidate those cachelines so that we see the latest
1045 * contents, and so long as we only read from the CPU mmap we do not
1046 * need to write those cachelines back afterwards.
1048 * On LLC, the emprical evidence suggests that writes from the GPU
1049 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
1050 * cachelines. (Other reads, such as the display engine, bypass the
1051 * LLC entirely requiring us to keep dirty pixels for the scanout
1052 * out of any cache.)
1054 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
1061 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
1062 struct iris_bo
*bo
, unsigned flags
)
1065 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1066 void *map
= iris_bo_gem_mmap(dbg
, bo
, true);
1071 VG_DEFINED(map
, bo
->size
);
1073 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
1074 VG_NOACCESS(map
, bo
->size
);
1075 os_munmap(map
, bo
->size
);
1080 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1083 if (!(flags
& MAP_ASYNC
)) {
1084 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
1091 * Perform an uncached mapping via the GTT.
1093 * Write access through the GTT is not quite fully coherent. On low power
1094 * systems especially, like modern Atoms, we can observe reads from RAM before
1095 * the write via GTT has landed. A write memory barrier that flushes the Write
1096 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1097 * read after the write as the GTT write suffers a small delay through the GTT
1098 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1099 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1100 * flushes prior to execbuf submission. However, if we are not informing the
1101 * kernel about our GTT writes, it will not flush before earlier access, such
1102 * as when using the cmdparser. Similarly, we need to be careful if we should
1103 * ever issue a CPU read immediately following a GTT write.
1105 * Telling the kernel about write access also has one more important
1106 * side-effect. Upon receiving notification about the write, it cancels any
1107 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1108 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1109 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1110 * tracking is handled on the buffer exchange instead.
1113 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1114 struct iris_bo
*bo
, unsigned flags
)
1116 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1118 /* Get a mapping of the buffer if we haven't before. */
1119 if (bo
->map_gtt
== NULL
) {
1120 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1122 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1124 /* Get the fake offset back... */
1125 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1127 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1128 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1133 void *map
= os_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1134 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1135 if (map
== MAP_FAILED
) {
1136 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1137 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1141 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1142 * already intercept this mmap call. However, for consistency between
1143 * all the mmap paths, we mark the pointer as defined now and mark it
1144 * as inaccessible afterwards.
1146 VG_DEFINED(map
, bo
->size
);
1148 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1149 VG_NOACCESS(map
, bo
->size
);
1150 os_munmap(map
, bo
->size
);
1153 assert(bo
->map_gtt
);
1155 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1158 if (!(flags
& MAP_ASYNC
)) {
1159 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1166 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1168 if (bo
->cache_coherent
)
1171 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1172 * an LLC platform reads always are coherent (as they are performed via the
1173 * central system agent). It is just the writes that we need to take special
1174 * care to ensure that land in main memory and not stick in the CPU cache.
1176 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1179 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1180 * across batch flushes where the kernel will change cache domains of the
1181 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1183 * Similarly, ASYNC typically means that the buffer will be accessed via
1184 * both the CPU and the GPU simultaneously. Batches may be executed that
1185 * use the BO even while it is mapped. While OpenGL technically disallows
1186 * most drawing while non-persistent mappings are active, we may still use
1187 * the GPU for blits or other operations, causing batches to happen at
1188 * inconvenient times.
1190 * If RAW is set, we expect the caller to be able to handle a WC buffer
1191 * more efficiently than the involuntary clflushes.
1193 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1196 return !(flags
& MAP_WRITE
);
1200 iris_bo_map(struct pipe_debug_callback
*dbg
,
1201 struct iris_bo
*bo
, unsigned flags
)
1203 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1204 return iris_bo_map_gtt(dbg
, bo
, flags
);
1208 if (can_map_cpu(bo
, flags
))
1209 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1211 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1213 /* Allow the attempt to fail by falling back to the GTT where necessary.
1215 * Not every buffer can be mmaped directly using the CPU (or WC), for
1216 * example buffers that wrap stolen memory or are imported from other
1217 * devices. For those, we have little choice but to use a GTT mmapping.
1218 * However, if we use a slow GTT mmapping for reads where we expected fast
1219 * access, that order of magnitude difference in throughput will be clearly
1220 * expressed by angry users.
1222 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1224 if (!map
&& !(flags
& MAP_RAW
)) {
1225 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1227 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1233 /** Waits for all GPU rendering with the object to have completed. */
1235 iris_bo_wait_rendering(struct iris_bo
*bo
)
1237 /* We require a kernel recent enough for WAIT_IOCTL support.
1238 * See intel_init_bufmgr()
1240 iris_bo_wait(bo
, -1);
1244 * Waits on a BO for the given amount of time.
1246 * @bo: buffer object to wait for
1247 * @timeout_ns: amount of time to wait in nanoseconds.
1248 * If value is less than 0, an infinite wait will occur.
1250 * Returns 0 if the wait was successful ie. the last batch referencing the
1251 * object has completed within the allotted time. Otherwise some negative return
1252 * value describes the error. Of particular interest is -ETIME when the wait has
1253 * failed to yield the desired result.
1255 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1256 * the operation to give up after a certain amount of time. Another subtle
1257 * difference is the internal locking semantics are different (this variant does
1258 * not hold the lock for the duration of the wait). This makes the wait subject
1259 * to a larger userspace race window.
1261 * The implementation shall wait until the object is no longer actively
1262 * referenced within a batch buffer at the time of the call. The wait will
1263 * not guarantee that the buffer is re-issued via another thread, or an flinked
1264 * handle. Userspace must make sure this race does not occur if such precision
1267 * Note that some kernels have broken the inifite wait for negative values
1268 * promise, upgrade to latest stable kernels if this is the case.
1271 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1273 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1275 /* If we know it's idle, don't bother with the kernel round trip */
1276 if (bo
->idle
&& !bo
->external
)
1279 struct drm_i915_gem_wait wait
= {
1280 .bo_handle
= bo
->gem_handle
,
1281 .timeout_ns
= timeout_ns
,
1283 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1293 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1295 /* Free aux-map buffers */
1296 gen_aux_map_finish(bufmgr
->aux_map_ctx
);
1298 /* bufmgr will no longer try to free VMA entries in the aux-map */
1299 bufmgr
->aux_map_ctx
= NULL
;
1301 mtx_destroy(&bufmgr
->lock
);
1303 /* Free any cached buffer objects we were going to reuse */
1304 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1305 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1307 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1308 list_del(&bo
->head
);
1314 /* Close any buffer objects on the dead list. */
1315 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
1316 list_del(&bo
->head
);
1320 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1321 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1323 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1324 if (z
!= IRIS_MEMZONE_BINDER
)
1325 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1334 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1337 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1338 struct drm_i915_gem_set_tiling set_tiling
;
1341 if (bo
->global_name
== 0 &&
1342 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1345 memset(&set_tiling
, 0, sizeof(set_tiling
));
1347 /* set_tiling is slightly broken and overwrites the
1348 * input on the error path, so we have to open code
1351 set_tiling
.handle
= bo
->gem_handle
;
1352 set_tiling
.tiling_mode
= tiling_mode
;
1353 set_tiling
.stride
= stride
;
1355 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1356 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1360 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1361 bo
->stride
= set_tiling
.stride
;
1366 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
,
1367 uint32_t tiling
, uint32_t stride
)
1372 mtx_lock(&bufmgr
->lock
);
1373 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1375 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1377 mtx_unlock(&bufmgr
->lock
);
1382 * See if the kernel has already returned this buffer to us. Just as
1383 * for named buffers, we must not create two bo's pointing at the same
1386 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, handle
);
1394 p_atomic_set(&bo
->refcount
, 1);
1396 /* Determine size of bo. The fd-to-handle ioctl really should
1397 * return the size, but it doesn't. If we have kernel 3.12 or
1398 * later, we can lseek on the prime fd to get the size. Older
1399 * kernels will just fail, in which case we fall back to the
1400 * provided (estimated or guess size). */
1401 ret
= lseek(prime_fd
, 0, SEEK_END
);
1405 bo
->bufmgr
= bufmgr
;
1407 bo
->reusable
= false;
1408 bo
->external
= true;
1409 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1411 /* From the Bspec, Memory Compression - Gen12:
1413 * The base address for the surface has to be 64K page aligned and the
1414 * surface is expected to be padded in the virtual domain to be 4 4K
1417 * The dmabuf may contain a compressed surface. Align the BO to 64KB just
1418 * in case. We always align to 64KB even on platforms where we don't need
1419 * to, because it's a fairly reasonable thing to do anyway.
1422 vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 64 * 1024);
1424 bo
->gem_handle
= handle
;
1425 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1427 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1428 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1431 if (get_tiling
.tiling_mode
== tiling
|| tiling
> I915_TILING_LAST
) {
1432 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1433 /* XXX stride is unknown */
1435 if (bo_set_tiling_internal(bo
, tiling
, stride
)) {
1441 mtx_unlock(&bufmgr
->lock
);
1446 mtx_unlock(&bufmgr
->lock
);
1451 iris_bo_make_external_locked(struct iris_bo
*bo
)
1453 if (!bo
->external
) {
1454 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1455 /* If a BO is going to be used externally, it could be sent to the
1456 * display HW. So make sure our CPU mappings don't assume cache
1457 * coherency since display is outside that cache.
1459 bo
->cache_coherent
= false;
1460 bo
->external
= true;
1461 bo
->reusable
= false;
1466 iris_bo_make_external(struct iris_bo
*bo
)
1468 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1471 assert(!bo
->reusable
);
1475 mtx_lock(&bufmgr
->lock
);
1476 iris_bo_make_external_locked(bo
);
1477 mtx_unlock(&bufmgr
->lock
);
1481 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1483 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1485 iris_bo_make_external(bo
);
1487 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1488 DRM_CLOEXEC
, prime_fd
) != 0)
1495 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1497 iris_bo_make_external(bo
);
1499 return bo
->gem_handle
;
1503 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1505 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1507 if (!bo
->global_name
) {
1508 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1510 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1513 mtx_lock(&bufmgr
->lock
);
1514 if (!bo
->global_name
) {
1515 iris_bo_make_external_locked(bo
);
1516 bo
->global_name
= flink
.name
;
1517 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1519 mtx_unlock(&bufmgr
->lock
);
1522 *name
= bo
->global_name
;
1527 iris_bo_export_gem_handle_for_device(struct iris_bo
*bo
, int drm_fd
,
1528 uint32_t *out_handle
)
1530 /* Only add the new GEM handle to the list of export if it belongs to a
1531 * different GEM device. Otherwise we might close the same buffer multiple
1534 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1535 int ret
= os_same_file_description(drm_fd
, bufmgr
->fd
);
1537 "Kernel has no file descriptor comparison support: %s\n",
1540 *out_handle
= iris_bo_export_gem_handle(bo
);
1544 struct bo_export
*export
= calloc(1, sizeof(*export
));
1548 export
->drm_fd
= drm_fd
;
1551 int err
= iris_bo_export_dmabuf(bo
, &dmabuf_fd
);
1557 mtx_lock(&bufmgr
->lock
);
1558 err
= drmPrimeFDToHandle(drm_fd
, dmabuf_fd
, &export
->gem_handle
);
1561 mtx_unlock(&bufmgr
->lock
);
1567 list_for_each_entry(struct bo_export
, iter
, &bo
->exports
, link
) {
1568 if (iter
->drm_fd
!= drm_fd
)
1570 /* Here we assume that for a given DRM fd, we'll always get back the
1571 * same GEM handle for a given buffer.
1573 assert(iter
->gem_handle
== export
->gem_handle
);
1580 list_addtail(&export
->link
, &bo
->exports
);
1582 mtx_unlock(&bufmgr
->lock
);
1584 *out_handle
= export
->gem_handle
;
1590 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1592 unsigned int i
= bufmgr
->num_buckets
;
1594 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1596 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1597 bufmgr
->cache_bucket
[i
].size
= size
;
1598 bufmgr
->num_buckets
++;
1600 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1601 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1602 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1606 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1608 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1610 /* OK, so power of two buckets was too wasteful of memory.
1611 * Give 3 other sizes between each power of two, to hopefully
1612 * cover things accurately enough. (The alternative is
1613 * probably to just go for exact matching of sizes, and assume
1614 * that for things like composited window resize the tiled
1615 * width/height alignment and rounding of sizes to pages will
1616 * get us useful cache hit rates anyway)
1618 add_bucket(bufmgr
, PAGE_SIZE
);
1619 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1620 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1622 /* Initialize the linked lists for BO reuse cache. */
1623 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1624 add_bucket(bufmgr
, size
);
1626 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1627 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1628 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1633 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1635 struct drm_i915_gem_context_create create
= { };
1636 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1638 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1642 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1643 * back to the default logical HW state and attempt to continue on to
1644 * our next submitted batchbuffer. However, our render batches assume
1645 * the previous GPU state is preserved, and only emit commands needed
1646 * to incrementally change that state. In particular, we inherit the
1647 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1648 * With default base addresses, our next batches will almost certainly
1649 * cause more GPU hangs, leading to repeated hangs until we're banned
1650 * or the machine is dead.
1652 * Here we tell the kernel not to attempt to recover our context but
1653 * immediately (on the next batchbuffer submission) report that the
1654 * context is lost, and we will do the recovery ourselves. Ideally,
1655 * we'll have two lost batches instead of a continual stream of hangs.
1657 struct drm_i915_gem_context_param p
= {
1658 .ctx_id
= create
.ctx_id
,
1659 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1662 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1664 return create
.ctx_id
;
1668 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1670 struct drm_i915_gem_context_param p
= {
1672 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1674 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1675 return p
.value
; /* on error, return 0 i.e. default priority */
1679 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1683 struct drm_i915_gem_context_param p
= {
1685 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1691 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1698 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1700 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1703 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1704 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1711 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1713 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1716 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1717 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1723 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1725 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1726 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1728 *result
= reg_read
.val
;
1733 iris_gtt_size(int fd
)
1735 /* We use the default (already allocated) context to determine
1736 * the default configuration of the virtual address space.
1738 struct drm_i915_gem_context_param p
= {
1739 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1741 if (!gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1747 static struct gen_buffer
*
1748 gen_aux_map_buffer_alloc(void *driver_ctx
, uint32_t size
)
1750 struct gen_buffer
*buf
= malloc(sizeof(struct gen_buffer
));
1754 struct iris_bufmgr
*bufmgr
= (struct iris_bufmgr
*)driver_ctx
;
1756 struct iris_bo
*bo
=
1757 iris_bo_alloc_tiled(bufmgr
, "aux-map", size
, 64 * 1024,
1758 IRIS_MEMZONE_OTHER
, I915_TILING_NONE
, 0, 0);
1760 buf
->driver_bo
= bo
;
1761 buf
->gpu
= bo
->gtt_offset
;
1762 buf
->gpu_end
= buf
->gpu
+ bo
->size
;
1763 buf
->map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
1768 gen_aux_map_buffer_free(void *driver_ctx
, struct gen_buffer
*buffer
)
1770 iris_bo_unreference((struct iris_bo
*)buffer
->driver_bo
);
1774 static struct gen_mapped_pinned_buffer_alloc aux_map_allocator
= {
1775 .alloc
= gen_aux_map_buffer_alloc
,
1776 .free
= gen_aux_map_buffer_free
,
1780 gem_param(int fd
, int name
)
1782 int v
= -1; /* No param uses (yet) the sign bit, reserve it for errors */
1784 struct drm_i915_getparam gp
= { .param
= name
, .value
= &v
};
1785 if (gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
))
1792 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1793 * and manage map buffer objections.
1795 * \param fd File descriptor of the opened DRM device.
1797 static struct iris_bufmgr
*
1798 iris_bufmgr_create(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1800 uint64_t gtt_size
= iris_gtt_size(fd
);
1801 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1804 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1808 /* Handles to buffer objects belong to the device fd and are not
1809 * reference counted by the kernel. If the same fd is used by
1810 * multiple parties (threads sharing the same screen bufmgr, or
1811 * even worse the same device fd passed to multiple libraries)
1812 * ownership of those handles is shared by those independent parties.
1814 * Don't do this! Ensure that each library/bufmgr has its own device
1815 * fd so that its namespace does not clash with another.
1817 bufmgr
->fd
= os_dupfd_cloexec(fd
);
1819 p_atomic_set(&bufmgr
->refcount
, 1);
1821 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1827 list_inithead(&bufmgr
->zombie_list
);
1829 bufmgr
->has_llc
= devinfo
->has_llc
;
1830 bufmgr
->bo_reuse
= bo_reuse
;
1831 bufmgr
->has_mmap_offset
= gem_param(fd
, I915_PARAM_MMAP_GTT_VERSION
) >= 4;
1833 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1834 const uint64_t _4GB
= 1ull << 32;
1835 const uint64_t _2GB
= 1ul << 31;
1837 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1838 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1840 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1841 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1842 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1843 IRIS_MEMZONE_SURFACE_START
,
1844 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1845 /* TODO: Why does limiting to 2GB help some state items on gen12?
1846 * - CC Viewport Pointer
1847 * - Blend State Pointer
1848 * - Color Calc State Pointer
1850 const uint64_t dynamic_pool_size
=
1851 (devinfo
->gen
>= 12 ? _2GB
: _4GB_minus_1
) - IRIS_BORDER_COLOR_POOL_SIZE
;
1852 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1853 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1856 /* Leave the last 4GB out of the high vma range, so that no state
1857 * base address + size can overflow 48 bits.
1859 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1860 IRIS_MEMZONE_OTHER_START
,
1861 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1863 init_cache_buckets(bufmgr
);
1865 bufmgr
->name_table
=
1866 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1867 bufmgr
->handle_table
=
1868 _mesa_hash_table_create(NULL
, _mesa_hash_uint
, _mesa_key_uint_equal
);
1870 if (devinfo
->gen
>= 12) {
1871 bufmgr
->aux_map_ctx
= gen_aux_map_init(bufmgr
, &aux_map_allocator
,
1873 assert(bufmgr
->aux_map_ctx
);
1879 static struct iris_bufmgr
*
1880 iris_bufmgr_ref(struct iris_bufmgr
*bufmgr
)
1882 p_atomic_inc(&bufmgr
->refcount
);
1887 iris_bufmgr_unref(struct iris_bufmgr
*bufmgr
)
1889 mtx_lock(&global_bufmgr_list_mutex
);
1890 if (p_atomic_dec_zero(&bufmgr
->refcount
)) {
1891 list_del(&bufmgr
->link
);
1892 iris_bufmgr_destroy(bufmgr
);
1894 mtx_unlock(&global_bufmgr_list_mutex
);
1898 * Gets an already existing GEM buffer manager or create a new one.
1900 * \param fd File descriptor of the opened DRM device.
1902 struct iris_bufmgr
*
1903 iris_bufmgr_get_for_fd(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1910 struct iris_bufmgr
*bufmgr
= NULL
;
1912 mtx_lock(&global_bufmgr_list_mutex
);
1913 list_for_each_entry(struct iris_bufmgr
, iter_bufmgr
, &global_bufmgr_list
, link
) {
1914 struct stat iter_st
;
1915 if (fstat(iter_bufmgr
->fd
, &iter_st
))
1918 if (st
.st_rdev
== iter_st
.st_rdev
) {
1919 assert(iter_bufmgr
->bo_reuse
== bo_reuse
);
1920 bufmgr
= iris_bufmgr_ref(iter_bufmgr
);
1925 bufmgr
= iris_bufmgr_create(devinfo
, fd
, bo_reuse
);
1926 list_addtail(&bufmgr
->link
, &global_bufmgr_list
);
1929 mtx_unlock(&global_bufmgr_list_mutex
);
1935 iris_bufmgr_get_fd(struct iris_bufmgr
*bufmgr
)
1941 iris_bufmgr_get_aux_map_context(struct iris_bufmgr
*bufmgr
)
1943 return bufmgr
->aux_map_ctx
;