src/gallium/drivers/iris/iris_bufmgr.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BUFMGR_H
  25 #define IRIS_BUFMGR_H
  26
  27 #include <stdbool.h>
  28 #include <stdint.h>
  29 #include <stdio.h>
  30 #include <sys/types.h>
  31 #include "util/macros.h"
  32 #include "util/u_atomic.h"
  33 #include "util/list.h"
  34 #include "pipe/p_defines.h"
  35
  36 struct gen_device_info;
  37 struct pipe_debug_callback;
  38
  39 /**
  40  * Memory zones.  When allocating a buffer, you can request that it is
  41  * placed into a specific region of the virtual address space (PPGTT).
  42  *
  43  * Most buffers can go anywhere (IRIS_MEMZONE_OTHER).  Some buffers are
  44  * accessed via an offset from a base address.  STATE_BASE_ADDRESS has
  45  * a maximum 4GB size for each region, so we need to restrict those
  46  * buffers to be within 4GB of the base.  Each memory zone corresponds
  47  * to a particular base address.
  48  *
  49  * We lay out the virtual address space as follows:
  50  *
  51  * - [0,   4K): Nothing  (empty page for null address)
  52  * - [4K,  4G): Shaders  (Instruction Base Address)
  53  * - [4G,  8G): Surfaces (Surface State Base Address, Bindless ...)
  54  * - [8G, 12G): Dynamic  (Dynamic State Base Address)
  55  * - [12G, *):  Other    (everything else in the full 48-bit VMA)
  56  *
  57  * A special 64kB "binder" buffer lives at the start of the surface memory
  58  * zone, holding binding tables referring to objects in the rest of the zone.
  59  *
  60  * Each GL context uses a separate GEM context, which technically gives them
  61  * each a separate VMA.  However, we assign address globally, so buffers will
  62  * have the same address in all GEM contexts.  This lets us have a single BO
  63  * field for the address, which is easy and cheap.
  64  *
  65  * One exception is the special "binder" BO.  Binders are context-local,
  66  * so while there are many of them, all binders are stored at the same
  67  * fixed address (in different VMAs).
  68  */
  69 enum iris_memory_zone {
  70    IRIS_MEMZONE_SHADER,
  71    IRIS_MEMZONE_SURFACE,
  72    IRIS_MEMZONE_DYNAMIC,
  73    IRIS_MEMZONE_OTHER,
  74
  75    IRIS_MEMZONE_BINDER,
  76 };
  77
  78 /* Intentionally exclude IRIS_MEMZONE_BINDER */
  79 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
  80
  81 #define IRIS_MEMZONE_SHADER_START     (0ull * (1ull << 32))
  82 #define IRIS_MEMZONE_SURFACE_START    (1ull * (1ull << 32))
  83 #define IRIS_MEMZONE_DYNAMIC_START    (2ull * (1ull << 32))
  84 #define IRIS_MEMZONE_OTHER_START      (3ull * (1ull << 32))
  85
  86 #define IRIS_BINDER_ADDRESS IRIS_MEMZONE_SURFACE_START
  87 #define IRIS_BINDER_SIZE (64 * 1024)
  88
  89 struct iris_bo {
  90    /**
  91     * Size in bytes of the buffer object.
  92     *
  93     * The size may be larger than the size originally requested for the
  94     * allocation, such as being aligned to page size.
  95     */
  96    uint64_t size;
  97
  98    /** Buffer manager context associated with this buffer object */
  99    struct iris_bufmgr *bufmgr;
 100
 101    /** The GEM handle for this buffer object. */
 102    uint32_t gem_handle;
 103
 104    /**
 105     * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
 106     * Translation Table).
 107     *
 108     * Although each hardware context has its own VMA, we assign BO's to the
 109     * same address in all contexts, for simplicity.
 110     */
 111    uint64_t gtt_offset;
 112
 113    /**
 114     * The validation list index for this buffer, or -1 when not in a batch.
 115     * Note that a single buffer may be in multiple batches (contexts), and
 116     * this is a global field, which refers to the last batch using the BO.
 117     * It should not be considered authoritative, but can be used to avoid a
 118     * linear walk of the validation list in the common case by guessing that
 119     * exec_bos[bo->index] == bo and confirming whether that's the case.
 120     */
 121    unsigned index;
 122
 123    /**
 124     * Boolean of whether the GPU is definitely not accessing the buffer.
 125     *
 126     * This is only valid when reusable, since non-reusable
 127     * buffers are those that have been shared with other
 128     * processes, so we don't know their state.
 129     */
 130    bool idle;
 131
 132    int refcount;
 133    const char *name;
 134
 135    uint64_t kflags;
 136
 137    /**
 138     * Kenel-assigned global name for this object
 139     *
 140     * List contains both flink named and prime fd'd objects
 141     */
 142    unsigned global_name;
 143
 144    /**
 145     * Current tiling mode
 146     */
 147    uint32_t tiling_mode;
 148    uint32_t swizzle_mode;
 149    uint32_t stride;
 150
 151    time_t free_time;
 152
 153    /** Mapped address for the buffer, saved across map/unmap cycles */
 154    void *map_cpu;
 155    /** GTT virtual address for the buffer, saved across map/unmap cycles */
 156    void *map_gtt;
 157    /** WC CPU address for the buffer, saved across map/unmap cycles */
 158    void *map_wc;
 159
 160    /** BO cache list */
 161    struct list_head head;
 162
 163    /**
 164     * Boolean of whether this buffer can be re-used
 165     */
 166    bool reusable;
 167
 168    /**
 169     * Boolean of whether this buffer has been shared with an external client.
 170     */
 171    bool external;
 172
 173    /**
 174     * Boolean of whether this buffer is cache coherent
 175     */
 176    bool cache_coherent;
 177 };
 178
 179 #define BO_ALLOC_ZEROED     (1<<0)
 180
 181 /**
 182  * Allocate a buffer object.
 183  *
 184  * Buffer objects are not necessarily initially mapped into CPU virtual
 185  * address space or graphics device aperture.  They must be mapped
 186  * using iris_bo_map() to be used by the CPU.
 187  */
 188 struct iris_bo *iris_bo_alloc(struct iris_bufmgr *bufmgr,
 189                               const char *name,
 190                               uint64_t size,
 191                               enum iris_memory_zone memzone);
 192
 193 /**
 194  * Allocate a tiled buffer object.
 195  *
 196  * Alignment for tiled objects is set automatically; the 'flags'
 197  * argument provides a hint about how the object will be used initially.
 198  *
 199  * Valid tiling formats are:
 200  *  I915_TILING_NONE
 201  *  I915_TILING_X
 202  *  I915_TILING_Y
 203  */
 204 struct iris_bo *iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr,
 205                                     const char *name,
 206                                     uint64_t size,
 207                                     uint32_t tiling_mode,
 208                                     uint32_t pitch,
 209                                     unsigned flags,
 210                                     enum iris_memory_zone memzone);
 211
 212 /** Takes a reference on a buffer object */
 213 static inline void
 214 iris_bo_reference(struct iris_bo *bo)
 215 {
 216    p_atomic_inc(&bo->refcount);
 217 }
 218
 219 /**
 220  * Releases a reference on a buffer object, freeing the data if
 221  * no references remain.
 222  */
 223 void iris_bo_unreference(struct iris_bo *bo);
 224
 225 #define MAP_READ          PIPE_TRANSFER_READ
 226 #define MAP_WRITE         PIPE_TRANSFER_WRITE
 227 #define MAP_ASYNC         PIPE_TRANSFER_UNSYNCHRONIZED
 228 #define MAP_PERSISTENT    PIPE_TRANSFER_PERSISTENT
 229 #define MAP_COHERENT      PIPE_TRANSFER_COHERENT
 230 /* internal */
 231 #define MAP_INTERNAL_MASK (0xff << 24)
 232 #define MAP_RAW           (0x01 << 24)
 233
 234 /**
 235  * Maps the buffer into userspace.
 236  *
 237  * This function will block waiting for any existing execution on the
 238  * buffer to complete, first.  The resulting mapping is returned.
 239  */
 240 MUST_CHECK void *iris_bo_map(struct pipe_debug_callback *dbg,
 241                              struct iris_bo *bo, unsigned flags);
 242
 243 /**
 244  * Reduces the refcount on the userspace mapping of the buffer
 245  * object.
 246  */
 247 static inline int iris_bo_unmap(struct iris_bo *bo) { return 0; }
 248
 249 /** Write data into an object. */
 250 int iris_bo_subdata(struct iris_bo *bo, uint64_t offset,
 251                    uint64_t size, const void *data);
 252 /**
 253  * Waits for rendering to an object by the GPU to have completed.
 254  *
 255  * This is not required for any access to the BO by bo_map,
 256  * bo_subdata, etc.  It is merely a way for the driver to implement
 257  * glFinish.
 258  */
 259 void iris_bo_wait_rendering(struct iris_bo *bo);
 260
 261 /**
 262  * Tears down the buffer manager instance.
 263  */
 264 void iris_bufmgr_destroy(struct iris_bufmgr *bufmgr);
 265
 266 /**
 267  * Get the current tiling (and resulting swizzling) mode for the bo.
 268  *
 269  * \param buf Buffer to get tiling mode for
 270  * \param tiling_mode returned tiling mode
 271  * \param swizzle_mode returned swizzling mode
 272  */
 273 int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
 274                       uint32_t *swizzle_mode);
 275
 276 /**
 277  * Create a visible name for a buffer which can be used by other apps
 278  *
 279  * \param buf Buffer to create a name for
 280  * \param name Returned name
 281  */
 282 int iris_bo_flink(struct iris_bo *bo, uint32_t *name);
 283
 284 /**
 285  * Returns 1 if mapping the buffer for write could cause the process
 286  * to block, due to the object being active in the GPU.
 287  */
 288 int iris_bo_busy(struct iris_bo *bo);
 289
 290 /**
 291  * Specify the volatility of the buffer.
 292  * \param bo Buffer to create a name for
 293  * \param madv The purgeable status
 294  *
 295  * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
 296  * reclaimed under memory pressure. If you subsequently require the buffer,
 297  * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
 298  *
 299  * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
 300  * marked as I915_MADV_DONTNEED.
 301  */
 302 int iris_bo_madvise(struct iris_bo *bo, int madv);
 303
 304 /* drm_bacon_bufmgr_gem.c */
 305 struct iris_bufmgr *iris_bufmgr_init(struct gen_device_info *devinfo, int fd);
 306 struct iris_bo *iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr,
 307                                              const char *name,
 308                                              unsigned handle);
 309 void iris_bufmgr_enable_reuse(struct iris_bufmgr *bufmgr);
 310
 311 int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns);
 312
 313 uint32_t iris_create_hw_context(struct iris_bufmgr *bufmgr);
 314
 315 #define IRIS_CONTEXT_LOW_PRIORITY    ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 316 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
 317 #define IRIS_CONTEXT_HIGH_PRIORITY   ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
 318
 319 int iris_hw_context_set_priority(struct iris_bufmgr *bufmgr,
 320                                  uint32_t ctx_id, int priority);
 321
 322 void iris_destroy_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 323
 324 int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd);
 325 struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd);
 326
 327 uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
 328
 329 int iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *out);
 330
 331 int drm_ioctl(int fd, unsigned long request, void *arg);
 332
 333 /**
 334  * Returns the BO's address relative to the appropriate base address.
 335  *
 336  * All of our base addresses are programmed to the start of a 4GB region,
 337  * so simply returning the bottom 32 bits of the BO address will give us
 338  * the offset from whatever base address corresponds to that memory region.
 339  */
 340 static inline uint32_t
 341 iris_bo_offset_from_base_address(struct iris_bo *bo)
 342 {
 343    /* This only works for buffers in the memory zones corresponding to a
 344     * base address - the top, unbounded memory zone doesn't have a base.
 345     */
 346    assert(bo->gtt_offset < IRIS_MEMZONE_OTHER_START);
 347    return bo->gtt_offset;
 348 }
 349
 350 #endif /* IRIS_BUFMGR_H */