2 * Copyright © 2017 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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30 #include <sys/types.h>
31 #include "util/macros.h"
32 #include "util/u_atomic.h"
33 #include "util/list.h"
34 #include "pipe/p_defines.h"
36 struct gen_device_info
;
37 struct pipe_debug_callback
;
40 * Memory zones. When allocating a buffer, you can request that it is
41 * placed into a specific region of the virtual address space (PPGTT).
43 * Most buffers can go anywhere (IRIS_MEMZONE_OTHER). Some buffers are
44 * accessed via an offset from a base address. STATE_BASE_ADDRESS has
45 * a maximum 4GB size for each region, so we need to restrict those
46 * buffers to be within 4GB of the base. Each memory zone corresponds
47 * to a particular base address.
49 * We lay out the virtual address space as follows:
51 * - [0, 4K): Nothing (empty page for null address)
52 * - [4K, 4G): Shaders (Instruction Base Address)
53 * - [4G, 8G): Surfaces & Binders (Surface State Base Address, Bindless ...)
54 * - [8G, 12G): Dynamic (Dynamic State Base Address)
55 * - [12G, *): Other (everything else in the full 48-bit VMA)
57 * A special buffer for border color lives at the start of the dynamic state
58 * memory zone. This unfortunately has to be handled specially because the
59 * SAMPLER_STATE "Indirect State Pointer" field is only a 24-bit pointer.
61 * Each GL context uses a separate GEM context, which technically gives them
62 * each a separate VMA. However, we assign address globally, so buffers will
63 * have the same address in all GEM contexts. This lets us have a single BO
64 * field for the address, which is easy and cheap.
66 enum iris_memory_zone
{
73 IRIS_MEMZONE_BORDER_COLOR_POOL
,
76 /* Intentionally exclude single buffer "zones" */
77 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
79 #define IRIS_BINDER_SIZE (64 * 1024)
80 #define IRIS_MAX_BINDERS 100
82 #define IRIS_MEMZONE_SHADER_START (0ull * (1ull << 32))
83 #define IRIS_MEMZONE_BINDER_START (1ull * (1ull << 32))
84 #define IRIS_MEMZONE_SURFACE_START (IRIS_MEMZONE_BINDER_START + IRIS_MAX_BINDERS * IRIS_BINDER_SIZE)
85 #define IRIS_MEMZONE_DYNAMIC_START (2ull * (1ull << 32))
86 #define IRIS_MEMZONE_OTHER_START (3ull * (1ull << 32))
88 #define IRIS_BORDER_COLOR_POOL_ADDRESS IRIS_MEMZONE_DYNAMIC_START
89 #define IRIS_BORDER_COLOR_POOL_SIZE (64 * 1024)
93 * Size in bytes of the buffer object.
95 * The size may be larger than the size originally requested for the
96 * allocation, such as being aligned to page size.
100 /** Buffer manager context associated with this buffer object */
101 struct iris_bufmgr
*bufmgr
;
103 /** The GEM handle for this buffer object. */
107 * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
108 * Translation Table).
110 * Although each hardware context has its own VMA, we assign BO's to the
111 * same address in all contexts, for simplicity.
116 * The validation list index for this buffer, or -1 when not in a batch.
117 * Note that a single buffer may be in multiple batches (contexts), and
118 * this is a global field, which refers to the last batch using the BO.
119 * It should not be considered authoritative, but can be used to avoid a
120 * linear walk of the validation list in the common case by guessing that
121 * exec_bos[bo->index] == bo and confirming whether that's the case.
123 * XXX: this is not ideal now that we have more than one batch per context,
124 * XXX: as the index will flop back and forth between the render index and
125 * XXX: compute index...
130 * Boolean of whether the GPU is definitely not accessing the buffer.
132 * This is only valid when reusable, since non-reusable
133 * buffers are those that have been shared with other
134 * processes, so we don't know their state.
144 * Kenel-assigned global name for this object
146 * List contains both flink named and prime fd'd objects
148 unsigned global_name
;
151 * Current tiling mode
153 uint32_t tiling_mode
;
154 uint32_t swizzle_mode
;
159 /** Mapped address for the buffer, saved across map/unmap cycles */
161 /** GTT virtual address for the buffer, saved across map/unmap cycles */
163 /** WC CPU address for the buffer, saved across map/unmap cycles */
167 struct list_head head
;
170 * Boolean of whether this buffer can be re-used
175 * Boolean of whether this buffer has been shared with an external client.
180 * Boolean of whether this buffer is cache coherent
185 * Boolean of whether this buffer points into user memory
189 /** Pre-computed hash using _mesa_hash_pointer for cache tracking sets */
193 #define BO_ALLOC_ZEROED (1<<0)
196 * Allocate a buffer object.
198 * Buffer objects are not necessarily initially mapped into CPU virtual
199 * address space or graphics device aperture. They must be mapped
200 * using iris_bo_map() to be used by the CPU.
202 struct iris_bo
*iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
205 enum iris_memory_zone memzone
);
208 * Allocate a tiled buffer object.
210 * Alignment for tiled objects is set automatically; the 'flags'
211 * argument provides a hint about how the object will be used initially.
213 * Valid tiling formats are:
218 struct iris_bo
*iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
,
221 enum iris_memory_zone memzone
,
222 uint32_t tiling_mode
,
227 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
228 void *ptr
, size_t size
,
229 enum iris_memory_zone memzone
);
231 /** Takes a reference on a buffer object */
233 iris_bo_reference(struct iris_bo
*bo
)
235 p_atomic_inc(&bo
->refcount
);
239 * Releases a reference on a buffer object, freeing the data if
240 * no references remain.
242 void iris_bo_unreference(struct iris_bo
*bo
);
244 #define MAP_READ PIPE_TRANSFER_READ
245 #define MAP_WRITE PIPE_TRANSFER_WRITE
246 #define MAP_ASYNC PIPE_TRANSFER_UNSYNCHRONIZED
247 #define MAP_PERSISTENT PIPE_TRANSFER_PERSISTENT
248 #define MAP_COHERENT PIPE_TRANSFER_COHERENT
250 #define MAP_INTERNAL_MASK (0xff << 24)
251 #define MAP_RAW (0x01 << 24)
254 * Maps the buffer into userspace.
256 * This function will block waiting for any existing execution on the
257 * buffer to complete, first. The resulting mapping is returned.
259 MUST_CHECK
void *iris_bo_map(struct pipe_debug_callback
*dbg
,
260 struct iris_bo
*bo
, unsigned flags
);
263 * Reduces the refcount on the userspace mapping of the buffer
266 static inline int iris_bo_unmap(struct iris_bo
*bo
) { return 0; }
269 * Waits for rendering to an object by the GPU to have completed.
271 * This is not required for any access to the BO by bo_map,
272 * bo_subdata, etc. It is merely a way for the driver to implement
275 void iris_bo_wait_rendering(struct iris_bo
*bo
);
278 * Tears down the buffer manager instance.
280 void iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
);
283 * Get the current tiling (and resulting swizzling) mode for the bo.
285 * \param buf Buffer to get tiling mode for
286 * \param tiling_mode returned tiling mode
287 * \param swizzle_mode returned swizzling mode
289 int iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
290 uint32_t *swizzle_mode
);
293 * Create a visible name for a buffer which can be used by other apps
295 * \param buf Buffer to create a name for
296 * \param name Returned name
298 int iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
);
301 * Returns 1 if mapping the buffer for write could cause the process
302 * to block, due to the object being active in the GPU.
304 int iris_bo_busy(struct iris_bo
*bo
);
307 * Specify the volatility of the buffer.
308 * \param bo Buffer to create a name for
309 * \param madv The purgeable status
311 * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
312 * reclaimed under memory pressure. If you subsequently require the buffer,
313 * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
315 * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
316 * marked as I915_MADV_DONTNEED.
318 int iris_bo_madvise(struct iris_bo
*bo
, int madv
);
320 /* drm_bacon_bufmgr_gem.c */
321 struct iris_bufmgr
*iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
);
322 struct iris_bo
*iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
325 void iris_bufmgr_enable_reuse(struct iris_bufmgr
*bufmgr
);
327 int iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
);
329 uint32_t iris_create_hw_context(struct iris_bufmgr
*bufmgr
);
331 #define IRIS_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
332 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
333 #define IRIS_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
335 int iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
336 uint32_t ctx_id
, int priority
);
338 void iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
);
340 int iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
);
341 struct iris_bo
*iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
);
343 uint32_t iris_bo_export_gem_handle(struct iris_bo
*bo
);
345 int iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *out
);
347 int drm_ioctl(int fd
, unsigned long request
, void *arg
);
350 * Returns the BO's address relative to the appropriate base address.
352 * All of our base addresses are programmed to the start of a 4GB region,
353 * so simply returning the bottom 32 bits of the BO address will give us
354 * the offset from whatever base address corresponds to that memory region.
356 static inline uint32_t
357 iris_bo_offset_from_base_address(struct iris_bo
*bo
)
359 /* This only works for buffers in the memory zones corresponding to a
360 * base address - the top, unbounded memory zone doesn't have a base.
362 assert(bo
->gtt_offset
< IRIS_MEMZONE_OTHER_START
);
363 return bo
->gtt_offset
;
366 #endif /* IRIS_BUFMGR_H */