2 * Copyright © 2017 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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30 #include <sys/types.h>
31 #include "util/macros.h"
32 #include "util/u_atomic.h"
33 #include "util/list.h"
34 #include "pipe/p_defines.h"
37 struct gen_device_info
;
38 struct pipe_debug_callback
;
41 * Memory zones. When allocating a buffer, you can request that it is
42 * placed into a specific region of the virtual address space (PPGTT).
44 * Most buffers can go anywhere (IRIS_MEMZONE_OTHER). Some buffers are
45 * accessed via an offset from a base address. STATE_BASE_ADDRESS has
46 * a maximum 4GB size for each region, so we need to restrict those
47 * buffers to be within 4GB of the base. Each memory zone corresponds
48 * to a particular base address.
50 * We lay out the virtual address space as follows:
52 * - [0, 4K): Nothing (empty page for null address)
53 * - [4K, 4G): Shaders (Instruction Base Address)
54 * - [4G, 8G): Surfaces & Binders (Surface State Base Address, Bindless ...)
55 * - [8G, 12G): Dynamic (Dynamic State Base Address)
56 * - [12G, *): Other (everything else in the full 48-bit VMA)
58 * A special buffer for border color lives at the start of the dynamic state
59 * memory zone. This unfortunately has to be handled specially because the
60 * SAMPLER_STATE "Indirect State Pointer" field is only a 24-bit pointer.
62 * Each GL context uses a separate GEM context, which technically gives them
63 * each a separate VMA. However, we assign address globally, so buffers will
64 * have the same address in all GEM contexts. This lets us have a single BO
65 * field for the address, which is easy and cheap.
67 enum iris_memory_zone
{
74 IRIS_MEMZONE_BORDER_COLOR_POOL
,
77 /* Intentionally exclude single buffer "zones" */
78 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
80 #define IRIS_BINDER_SIZE (64 * 1024)
81 #define IRIS_MAX_BINDERS 100
83 #define IRIS_MEMZONE_SHADER_START (0ull * (1ull << 32))
84 #define IRIS_MEMZONE_BINDER_START (1ull * (1ull << 32))
85 #define IRIS_MEMZONE_SURFACE_START (IRIS_MEMZONE_BINDER_START + IRIS_MAX_BINDERS * IRIS_BINDER_SIZE)
86 #define IRIS_MEMZONE_DYNAMIC_START (2ull * (1ull << 32))
87 #define IRIS_MEMZONE_OTHER_START (3ull * (1ull << 32))
89 #define IRIS_BORDER_COLOR_POOL_ADDRESS IRIS_MEMZONE_DYNAMIC_START
90 #define IRIS_BORDER_COLOR_POOL_SIZE (64 * 1024)
94 * Size in bytes of the buffer object.
96 * The size may be larger than the size originally requested for the
97 * allocation, such as being aligned to page size.
101 /** Buffer manager context associated with this buffer object */
102 struct iris_bufmgr
*bufmgr
;
104 /** Pre-computed hash using _mesa_hash_pointer for cache tracking sets */
107 /** The GEM handle for this buffer object. */
111 * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
112 * Translation Table).
114 * Although each hardware context has its own VMA, we assign BO's to the
115 * same address in all contexts, for simplicity.
120 * If non-zero, then this bo has an aux-map translation to this address.
122 uint64_t aux_map_address
;
125 * The validation list index for this buffer, or -1 when not in a batch.
126 * Note that a single buffer may be in multiple batches (contexts), and
127 * this is a global field, which refers to the last batch using the BO.
128 * It should not be considered authoritative, but can be used to avoid a
129 * linear walk of the validation list in the common case by guessing that
130 * exec_bos[bo->index] == bo and confirming whether that's the case.
132 * XXX: this is not ideal now that we have more than one batch per context,
133 * XXX: as the index will flop back and forth between the render index and
134 * XXX: compute index...
144 * Kenel-assigned global name for this object
146 * List contains both flink named and prime fd'd objects
148 unsigned global_name
;
151 * Current tiling mode
153 uint32_t tiling_mode
;
154 uint32_t swizzle_mode
;
159 /** Mapped address for the buffer, saved across map/unmap cycles */
161 /** GTT virtual address for the buffer, saved across map/unmap cycles */
163 /** WC CPU address for the buffer, saved across map/unmap cycles */
167 struct list_head head
;
170 * Boolean of whether the GPU is definitely not accessing the buffer.
172 * This is only valid when reusable, since non-reusable
173 * buffers are those that have been shared with other
174 * processes, so we don't know their state.
179 * Boolean of whether this buffer can be re-used
184 * Boolean of whether this buffer has been shared with an external client.
189 * Boolean of whether this buffer is cache coherent
194 * Boolean of whether this buffer points into user memory
199 #define BO_ALLOC_ZEROED (1<<0)
200 #define BO_ALLOC_COHERENT (1<<1)
203 * Allocate a buffer object.
205 * Buffer objects are not necessarily initially mapped into CPU virtual
206 * address space or graphics device aperture. They must be mapped
207 * using iris_bo_map() to be used by the CPU.
209 struct iris_bo
*iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
212 enum iris_memory_zone memzone
);
215 * Allocate a tiled buffer object.
217 * Alignment for tiled objects is set automatically; the 'flags'
218 * argument provides a hint about how the object will be used initially.
220 * Valid tiling formats are:
225 struct iris_bo
*iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
,
229 enum iris_memory_zone memzone
,
230 uint32_t tiling_mode
,
235 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
236 void *ptr
, size_t size
,
237 enum iris_memory_zone memzone
);
239 /** Takes a reference on a buffer object */
241 iris_bo_reference(struct iris_bo
*bo
)
243 p_atomic_inc(&bo
->refcount
);
247 * Releases a reference on a buffer object, freeing the data if
248 * no references remain.
250 void iris_bo_unreference(struct iris_bo
*bo
);
252 #define MAP_READ PIPE_TRANSFER_READ
253 #define MAP_WRITE PIPE_TRANSFER_WRITE
254 #define MAP_ASYNC PIPE_TRANSFER_UNSYNCHRONIZED
255 #define MAP_PERSISTENT PIPE_TRANSFER_PERSISTENT
256 #define MAP_COHERENT PIPE_TRANSFER_COHERENT
258 #define MAP_INTERNAL_MASK (0xffu << 24)
259 #define MAP_RAW (0x01 << 24)
261 #define MAP_FLAGS (MAP_READ | MAP_WRITE | MAP_ASYNC | \
262 MAP_PERSISTENT | MAP_COHERENT | MAP_INTERNAL_MASK)
265 * Maps the buffer into userspace.
267 * This function will block waiting for any existing execution on the
268 * buffer to complete, first. The resulting mapping is returned.
270 MUST_CHECK
void *iris_bo_map(struct pipe_debug_callback
*dbg
,
271 struct iris_bo
*bo
, unsigned flags
);
274 * Reduces the refcount on the userspace mapping of the buffer
277 static inline int iris_bo_unmap(struct iris_bo
*bo
) { return 0; }
280 * Waits for rendering to an object by the GPU to have completed.
282 * This is not required for any access to the BO by bo_map,
283 * bo_subdata, etc. It is merely a way for the driver to implement
286 void iris_bo_wait_rendering(struct iris_bo
*bo
);
290 * Unref a buffer manager instance.
292 void iris_bufmgr_unref(struct iris_bufmgr
*bufmgr
);
295 * Get the current tiling (and resulting swizzling) mode for the bo.
297 * \param buf Buffer to get tiling mode for
298 * \param tiling_mode returned tiling mode
299 * \param swizzle_mode returned swizzling mode
301 int iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
302 uint32_t *swizzle_mode
);
305 * Create a visible name for a buffer which can be used by other apps
307 * \param buf Buffer to create a name for
308 * \param name Returned name
310 int iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
);
313 * Make a BO externally accessible.
315 * \param bo Buffer to make external
317 void iris_bo_make_external(struct iris_bo
*bo
);
320 * Returns 1 if mapping the buffer for write could cause the process
321 * to block, due to the object being active in the GPU.
323 int iris_bo_busy(struct iris_bo
*bo
);
326 * Specify the volatility of the buffer.
327 * \param bo Buffer to create a name for
328 * \param madv The purgeable status
330 * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
331 * reclaimed under memory pressure. If you subsequently require the buffer,
332 * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
334 * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
335 * marked as I915_MADV_DONTNEED.
337 int iris_bo_madvise(struct iris_bo
*bo
, int madv
);
339 /* drm_bacon_bufmgr_gem.c */
340 struct iris_bufmgr
*iris_bufmgr_get_for_fd(struct gen_device_info
*devinfo
, int fd
,
342 int iris_bufmgr_get_fd(struct iris_bufmgr
*bufmgr
);
344 struct iris_bo
*iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
348 void* iris_bufmgr_get_aux_map_context(struct iris_bufmgr
*bufmgr
);
350 int iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
);
352 uint32_t iris_create_hw_context(struct iris_bufmgr
*bufmgr
);
353 uint32_t iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
);
355 #define IRIS_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
356 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
357 #define IRIS_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
359 int iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
360 uint32_t ctx_id
, int priority
);
362 void iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
);
364 int iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
);
365 struct iris_bo
*iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
,
366 uint32_t tiling
, uint32_t stride
);
368 uint32_t iris_bo_export_gem_handle(struct iris_bo
*bo
);
370 int iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *out
);
372 int drm_ioctl(int fd
, unsigned long request
, void *arg
);
375 * Returns the BO's address relative to the appropriate base address.
377 * All of our base addresses are programmed to the start of a 4GB region,
378 * so simply returning the bottom 32 bits of the BO address will give us
379 * the offset from whatever base address corresponds to that memory region.
381 static inline uint32_t
382 iris_bo_offset_from_base_address(struct iris_bo
*bo
)
384 /* This only works for buffers in the memory zones corresponding to a
385 * base address - the top, unbounded memory zone doesn't have a base.
387 assert(bo
->gtt_offset
< IRIS_MEMZONE_OTHER_START
);
388 return bo
->gtt_offset
;
391 enum iris_memory_zone
iris_memzone_for_address(uint64_t address
);
393 #endif /* IRIS_BUFMGR_H */