src/gallium/drivers/iris/iris_bufmgr.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BUFMGR_H
  25 #define IRIS_BUFMGR_H
  26
  27 #include <stdbool.h>
  28 #include <stdint.h>
  29 #include <stdio.h>
  30 #include <sys/types.h>
  31 #include "util/macros.h"
  32 #include "util/u_atomic.h"
  33 #include "util/list.h"
  34 #include "pipe/p_defines.h"
  35
  36 struct iris_batch;
  37 struct gen_device_info;
  38 struct pipe_debug_callback;
  39
  40 /**
  41  * Memory zones.  When allocating a buffer, you can request that it is
  42  * placed into a specific region of the virtual address space (PPGTT).
  43  *
  44  * Most buffers can go anywhere (IRIS_MEMZONE_OTHER).  Some buffers are
  45  * accessed via an offset from a base address.  STATE_BASE_ADDRESS has
  46  * a maximum 4GB size for each region, so we need to restrict those
  47  * buffers to be within 4GB of the base.  Each memory zone corresponds
  48  * to a particular base address.
  49  *
  50  * We lay out the virtual address space as follows:
  51  *
  52  * - [0,   4K): Nothing            (empty page for null address)
  53  * - [4K,  4G): Shaders            (Instruction Base Address)
  54  * - [4G,  8G): Surfaces & Binders (Surface State Base Address, Bindless ...)
  55  * - [8G, 12G): Dynamic            (Dynamic State Base Address)
  56  * - [12G, *):  Other              (everything else in the full 48-bit VMA)
  57  *
  58  * A special buffer for border color lives at the start of the dynamic state
  59  * memory zone.  This unfortunately has to be handled specially because the
  60  * SAMPLER_STATE "Indirect State Pointer" field is only a 24-bit pointer.
  61  *
  62  * Each GL context uses a separate GEM context, which technically gives them
  63  * each a separate VMA.  However, we assign address globally, so buffers will
  64  * have the same address in all GEM contexts.  This lets us have a single BO
  65  * field for the address, which is easy and cheap.
  66  */
  67 enum iris_memory_zone {
  68    IRIS_MEMZONE_SHADER,
  69    IRIS_MEMZONE_BINDER,
  70    IRIS_MEMZONE_SURFACE,
  71    IRIS_MEMZONE_DYNAMIC,
  72    IRIS_MEMZONE_OTHER,
  73
  74    IRIS_MEMZONE_BORDER_COLOR_POOL,
  75 };
  76
  77 /* Intentionally exclude single buffer "zones" */
  78 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
  79
  80 #define IRIS_BINDER_SIZE (64 * 1024)
  81 #define IRIS_MAX_BINDERS 100
  82
  83 #define IRIS_MEMZONE_SHADER_START     (0ull * (1ull << 32))
  84 #define IRIS_MEMZONE_BINDER_START     (1ull * (1ull << 32))
  85 #define IRIS_MEMZONE_SURFACE_START    (IRIS_MEMZONE_BINDER_START + IRIS_MAX_BINDERS * IRIS_BINDER_SIZE)
  86 #define IRIS_MEMZONE_DYNAMIC_START    (2ull * (1ull << 32))
  87 #define IRIS_MEMZONE_OTHER_START      (3ull * (1ull << 32))
  88
  89 #define IRIS_BORDER_COLOR_POOL_ADDRESS IRIS_MEMZONE_DYNAMIC_START
  90 #define IRIS_BORDER_COLOR_POOL_SIZE (64 * 1024)
  91
  92 struct iris_bo {
  93    /**
  94     * Size in bytes of the buffer object.
  95     *
  96     * The size may be larger than the size originally requested for the
  97     * allocation, such as being aligned to page size.
  98     */
  99    uint64_t size;
 100
 101    /** Buffer manager context associated with this buffer object */
 102    struct iris_bufmgr *bufmgr;
 103
 104    /** The GEM handle for this buffer object. */
 105    uint32_t gem_handle;
 106
 107    /**
 108     * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
 109     * Translation Table).
 110     *
 111     * Although each hardware context has its own VMA, we assign BO's to the
 112     * same address in all contexts, for simplicity.
 113     */
 114    uint64_t gtt_offset;
 115
 116    /**
 117     * If non-zero, then this bo has an aux-map translation to this address.
 118     */
 119    uint64_t aux_map_address;
 120
 121    /**
 122     * The validation list index for this buffer, or -1 when not in a batch.
 123     * Note that a single buffer may be in multiple batches (contexts), and
 124     * this is a global field, which refers to the last batch using the BO.
 125     * It should not be considered authoritative, but can be used to avoid a
 126     * linear walk of the validation list in the common case by guessing that
 127     * exec_bos[bo->index] == bo and confirming whether that's the case.
 128     *
 129     * XXX: this is not ideal now that we have more than one batch per context,
 130     * XXX: as the index will flop back and forth between the render index and
 131     * XXX: compute index...
 132     */
 133    unsigned index;
 134
 135    /**
 136     * Boolean of whether the GPU is definitely not accessing the buffer.
 137     *
 138     * This is only valid when reusable, since non-reusable
 139     * buffers are those that have been shared with other
 140     * processes, so we don't know their state.
 141     */
 142    bool idle;
 143
 144    int refcount;
 145    const char *name;
 146
 147    uint64_t kflags;
 148
 149    /**
 150     * Kenel-assigned global name for this object
 151     *
 152     * List contains both flink named and prime fd'd objects
 153     */
 154    unsigned global_name;
 155
 156    /**
 157     * Current tiling mode
 158     */
 159    uint32_t tiling_mode;
 160    uint32_t swizzle_mode;
 161    uint32_t stride;
 162
 163    time_t free_time;
 164
 165    /** Mapped address for the buffer, saved across map/unmap cycles */
 166    void *map_cpu;
 167    /** GTT virtual address for the buffer, saved across map/unmap cycles */
 168    void *map_gtt;
 169    /** WC CPU address for the buffer, saved across map/unmap cycles */
 170    void *map_wc;
 171
 172    /** BO cache list */
 173    struct list_head head;
 174
 175    /**
 176     * Boolean of whether this buffer can be re-used
 177     */
 178    bool reusable;
 179
 180    /**
 181     * Boolean of whether this buffer has been shared with an external client.
 182     */
 183    bool external;
 184
 185    /**
 186     * Boolean of whether this buffer is cache coherent
 187     */
 188    bool cache_coherent;
 189
 190    /**
 191     * Boolean of whether this buffer points into user memory
 192     */
 193    bool userptr;
 194
 195    /** Pre-computed hash using _mesa_hash_pointer for cache tracking sets */
 196    uint32_t hash;
 197 };
 198
 199 #define BO_ALLOC_ZEROED     (1<<0)
 200 #define BO_ALLOC_COHERENT   (1<<1)
 201
 202 /**
 203  * Allocate a buffer object.
 204  *
 205  * Buffer objects are not necessarily initially mapped into CPU virtual
 206  * address space or graphics device aperture.  They must be mapped
 207  * using iris_bo_map() to be used by the CPU.
 208  */
 209 struct iris_bo *iris_bo_alloc(struct iris_bufmgr *bufmgr,
 210                               const char *name,
 211                               uint64_t size,
 212                               enum iris_memory_zone memzone);
 213
 214 /**
 215  * Allocate a tiled buffer object.
 216  *
 217  * Alignment for tiled objects is set automatically; the 'flags'
 218  * argument provides a hint about how the object will be used initially.
 219  *
 220  * Valid tiling formats are:
 221  *  I915_TILING_NONE
 222  *  I915_TILING_X
 223  *  I915_TILING_Y
 224  */
 225 struct iris_bo *iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr,
 226                                     const char *name,
 227                                     uint64_t size,
 228                                     uint32_t alignment,
 229                                     enum iris_memory_zone memzone,
 230                                     uint32_t tiling_mode,
 231                                     uint32_t pitch,
 232                                     unsigned flags);
 233
 234 struct iris_bo *
 235 iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
 236                        void *ptr, size_t size,
 237                        enum iris_memory_zone memzone);
 238
 239 /** Takes a reference on a buffer object */
 240 static inline void
 241 iris_bo_reference(struct iris_bo *bo)
 242 {
 243    p_atomic_inc(&bo->refcount);
 244 }
 245
 246 /**
 247  * Releases a reference on a buffer object, freeing the data if
 248  * no references remain.
 249  */
 250 void iris_bo_unreference(struct iris_bo *bo);
 251
 252 #define MAP_READ          PIPE_TRANSFER_READ
 253 #define MAP_WRITE         PIPE_TRANSFER_WRITE
 254 #define MAP_ASYNC         PIPE_TRANSFER_UNSYNCHRONIZED
 255 #define MAP_PERSISTENT    PIPE_TRANSFER_PERSISTENT
 256 #define MAP_COHERENT      PIPE_TRANSFER_COHERENT
 257 /* internal */
 258 #define MAP_INTERNAL_MASK (0xffu << 24)
 259 #define MAP_RAW           (0x01 << 24)
 260
 261 #define MAP_FLAGS         (MAP_READ | MAP_WRITE | MAP_ASYNC | \
 262                            MAP_PERSISTENT | MAP_COHERENT | MAP_INTERNAL_MASK)
 263
 264 /**
 265  * Maps the buffer into userspace.
 266  *
 267  * This function will block waiting for any existing execution on the
 268  * buffer to complete, first.  The resulting mapping is returned.
 269  */
 270 MUST_CHECK void *iris_bo_map(struct pipe_debug_callback *dbg,
 271                              struct iris_bo *bo, unsigned flags);
 272
 273 /**
 274  * Reduces the refcount on the userspace mapping of the buffer
 275  * object.
 276  */
 277 static inline int iris_bo_unmap(struct iris_bo *bo) { return 0; }
 278
 279 /**
 280  * Waits for rendering to an object by the GPU to have completed.
 281  *
 282  * This is not required for any access to the BO by bo_map,
 283  * bo_subdata, etc.  It is merely a way for the driver to implement
 284  * glFinish.
 285  */
 286 void iris_bo_wait_rendering(struct iris_bo *bo);
 287
 288 /**
 289  * Tears down the buffer manager instance.
 290  */
 291 void iris_bufmgr_destroy(struct iris_bufmgr *bufmgr);
 292
 293 /**
 294  * Get the current tiling (and resulting swizzling) mode for the bo.
 295  *
 296  * \param buf Buffer to get tiling mode for
 297  * \param tiling_mode returned tiling mode
 298  * \param swizzle_mode returned swizzling mode
 299  */
 300 int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
 301                       uint32_t *swizzle_mode);
 302
 303 /**
 304  * Create a visible name for a buffer which can be used by other apps
 305  *
 306  * \param buf Buffer to create a name for
 307  * \param name Returned name
 308  */
 309 int iris_bo_flink(struct iris_bo *bo, uint32_t *name);
 310
 311 /**
 312  * Returns 1 if mapping the buffer for write could cause the process
 313  * to block, due to the object being active in the GPU.
 314  */
 315 int iris_bo_busy(struct iris_bo *bo);
 316
 317 /**
 318  * Specify the volatility of the buffer.
 319  * \param bo Buffer to create a name for
 320  * \param madv The purgeable status
 321  *
 322  * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
 323  * reclaimed under memory pressure. If you subsequently require the buffer,
 324  * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
 325  *
 326  * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
 327  * marked as I915_MADV_DONTNEED.
 328  */
 329 int iris_bo_madvise(struct iris_bo *bo, int madv);
 330
 331 /* drm_bacon_bufmgr_gem.c */
 332 struct iris_bufmgr *iris_bufmgr_init(struct gen_device_info *devinfo, int fd,
 333                                      bool bo_reuse);
 334 struct iris_bo *iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr,
 335                                              const char *name,
 336                                              unsigned handle);
 337
 338 void* iris_bufmgr_get_aux_map_context(struct iris_bufmgr *bufmgr);
 339
 340 int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns);
 341
 342 uint32_t iris_create_hw_context(struct iris_bufmgr *bufmgr);
 343 uint32_t iris_clone_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 344
 345 #define IRIS_CONTEXT_LOW_PRIORITY    ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 346 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
 347 #define IRIS_CONTEXT_HIGH_PRIORITY   ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
 348
 349 int iris_hw_context_set_priority(struct iris_bufmgr *bufmgr,
 350                                  uint32_t ctx_id, int priority);
 351
 352 void iris_destroy_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 353
 354 int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd);
 355 struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd,
 356                                       uint32_t tiling, uint32_t stride);
 357
 358 uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
 359
 360 int iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *out);
 361
 362 int drm_ioctl(int fd, unsigned long request, void *arg);
 363
 364 /**
 365  * Returns the BO's address relative to the appropriate base address.
 366  *
 367  * All of our base addresses are programmed to the start of a 4GB region,
 368  * so simply returning the bottom 32 bits of the BO address will give us
 369  * the offset from whatever base address corresponds to that memory region.
 370  */
 371 static inline uint32_t
 372 iris_bo_offset_from_base_address(struct iris_bo *bo)
 373 {
 374    /* This only works for buffers in the memory zones corresponding to a
 375     * base address - the top, unbounded memory zone doesn't have a base.
 376     */
 377    assert(bo->gtt_offset < IRIS_MEMZONE_OTHER_START);
 378    return bo->gtt_offset;
 379 }
 380
 381 enum iris_memory_zone iris_memzone_for_address(uint64_t address);
 382
 383 #endif /* IRIS_BUFMGR_H */