src/gallium/drivers/iris/iris_bufmgr.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BUFMGR_H
  25 #define IRIS_BUFMGR_H
  26
  27 #include <stdbool.h>
  28 #include <stdint.h>
  29 #include <stdio.h>
  30 #include <sys/types.h>
  31 #include "util/macros.h"
  32 #include "util/u_atomic.h"
  33 #include "util/list.h"
  34 #include "pipe/p_defines.h"
  35
  36 struct gen_device_info;
  37 struct pipe_debug_callback;
  38
  39 /**
  40  * Memory zones.  When allocating a buffer, you can request that it is
  41  * placed into a specific region of the virtual address space (PPGTT).
  42  *
  43  * Most buffers can go anywhere (IRIS_MEMZONE_OTHER).  Some buffers are
  44  * accessed via an offset from a base address.  STATE_BASE_ADDRESS has
  45  * a maximum 4GB size for each region, so we need to restrict those
  46  * buffers to be within 4GB of the base.  Each memory zone corresponds
  47  * to a particular base address.
  48  *
  49  * We lay out the virtual address space as follows:
  50  *
  51  * - [0,   4K): Nothing  (empty page for null address)
  52  * - [4K,  4G): Shaders  (Instruction Base Address)
  53  * - [4G,  8G): Surfaces (Surface State Base Address, Bindless ...)
  54  * - [8G, 12G): Dynamic  (Dynamic State Base Address)
  55  * - [12G, *):  Other    (everything else in the full 48-bit VMA)
  56  *
  57  * A special 64kB "binder" buffer lives at the start of the surface memory
  58  * zone, holding binding tables referring to objects in the rest of the zone.
  59  *
  60  * Each GL context uses a separate GEM context, which technically gives them
  61  * each a separate VMA.  However, we assign address globally, so buffers will
  62  * have the same address in all GEM contexts.  This lets us have a single BO
  63  * field for the address, which is easy and cheap.
  64  *
  65  * One exception is the special "binder" BO.  Binders are context-local,
  66  * so while there are many of them, all binders are stored at the same
  67  * fixed address (in different VMAs).
  68  */
  69 enum iris_memory_zone {
  70    IRIS_MEMZONE_SHADER,
  71    IRIS_MEMZONE_SURFACE,
  72    IRIS_MEMZONE_DYNAMIC,
  73    IRIS_MEMZONE_OTHER,
  74
  75    IRIS_MEMZONE_BINDER,
  76 };
  77
  78 /* Intentionally exclude IRIS_MEMZONE_BINDER */
  79 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
  80
  81 #define IRIS_MEMZONE_SHADER_START     (0ull * (1ull << 32))
  82 #define IRIS_MEMZONE_SURFACE_START    (1ull * (1ull << 32))
  83 #define IRIS_MEMZONE_DYNAMIC_START    (2ull * (1ull << 32))
  84 #define IRIS_MEMZONE_OTHER_START      (3ull * (1ull << 32))
  85
  86 #define IRIS_BINDER_ADDRESS IRIS_MEMZONE_SURFACE_START
  87
  88 struct iris_bo {
  89    /**
  90     * Size in bytes of the buffer object.
  91     *
  92     * The size may be larger than the size originally requested for the
  93     * allocation, such as being aligned to page size.
  94     */
  95    uint64_t size;
  96
  97    /** Buffer manager context associated with this buffer object */
  98    struct iris_bufmgr *bufmgr;
  99
 100    /** The GEM handle for this buffer object. */
 101    uint32_t gem_handle;
 102
 103    /**
 104     * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
 105     * Translation Table).
 106     *
 107     * Although each hardware context has its own VMA, we assign BO's to the
 108     * same address in all contexts, for simplicity.
 109     */
 110    uint64_t gtt_offset;
 111
 112    /**
 113     * The validation list index for this buffer, or -1 when not in a batch.
 114     * Note that a single buffer may be in multiple batches (contexts), and
 115     * this is a global field, which refers to the last batch using the BO.
 116     * It should not be considered authoritative, but can be used to avoid a
 117     * linear walk of the validation list in the common case by guessing that
 118     * exec_bos[bo->index] == bo and confirming whether that's the case.
 119     */
 120    unsigned index;
 121
 122    /**
 123     * Boolean of whether the GPU is definitely not accessing the buffer.
 124     *
 125     * This is only valid when reusable, since non-reusable
 126     * buffers are those that have been shared with other
 127     * processes, so we don't know their state.
 128     */
 129    bool idle;
 130
 131    int refcount;
 132    const char *name;
 133
 134    uint64_t kflags;
 135
 136    /**
 137     * Kenel-assigned global name for this object
 138     *
 139     * List contains both flink named and prime fd'd objects
 140     */
 141    unsigned global_name;
 142
 143    /**
 144     * Current tiling mode
 145     */
 146    uint32_t tiling_mode;
 147    uint32_t swizzle_mode;
 148    uint32_t stride;
 149
 150    time_t free_time;
 151
 152    /** Mapped address for the buffer, saved across map/unmap cycles */
 153    void *map_cpu;
 154    /** GTT virtual address for the buffer, saved across map/unmap cycles */
 155    void *map_gtt;
 156    /** WC CPU address for the buffer, saved across map/unmap cycles */
 157    void *map_wc;
 158
 159    /** BO cache list */
 160    struct list_head head;
 161
 162    /**
 163     * Boolean of whether this buffer can be re-used
 164     */
 165    bool reusable;
 166
 167    /**
 168     * Boolean of whether this buffer has been shared with an external client.
 169     */
 170    bool external;
 171
 172    /**
 173     * Boolean of whether this buffer is cache coherent
 174     */
 175    bool cache_coherent;
 176 };
 177
 178 #define BO_ALLOC_ZEROED     (1<<0)
 179
 180 /**
 181  * Allocate a buffer object.
 182  *
 183  * Buffer objects are not necessarily initially mapped into CPU virtual
 184  * address space or graphics device aperture.  They must be mapped
 185  * using iris_bo_map() to be used by the CPU.
 186  */
 187 struct iris_bo *iris_bo_alloc(struct iris_bufmgr *bufmgr,
 188                               const char *name,
 189                               uint64_t size,
 190                               enum iris_memory_zone memzone);
 191
 192 /**
 193  * Allocate a tiled buffer object.
 194  *
 195  * Alignment for tiled objects is set automatically; the 'flags'
 196  * argument provides a hint about how the object will be used initially.
 197  *
 198  * Valid tiling formats are:
 199  *  I915_TILING_NONE
 200  *  I915_TILING_X
 201  *  I915_TILING_Y
 202  */
 203 struct iris_bo *iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr,
 204                                     const char *name,
 205                                     uint64_t size,
 206                                     uint32_t tiling_mode,
 207                                     uint32_t pitch,
 208                                     unsigned flags,
 209                                     enum iris_memory_zone memzone);
 210
 211 /** Takes a reference on a buffer object */
 212 static inline void
 213 iris_bo_reference(struct iris_bo *bo)
 214 {
 215    p_atomic_inc(&bo->refcount);
 216 }
 217
 218 /**
 219  * Releases a reference on a buffer object, freeing the data if
 220  * no references remain.
 221  */
 222 void iris_bo_unreference(struct iris_bo *bo);
 223
 224 #define MAP_READ          PIPE_TRANSFER_READ
 225 #define MAP_WRITE         PIPE_TRANSFER_WRITE
 226 #define MAP_ASYNC         PIPE_TRANSFER_UNSYNCHRONIZED
 227 #define MAP_PERSISTENT    PIPE_TRANSFER_PERSISTENT
 228 #define MAP_COHERENT      PIPE_TRANSFER_COHERENT
 229 /* internal */
 230 #define MAP_INTERNAL_MASK (0xff << 24)
 231 #define MAP_RAW           (0x01 << 24)
 232
 233 /**
 234  * Maps the buffer into userspace.
 235  *
 236  * This function will block waiting for any existing execution on the
 237  * buffer to complete, first.  The resulting mapping is returned.
 238  */
 239 MUST_CHECK void *iris_bo_map(struct pipe_debug_callback *dbg,
 240                              struct iris_bo *bo, unsigned flags);
 241
 242 /**
 243  * Reduces the refcount on the userspace mapping of the buffer
 244  * object.
 245  */
 246 static inline int iris_bo_unmap(struct iris_bo *bo) { return 0; }
 247
 248 /** Write data into an object. */
 249 int iris_bo_subdata(struct iris_bo *bo, uint64_t offset,
 250                    uint64_t size, const void *data);
 251 /**
 252  * Waits for rendering to an object by the GPU to have completed.
 253  *
 254  * This is not required for any access to the BO by bo_map,
 255  * bo_subdata, etc.  It is merely a way for the driver to implement
 256  * glFinish.
 257  */
 258 void iris_bo_wait_rendering(struct iris_bo *bo);
 259
 260 /**
 261  * Tears down the buffer manager instance.
 262  */
 263 void iris_bufmgr_destroy(struct iris_bufmgr *bufmgr);
 264
 265 /**
 266  * Get the current tiling (and resulting swizzling) mode for the bo.
 267  *
 268  * \param buf Buffer to get tiling mode for
 269  * \param tiling_mode returned tiling mode
 270  * \param swizzle_mode returned swizzling mode
 271  */
 272 int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
 273                       uint32_t *swizzle_mode);
 274
 275 /**
 276  * Create a visible name for a buffer which can be used by other apps
 277  *
 278  * \param buf Buffer to create a name for
 279  * \param name Returned name
 280  */
 281 int iris_bo_flink(struct iris_bo *bo, uint32_t *name);
 282
 283 /**
 284  * Returns 1 if mapping the buffer for write could cause the process
 285  * to block, due to the object being active in the GPU.
 286  */
 287 int iris_bo_busy(struct iris_bo *bo);
 288
 289 /**
 290  * Specify the volatility of the buffer.
 291  * \param bo Buffer to create a name for
 292  * \param madv The purgeable status
 293  *
 294  * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
 295  * reclaimed under memory pressure. If you subsequently require the buffer,
 296  * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
 297  *
 298  * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
 299  * marked as I915_MADV_DONTNEED.
 300  */
 301 int iris_bo_madvise(struct iris_bo *bo, int madv);
 302
 303 /* drm_bacon_bufmgr_gem.c */
 304 struct iris_bufmgr *iris_bufmgr_init(struct gen_device_info *devinfo, int fd);
 305 struct iris_bo *iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr,
 306                                              const char *name,
 307                                              unsigned handle);
 308 void iris_bufmgr_enable_reuse(struct iris_bufmgr *bufmgr);
 309
 310 int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns);
 311
 312 uint32_t iris_create_hw_context(struct iris_bufmgr *bufmgr);
 313
 314 #define IRIS_CONTEXT_LOW_PRIORITY    ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 315 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
 316 #define IRIS_CONTEXT_HIGH_PRIORITY   ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
 317
 318 int iris_hw_context_set_priority(struct iris_bufmgr *bufmgr,
 319                                  uint32_t ctx_id, int priority);
 320
 321 void iris_destroy_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 322
 323 int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd);
 324 struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd);
 325
 326 uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
 327
 328 int iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *out);
 329
 330 int drm_ioctl(int fd, unsigned long request, void *arg);
 331
 332 /**
 333  * Returns the BO's address relative to the appropriate base address.
 334  *
 335  * All of our base addresses are programmed to the start of a 4GB region,
 336  * so simply returning the bottom 32 bits of the BO address will give us
 337  * the offset from whatever base address corresponds to that memory region.
 338  */
 339 static inline uint32_t
 340 iris_bo_offset_from_base_address(struct iris_bo *bo)
 341 {
 342    /* This only works for buffers in the memory zones corresponding to a
 343     * base address - the top, unbounded memory zone doesn't have a base.
 344     */
 345    assert(bo->gtt_offset < IRIS_MEMZONE_OTHER_START);
 346    return bo->gtt_offset;
 347 }
 348
 349 #endif /* IRIS_BUFMGR_H */