2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
79 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
81 /* XXX: Need to fix channel select for gen8 before enabling this. */
82 if (devinfo
->gen
!= 9)
85 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
88 /* Surface state can only record one fast clear color value. Therefore
89 * unless different levels/layers agree on the color it can be used to
90 * represent only single level/layer. Here it will be reserved for the
91 * first slice (level 0, layer 0).
93 if (level
> 0 || box
->z
> 0 || box
->depth
> 1)
96 /* Check for partial clear */
97 if (box
->x
> 0 || box
->y
> 0 ||
98 box
->width
< p_res
->width0
||
99 box
->height
< p_res
->height0
) {
103 /* We store clear colors as floats or uints as needed. If there are
104 * texture views in play, the formats will not properly be respected
105 * during resolves because the resolve operations only know about the
106 * resource and not the renderbuffer.
108 if (render_format
!= format
)
111 /* XXX: if (irb->mt->supports_fast_clear)
112 * see intel_miptree_create_for_dri_image()
115 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
121 static union isl_color_value
122 convert_fast_clear_color(struct iris_context
*ice
,
123 struct iris_resource
*res
,
124 const union isl_color_value color
)
126 union isl_color_value override_color
= color
;
127 struct pipe_resource
*p_res
= (void *) res
;
129 const enum pipe_format format
= p_res
->format
;
130 const struct util_format_description
*desc
=
131 util_format_description(format
);
132 unsigned colormask
= util_format_colormask(desc
);
134 if (util_format_is_intensity(format
) ||
135 util_format_is_luminance(format
) ||
136 util_format_is_luminance_alpha(format
)) {
137 override_color
.u32
[1] = override_color
.u32
[0];
138 override_color
.u32
[2] = override_color
.u32
[0];
139 if (util_format_is_intensity(format
))
140 override_color
.u32
[3] = override_color
.u32
[0];
142 for (int chan
= 0; chan
< 3; chan
++) {
143 if (!(colormask
& (1 << chan
)))
144 override_color
.u32
[chan
] = 0;
148 if (util_format_is_unorm(format
)) {
149 for (int i
= 0; i
< 4; i
++)
150 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
151 } else if (util_format_is_snorm(format
)) {
152 for (int i
= 0; i
< 4; i
++)
153 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
154 } else if (util_format_is_pure_uint(format
)) {
155 for (int i
= 0; i
< 4; i
++) {
156 unsigned bits
= util_format_get_component_bits(
157 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
159 uint32_t max
= (1u << bits
) - 1;
160 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
163 } else if (util_format_is_pure_sint(format
)) {
164 for (int i
= 0; i
< 4; i
++) {
165 unsigned bits
= util_format_get_component_bits(
166 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
168 int32_t max
= (1 << (bits
- 1)) - 1;
169 int32_t min
= -(1 << (bits
- 1));
170 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
173 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
174 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
175 /* these packed float formats only store unsigned values */
176 for (int i
= 0; i
< 4; i
++)
177 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
180 if (!(colormask
& 1 << 3)) {
181 if (util_format_is_pure_integer(format
))
182 override_color
.u32
[3] = 1;
184 override_color
.f32
[3] = 1.0f
;
187 /* Handle linear to SRGB conversion */
188 if (util_format_is_srgb(format
)) {
189 for (int i
= 0; i
< 3; i
++) {
190 override_color
.f32
[i
] =
191 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
195 return override_color
;
199 fast_clear_color(struct iris_context
*ice
,
200 struct iris_resource
*res
,
202 const struct pipe_box
*box
,
203 enum isl_format format
,
204 union isl_color_value color
,
205 enum blorp_batch_flags blorp_flags
)
207 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
208 struct pipe_resource
*p_res
= (void *) res
;
209 const enum isl_aux_state aux_state
=
210 iris_resource_get_aux_state(res
, level
, box
->z
);
212 color
= convert_fast_clear_color(ice
, res
, color
);
214 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
218 /* We decided that we are going to fast clear, and the color is
219 * changing. But if we have a predicate bit set, the predication
220 * affects whether we should clear or not, and if we shouldn't, we
221 * also shouldn't update the clear color.
223 * However, we can't simply predicate-update the clear color (the
224 * commands don't support that). And we would lose track of the
225 * color, preventing us from doing some optimizations later.
227 * Since changing the clear color when the predication bit is enabled
228 * is not something that should happen often, we stall on the CPU here
229 * to resolve the predication, and then proceed.
231 iris_resolve_conditional_render(ice
);
232 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
236 iris_resource_set_clear_color(ice
, res
, color
);
238 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
239 * changed, the clear is redundant and can be skipped.
241 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
244 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
246 * "Any transition from any value in {Clear, Render, Resolve} to a
247 * different value in {Clear, Render, Resolve} requires end of pipe
250 * In other words, fast clear ops are not properly synchronized with
251 * other drawing. We need to use a PIPE_CONTROL to ensure that the
252 * contents of the previous draw hit the render target before we resolve
253 * and again afterwards to ensure that the resolve is complete before we
254 * do any more regular drawing.
256 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
258 /* If we reach this point, we need to fast clear to change the state to
259 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
261 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
263 struct blorp_batch blorp_batch
;
264 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
266 struct blorp_surf surf
;
267 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
270 blorp_fast_clear(&blorp_batch
, &surf
, format
,
271 level
, box
->z
, box
->depth
,
272 box
->x
, box
->y
, box
->x
+ box
->width
,
273 box
->y
+ box
->height
);
274 blorp_batch_finish(&blorp_batch
);
275 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
277 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
278 box
->depth
, ISL_AUX_STATE_CLEAR
);
279 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
284 clear_color(struct iris_context
*ice
,
285 struct pipe_resource
*p_res
,
287 const struct pipe_box
*box
,
288 bool render_condition_enabled
,
289 enum isl_format format
,
290 struct isl_swizzle swizzle
,
291 union isl_color_value color
)
293 struct iris_resource
*res
= (void *) p_res
;
295 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
296 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
297 enum blorp_batch_flags blorp_flags
= 0;
299 if (render_condition_enabled
) {
300 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
303 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
304 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
307 iris_batch_maybe_flush(batch
, 1500);
309 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
310 res
->surf
.format
, format
, color
);
311 if (can_fast_clear
) {
312 fast_clear_color(ice
, res
, level
, box
, format
, color
,
317 bool color_write_disable
[4] = { false, false, false, false };
318 enum isl_aux_usage aux_usage
=
319 iris_resource_render_aux_usage(ice
, res
, format
,
322 iris_resource_prepare_render(ice
, batch
, res
, level
,
323 box
->z
, box
->depth
, aux_usage
);
325 struct blorp_surf surf
;
326 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
329 struct blorp_batch blorp_batch
;
330 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
332 if (!isl_format_supports_rendering(devinfo
, format
) &&
333 isl_format_is_rgbx(format
))
334 format
= isl_format_rgbx_to_rgba(format
);
336 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
337 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
338 box
->x
+ box
->width
, box
->y
+ box
->height
,
339 color
, color_write_disable
);
341 blorp_batch_finish(&blorp_batch
);
342 iris_flush_and_dirty_for_history(ice
, batch
, res
);
344 iris_resource_finish_render(ice
, res
, level
,
345 box
->z
, box
->depth
, aux_usage
);
349 can_fast_clear_depth(struct iris_context
*ice
,
350 struct iris_resource
*res
,
352 const struct pipe_box
*box
,
355 struct pipe_resource
*p_res
= (void *) res
;
357 /* Check for partial clears */
358 if (box
->x
> 0 || box
->y
> 0 ||
359 box
->width
< u_minify(p_res
->width0
, level
) ||
360 box
->height
< u_minify(p_res
->height0
, level
)) {
364 if (!(res
->aux
.has_hiz
& (1 << level
)))
371 fast_clear_depth(struct iris_context
*ice
,
372 struct iris_resource
*res
,
374 const struct pipe_box
*box
,
377 struct pipe_resource
*p_res
= (void *) res
;
378 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
380 /* Quantize the clear value to what can be stored in the actual depth
381 * buffer. This makes the following check more accurate because it now
382 * checks if the actual depth bits will match. It also prevents us from
383 * getting a too-accurate depth value during depth testing or when sampling
386 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
387 const uint32_t depth_max
= (1 << nbits
) - 1;
388 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
389 (unsigned)(depth
* depth_max
) / (float)depth_max
;
391 bool update_clear_depth
= false;
393 /* If we're clearing to a new clear value, then we need to resolve any clear
394 * flags out of the HiZ buffer into the real depth buffer.
396 if (res
->aux
.clear_color
.f32
[0] != depth
) {
397 /* We decided that we are going to fast clear, and the color is
398 * changing. But if we have a predicate bit set, the predication
399 * affects whether we should clear or not, and if we shouldn't, we
400 * also shouldn't update the clear color.
402 * However, we can't simply predicate-update the clear color (the
403 * commands don't support that). And we would lose track of the
404 * color, preventing us from doing some optimizations later.
406 * For depth clears, things are even more complicated, because here we
407 * resolve the other levels/layers if they have a different color than
408 * the current one. That resolve can be predicated, but we also set those
409 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
410 * Keeping track of the aux state when predication is involved is just
411 * even more complex, so the easiest thing to do when the fast clear
412 * depth is changing is to stall on the CPU and resolve the predication.
414 iris_resolve_conditional_render(ice
);
415 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
418 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
419 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
422 const unsigned level_layers
=
423 iris_get_num_logical_layers(res
, res_level
);
424 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
425 if (res_level
== level
&&
427 layer
< box
->z
+ box
->depth
) {
428 /* We're going to clear this layer anyway. Leave it alone. */
432 enum isl_aux_state aux_state
=
433 iris_resource_get_aux_state(res
, res_level
, layer
);
435 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
436 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
437 /* This slice doesn't have any fast-cleared bits. */
441 /* If we got here, then the level may have fast-clear bits that
442 * use the old clear value. We need to do a depth resolve to get
443 * rid of their use of the clear value before we can change it.
444 * Fortunately, few applications ever change their depth clear
445 * value so this shouldn't happen often.
447 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
448 ISL_AUX_OP_FULL_RESOLVE
, false);
449 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
450 ISL_AUX_STATE_RESOLVED
);
453 const union isl_color_value clear_value
= { .f32
= {depth
, } };
454 iris_resource_set_clear_color(ice
, res
, clear_value
);
455 update_clear_depth
= true;
458 for (unsigned l
= 0; l
< box
->depth
; l
++) {
459 enum isl_aux_state aux_state
=
460 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
461 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
462 iris_hiz_exec(ice
, batch
, res
, level
,
463 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
468 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
469 ISL_AUX_STATE_CLEAR
);
470 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
474 clear_depth_stencil(struct iris_context
*ice
,
475 struct pipe_resource
*p_res
,
477 const struct pipe_box
*box
,
478 bool render_condition_enabled
,
484 struct iris_resource
*res
= (void *) p_res
;
486 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
487 enum blorp_batch_flags blorp_flags
= 0;
489 if (render_condition_enabled
) {
490 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
493 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
494 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
497 iris_batch_maybe_flush(batch
, 1500);
499 struct iris_resource
*z_res
;
500 struct iris_resource
*stencil_res
;
501 struct blorp_surf z_surf
;
502 struct blorp_surf stencil_surf
;
504 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
505 if (z_res
&& clear_depth
&&
506 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
507 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
508 iris_flush_and_dirty_for_history(ice
, batch
, res
);
513 /* At this point, we might have fast cleared the depth buffer. So if there's
514 * no stencil clear pending, return early.
516 if (!(clear_depth
|| clear_stencil
)) {
521 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
522 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
523 z_res
->aux
.usage
, level
, true);
526 struct blorp_batch blorp_batch
;
527 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
530 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
531 &stencil_res
->base
, stencil_res
->aux
.usage
,
535 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
536 level
, box
->z
, box
->depth
,
539 box
->y
+ box
->height
,
540 clear_depth
&& z_res
, depth
,
541 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
543 blorp_batch_finish(&blorp_batch
);
544 iris_flush_and_dirty_for_history(ice
, batch
, res
);
547 iris_resource_finish_depth(ice
, z_res
, level
,
548 box
->z
, box
->depth
, true);
553 * The pipe->clear() driver hook.
555 * This clears buffers attached to the current draw framebuffer.
558 iris_clear(struct pipe_context
*ctx
,
560 const union pipe_color_union
*p_color
,
564 struct iris_context
*ice
= (void *) ctx
;
565 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
567 assert(buffers
!= 0);
569 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
570 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
571 struct pipe_box box
= {
572 .width
= cso_fb
->width
,
573 .height
= cso_fb
->height
,
574 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
575 .z
= psurf
->u
.tex
.first_layer
,
578 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
579 buffers
& PIPE_CLEAR_DEPTH
,
580 buffers
& PIPE_CLEAR_STENCIL
,
584 if (buffers
& PIPE_CLEAR_COLOR
) {
585 /* pipe_color_union and isl_color_value are interchangeable */
586 union isl_color_value
*color
= (void *) p_color
;
588 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
589 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
590 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
591 struct iris_surface
*isurf
= (void *) psurf
;
592 struct pipe_box box
= {
593 .width
= cso_fb
->width
,
594 .height
= cso_fb
->height
,
595 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
596 .z
= psurf
->u
.tex
.first_layer
,
599 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
600 true, isurf
->view
.format
, isurf
->view
.swizzle
,
608 * The pipe->clear_texture() driver hook.
610 * This clears the given texture resource.
613 iris_clear_texture(struct pipe_context
*ctx
,
614 struct pipe_resource
*p_res
,
616 const struct pipe_box
*box
,
619 struct iris_context
*ice
= (void *) ctx
;
620 struct iris_screen
*screen
= (void *) ctx
->screen
;
621 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
623 if (util_format_is_depth_or_stencil(p_res
->format
)) {
624 const struct util_format_description
*fmt_desc
=
625 util_format_description(p_res
->format
);
630 if (fmt_desc
->unpack_z_float
)
631 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
633 if (fmt_desc
->unpack_s_8uint
)
634 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
636 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
639 union isl_color_value color
;
640 struct iris_resource
*res
= (void *) p_res
;
641 enum isl_format format
= res
->surf
.format
;
643 if (!isl_format_supports_rendering(devinfo
, format
)) {
644 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
645 // XXX: actually just get_copy_format_for_bpb from BLORP
646 // XXX: don't cut and paste this
648 case 8: format
= ISL_FORMAT_R8_UINT
; break;
649 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
650 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
651 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
652 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
653 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
654 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
655 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
657 unreachable("Unknown format bpb");
660 /* No aux surfaces for non-renderable surfaces */
661 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
664 isl_color_value_unpack(&color
, format
, data
);
666 clear_color(ice
, p_res
, level
, box
, true, format
,
667 ISL_SWIZZLE_IDENTITY
, color
);
672 * The pipe->clear_render_target() driver hook.
674 * This clears the given render target surface.
677 iris_clear_render_target(struct pipe_context
*ctx
,
678 struct pipe_surface
*psurf
,
679 const union pipe_color_union
*p_color
,
680 unsigned dst_x
, unsigned dst_y
,
681 unsigned width
, unsigned height
,
682 bool render_condition_enabled
)
684 struct iris_context
*ice
= (void *) ctx
;
685 struct iris_surface
*isurf
= (void *) psurf
;
686 struct pipe_box box
= {
689 .z
= psurf
->u
.tex
.first_layer
,
692 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
695 /* pipe_color_union and isl_color_value are interchangeable */
696 union isl_color_value
*color
= (void *) p_color
;
698 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
699 render_condition_enabled
,
700 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
704 * The pipe->clear_depth_stencil() driver hook.
706 * This clears the given depth/stencil surface.
709 iris_clear_depth_stencil(struct pipe_context
*ctx
,
710 struct pipe_surface
*psurf
,
714 unsigned dst_x
, unsigned dst_y
,
715 unsigned width
, unsigned height
,
716 bool render_condition_enabled
)
718 struct iris_context
*ice
= (void *) ctx
;
719 struct pipe_box box
= {
722 .z
= psurf
->u
.tex
.first_layer
,
725 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
728 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
730 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
731 render_condition_enabled
,
732 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
737 iris_init_clear_functions(struct pipe_context
*ctx
)
739 ctx
->clear
= iris_clear
;
740 ctx
->clear_texture
= iris_clear_texture
;
741 ctx
->clear_render_target
= iris_clear_render_target
;
742 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;