2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
39 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
40 enum isl_format format
,
41 const union isl_color_value color
)
43 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
44 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
46 if (isl_format_has_int_channel(format
)) {
47 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
48 isl_format_get_name(format
));
52 for (int i
= 0; i
< 4; i
++) {
53 if (!isl_format_has_color_component(format
, i
)) {
57 if (devinfo
->gen
< 9 &&
58 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
67 can_fast_clear_color(struct iris_context
*ice
,
68 struct pipe_resource
*p_res
,
70 const struct pipe_box
*box
,
71 enum isl_format render_format
,
72 union isl_color_value color
)
74 struct iris_resource
*res
= (void *) p_res
;
76 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
79 if (!isl_aux_usage_has_fast_clears(res
->aux
.usage
))
82 /* Check for partial clear */
83 if (box
->x
> 0 || box
->y
> 0 ||
84 box
->width
< minify(p_res
->width0
, level
) ||
85 box
->height
< minify(p_res
->height0
, level
)) {
89 /* Disable sRGB fast-clears for non-0/1 color values. For texturing and
90 * draw calls, HW expects the clear color to be in two different color
91 * spaces after sRGB fast-clears - sRGB in the former and linear in the
92 * latter. By limiting the allowable values to 0/1, both color space
93 * requirements are satisfied.
95 if (isl_format_is_srgb(render_format
) &&
96 !isl_color_value_is_zero_one(color
, render_format
)) {
100 /* We store clear colors as floats or uints as needed. If there are
101 * texture views in play, the formats will not properly be respected
102 * during resolves because the resolve operations only know about the
103 * resource and not the renderbuffer.
105 if (!iris_render_formats_color_compatible(render_format
, res
->surf
.format
,
110 /* XXX: if (irb->mt->supports_fast_clear)
111 * see intel_miptree_create_for_dri_image()
114 if (!iris_is_color_fast_clear_compatible(ice
, res
->surf
.format
, color
))
120 static union isl_color_value
121 convert_fast_clear_color(struct iris_context
*ice
,
122 struct iris_resource
*res
,
123 const union isl_color_value color
)
125 union isl_color_value override_color
= color
;
126 struct pipe_resource
*p_res
= (void *) res
;
128 const enum pipe_format format
= p_res
->format
;
129 const struct util_format_description
*desc
=
130 util_format_description(format
);
131 unsigned colormask
= util_format_colormask(desc
);
133 if (util_format_is_intensity(format
) ||
134 util_format_is_luminance(format
) ||
135 util_format_is_luminance_alpha(format
)) {
136 override_color
.u32
[1] = override_color
.u32
[0];
137 override_color
.u32
[2] = override_color
.u32
[0];
138 if (util_format_is_intensity(format
))
139 override_color
.u32
[3] = override_color
.u32
[0];
141 for (int chan
= 0; chan
< 3; chan
++) {
142 if (!(colormask
& (1 << chan
)))
143 override_color
.u32
[chan
] = 0;
147 if (util_format_is_unorm(format
)) {
148 for (int i
= 0; i
< 4; i
++)
149 override_color
.f32
[i
] = SATURATE(override_color
.f32
[i
]);
150 } else if (util_format_is_snorm(format
)) {
151 for (int i
= 0; i
< 4; i
++)
152 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
153 } else if (util_format_is_pure_uint(format
)) {
154 for (int i
= 0; i
< 4; i
++) {
155 unsigned bits
= util_format_get_component_bits(
156 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
158 uint32_t max
= (1u << bits
) - 1;
159 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
162 } else if (util_format_is_pure_sint(format
)) {
163 for (int i
= 0; i
< 4; i
++) {
164 unsigned bits
= util_format_get_component_bits(
165 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
167 int32_t max
= (1 << (bits
- 1)) - 1;
168 int32_t min
= -(1 << (bits
- 1));
169 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
172 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
173 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
174 /* these packed float formats only store unsigned values */
175 for (int i
= 0; i
< 4; i
++)
176 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
179 if (!(colormask
& 1 << 3)) {
180 if (util_format_is_pure_integer(format
))
181 override_color
.u32
[3] = 1;
183 override_color
.f32
[3] = 1.0f
;
186 return override_color
;
190 fast_clear_color(struct iris_context
*ice
,
191 struct iris_resource
*res
,
193 const struct pipe_box
*box
,
194 enum isl_format format
,
195 union isl_color_value color
,
196 enum blorp_batch_flags blorp_flags
)
198 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
199 struct pipe_resource
*p_res
= (void *) res
;
200 const enum isl_aux_state aux_state
=
201 iris_resource_get_aux_state(res
, level
, box
->z
);
203 color
= convert_fast_clear_color(ice
, res
, color
);
205 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
209 /* We decided that we are going to fast clear, and the color is
210 * changing. But if we have a predicate bit set, the predication
211 * affects whether we should clear or not, and if we shouldn't, we
212 * also shouldn't update the clear color.
214 * However, we can't simply predicate-update the clear color (the
215 * commands don't support that). And we would lose track of the
216 * color, preventing us from doing some optimizations later.
218 * Since changing the clear color when the predication bit is enabled
219 * is not something that should happen often, we stall on the CPU here
220 * to resolve the predication, and then proceed.
222 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
223 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
226 /* If we are clearing to a new clear value, we need to resolve fast
227 * clears from other levels/layers first, since we can't have different
228 * levels/layers with different fast clear colors.
230 for (unsigned res_lvl
= 0; res_lvl
< res
->surf
.levels
; res_lvl
++) {
231 const unsigned level_layers
=
232 iris_get_num_logical_layers(res
, res_lvl
);
233 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
234 if (res_lvl
== level
&&
236 layer
< box
->z
+ box
->depth
) {
237 /* We're going to clear this layer anyway. Leave it alone. */
241 enum isl_aux_state aux_state
=
242 iris_resource_get_aux_state(res
, res_lvl
, layer
);
244 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
245 aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
&&
246 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
247 /* This slice doesn't have any fast-cleared bits. */
251 /* If we got here, then the level may have fast-clear bits that use
252 * the old clear value. We need to do a color resolve to get rid
253 * of their use of the clear color before we can change it.
254 * Fortunately, few applications ever change their clear color at
255 * different levels/layers, so this shouldn't happen often.
257 iris_resource_prepare_access(ice
, res
,
258 res_lvl
, 1, layer
, 1,
261 perf_debug(&ice
->dbg
,
262 "Resolving resource (%p) level %d, layer %d: color changing from "
263 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
264 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
266 res
->aux
.clear_color
.f32
[0],
267 res
->aux
.clear_color
.f32
[1],
268 res
->aux
.clear_color
.f32
[2],
269 res
->aux
.clear_color
.f32
[3],
270 color
.f32
[0], color
.f32
[1], color
.f32
[2], color
.f32
[3]);
275 iris_resource_set_clear_color(ice
, res
, color
);
277 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
278 * changed, the clear is redundant and can be skipped.
280 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
283 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
285 * "Any transition from any value in {Clear, Render, Resolve} to a
286 * different value in {Clear, Render, Resolve} requires end of pipe
289 * In other words, fast clear ops are not properly synchronized with
290 * other drawing. We need to use a PIPE_CONTROL to ensure that the
291 * contents of the previous draw hit the render target before we resolve
292 * and again afterwards to ensure that the resolve is complete before we
293 * do any more regular drawing.
295 iris_emit_end_of_pipe_sync(batch
,
296 "fast clear: pre-flush",
297 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
299 iris_batch_sync_region_start(batch
);
301 /* If we reach this point, we need to fast clear to change the state to
302 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
304 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
306 struct blorp_batch blorp_batch
;
307 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
309 struct blorp_surf surf
;
310 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
311 p_res
, res
->aux
.usage
, level
, true);
313 blorp_fast_clear(&blorp_batch
, &surf
, format
, ISL_SWIZZLE_IDENTITY
,
314 level
, box
->z
, box
->depth
,
315 box
->x
, box
->y
, box
->x
+ box
->width
,
316 box
->y
+ box
->height
);
317 blorp_batch_finish(&blorp_batch
);
318 iris_emit_end_of_pipe_sync(batch
,
319 "fast clear: post flush",
320 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
321 iris_batch_sync_region_end(batch
);
323 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
324 box
->depth
, ISL_AUX_STATE_CLEAR
);
325 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
326 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
331 clear_color(struct iris_context
*ice
,
332 struct pipe_resource
*p_res
,
334 const struct pipe_box
*box
,
335 bool render_condition_enabled
,
336 enum isl_format format
,
337 struct isl_swizzle swizzle
,
338 union isl_color_value color
)
340 struct iris_resource
*res
= (void *) p_res
;
342 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
343 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
344 enum blorp_batch_flags blorp_flags
= 0;
346 if (render_condition_enabled
) {
347 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
350 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
351 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
354 if (p_res
->target
== PIPE_BUFFER
)
355 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
357 iris_batch_maybe_flush(batch
, 1500);
359 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
361 if (can_fast_clear
) {
362 fast_clear_color(ice
, res
, level
, box
, format
, color
,
367 bool color_write_disable
[4] = { false, false, false, false };
368 enum isl_aux_usage aux_usage
=
369 iris_resource_render_aux_usage(ice
, res
, format
, false);
371 iris_resource_prepare_render(ice
, batch
, res
, level
,
372 box
->z
, box
->depth
, aux_usage
);
373 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_RENDER_WRITE
);
375 struct blorp_surf surf
;
376 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
377 p_res
, aux_usage
, level
, true);
379 iris_batch_sync_region_start(batch
);
381 struct blorp_batch blorp_batch
;
382 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
384 if (!isl_format_supports_rendering(devinfo
, format
) &&
385 isl_format_is_rgbx(format
))
386 format
= isl_format_rgbx_to_rgba(format
);
388 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
389 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
390 box
->x
+ box
->width
, box
->y
+ box
->height
,
391 color
, color_write_disable
);
393 blorp_batch_finish(&blorp_batch
);
394 iris_batch_sync_region_end(batch
);
396 iris_flush_and_dirty_for_history(ice
, batch
, res
,
397 PIPE_CONTROL_RENDER_TARGET_FLUSH
,
398 "cache history: post color clear");
400 iris_resource_finish_render(ice
, res
, level
,
401 box
->z
, box
->depth
, aux_usage
);
405 can_fast_clear_depth(struct iris_context
*ice
,
406 struct iris_resource
*res
,
408 const struct pipe_box
*box
,
411 struct pipe_resource
*p_res
= (void *) res
;
412 struct pipe_context
*ctx
= (void *) ice
;
413 struct iris_screen
*screen
= (void *) ctx
->screen
;
414 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
416 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
419 /* Check for partial clears */
420 if (box
->x
> 0 || box
->y
> 0 ||
421 box
->width
< u_minify(p_res
->width0
, level
) ||
422 box
->height
< u_minify(p_res
->height0
, level
)) {
426 if (!(res
->aux
.has_hiz
& (1 << level
)))
429 return blorp_can_hiz_clear_depth(devinfo
, &res
->surf
, res
->aux
.usage
,
430 level
, box
->z
, box
->x
, box
->y
,
432 box
->y
+ box
->height
);
436 fast_clear_depth(struct iris_context
*ice
,
437 struct iris_resource
*res
,
439 const struct pipe_box
*box
,
442 struct pipe_resource
*p_res
= (void *) res
;
443 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
445 /* Quantize the clear value to what can be stored in the actual depth
446 * buffer. This makes the following check more accurate because it now
447 * checks if the actual depth bits will match. It also prevents us from
448 * getting a too-accurate depth value during depth testing or when sampling
451 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
452 const uint32_t depth_max
= (1 << nbits
) - 1;
453 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
454 (unsigned)(depth
* depth_max
) / (float)depth_max
;
456 bool update_clear_depth
= false;
458 /* If we're clearing to a new clear value, then we need to resolve any clear
459 * flags out of the HiZ buffer into the real depth buffer.
461 if (res
->aux
.clear_color
.f32
[0] != depth
) {
462 /* We decided that we are going to fast clear, and the color is
463 * changing. But if we have a predicate bit set, the predication
464 * affects whether we should clear or not, and if we shouldn't, we
465 * also shouldn't update the clear color.
467 * However, we can't simply predicate-update the clear color (the
468 * commands don't support that). And we would lose track of the
469 * color, preventing us from doing some optimizations later.
471 * For depth clears, things are even more complicated, because here we
472 * resolve the other levels/layers if they have a different color than
473 * the current one. That resolve can be predicated, but we also set those
474 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
475 * Keeping track of the aux state when predication is involved is just
476 * even more complex, so the easiest thing to do when the fast clear
477 * depth is changing is to stall on the CPU and resolve the predication.
479 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
480 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
483 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
484 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
487 const unsigned level_layers
=
488 iris_get_num_logical_layers(res
, res_level
);
489 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
490 if (res_level
== level
&&
492 layer
< box
->z
+ box
->depth
) {
493 /* We're going to clear this layer anyway. Leave it alone. */
497 enum isl_aux_state aux_state
=
498 iris_resource_get_aux_state(res
, res_level
, layer
);
500 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
501 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
502 /* This slice doesn't have any fast-cleared bits. */
506 /* If we got here, then the level may have fast-clear bits that
507 * use the old clear value. We need to do a depth resolve to get
508 * rid of their use of the clear value before we can change it.
509 * Fortunately, few applications ever change their depth clear
510 * value so this shouldn't happen often.
512 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
513 ISL_AUX_OP_FULL_RESOLVE
, false);
514 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
515 ISL_AUX_STATE_RESOLVED
);
518 const union isl_color_value clear_value
= { .f32
= {depth
, } };
519 iris_resource_set_clear_color(ice
, res
, clear_value
);
520 update_clear_depth
= true;
523 for (unsigned l
= 0; l
< box
->depth
; l
++) {
524 enum isl_aux_state aux_state
=
525 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
526 if (update_clear_depth
|| aux_state
!= ISL_AUX_STATE_CLEAR
) {
527 if (aux_state
== ISL_AUX_STATE_CLEAR
) {
528 perf_debug(&ice
->dbg
, "Performing HiZ clear just to update the "
529 "depth clear value\n");
531 iris_hiz_exec(ice
, batch
, res
, level
,
532 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
537 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
538 ISL_AUX_STATE_CLEAR
);
539 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
543 clear_depth_stencil(struct iris_context
*ice
,
544 struct pipe_resource
*p_res
,
546 const struct pipe_box
*box
,
547 bool render_condition_enabled
,
553 struct iris_resource
*res
= (void *) p_res
;
555 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
556 enum blorp_batch_flags blorp_flags
= 0;
558 if (render_condition_enabled
) {
559 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
562 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
563 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
566 iris_batch_maybe_flush(batch
, 1500);
568 struct iris_resource
*z_res
;
569 struct iris_resource
*stencil_res
;
570 struct blorp_surf z_surf
;
571 struct blorp_surf stencil_surf
;
573 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
574 if (z_res
&& clear_depth
&&
575 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
576 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
577 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
578 "cache history: post fast Z clear");
583 /* At this point, we might have fast cleared the depth buffer. So if there's
584 * no stencil clear pending, return early.
586 if (!(clear_depth
|| (clear_stencil
&& stencil_res
))) {
590 if (clear_depth
&& z_res
) {
591 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
592 iris_emit_buffer_barrier_for(batch
, z_res
->bo
, IRIS_DOMAIN_DEPTH_WRITE
);
593 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
594 &z_surf
, &z_res
->base
, z_res
->aux
.usage
,
598 uint8_t stencil_mask
= clear_stencil
&& stencil_res
? 0xff : 0;
600 iris_resource_prepare_access(ice
, stencil_res
, level
, 1, box
->z
,
601 box
->depth
, stencil_res
->aux
.usage
, false);
602 iris_emit_buffer_barrier_for(batch
, stencil_res
->bo
,
603 IRIS_DOMAIN_DEPTH_WRITE
);
604 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
605 &stencil_surf
, &stencil_res
->base
,
606 stencil_res
->aux
.usage
, level
, true);
609 iris_batch_sync_region_start(batch
);
611 struct blorp_batch blorp_batch
;
612 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
614 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
615 level
, box
->z
, box
->depth
,
618 box
->y
+ box
->height
,
619 clear_depth
&& z_res
, depth
,
620 stencil_mask
, stencil
);
622 blorp_batch_finish(&blorp_batch
);
623 iris_batch_sync_region_end(batch
);
625 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
626 "cache history: post slow ZS clear");
628 if (clear_depth
&& z_res
) {
629 iris_resource_finish_depth(ice
, z_res
, level
,
630 box
->z
, box
->depth
, true);
634 iris_resource_finish_write(ice
, stencil_res
, level
, box
->z
, box
->depth
,
635 stencil_res
->aux
.usage
);
640 * The pipe->clear() driver hook.
642 * This clears buffers attached to the current draw framebuffer.
645 iris_clear(struct pipe_context
*ctx
,
647 const struct pipe_scissor_state
*scissor_state
,
648 const union pipe_color_union
*p_color
,
652 struct iris_context
*ice
= (void *) ctx
;
653 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
655 assert(buffers
!= 0);
657 struct pipe_box box
= {
658 .width
= cso_fb
->width
,
659 .height
= cso_fb
->height
,
663 box
.x
= scissor_state
->minx
;
664 box
.y
= scissor_state
->miny
;
665 box
.width
= MIN2(box
.width
, scissor_state
->maxx
- scissor_state
->minx
);
666 box
.height
= MIN2(box
.height
, scissor_state
->maxy
- scissor_state
->miny
);
669 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
670 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
672 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1;
673 box
.z
= psurf
->u
.tex
.first_layer
,
674 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
675 buffers
& PIPE_CLEAR_DEPTH
,
676 buffers
& PIPE_CLEAR_STENCIL
,
680 if (buffers
& PIPE_CLEAR_COLOR
) {
681 /* pipe_color_union and isl_color_value are interchangeable */
682 union isl_color_value
*color
= (void *) p_color
;
684 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
685 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
686 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
687 struct iris_surface
*isurf
= (void *) psurf
;
688 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
689 box
.z
= psurf
->u
.tex
.first_layer
,
691 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
692 true, isurf
->view
.format
, isurf
->view
.swizzle
,
700 * The pipe->clear_texture() driver hook.
702 * This clears the given texture resource.
705 iris_clear_texture(struct pipe_context
*ctx
,
706 struct pipe_resource
*p_res
,
708 const struct pipe_box
*box
,
711 struct iris_context
*ice
= (void *) ctx
;
712 struct iris_screen
*screen
= (void *) ctx
->screen
;
713 struct iris_resource
*res
= (void *) p_res
;
714 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
716 if (iris_resource_unfinished_aux_import(res
))
717 iris_resource_finish_aux_import(ctx
->screen
, res
);
719 if (util_format_is_depth_or_stencil(p_res
->format
)) {
720 const struct util_format_unpack_description
*unpack
=
721 util_format_unpack_description(p_res
->format
);
726 if (unpack
->unpack_z_float
)
727 util_format_unpack_z_float(p_res
->format
, &depth
, data
, 1);
729 if (unpack
->unpack_s_8uint
)
730 util_format_unpack_s_8uint(p_res
->format
, &stencil
, data
, 1);
732 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
735 union isl_color_value color
;
736 struct iris_resource
*res
= (void *) p_res
;
737 enum isl_format format
= res
->surf
.format
;
739 if (!isl_format_supports_rendering(devinfo
, format
)) {
740 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
741 // XXX: actually just get_copy_format_for_bpb from BLORP
742 // XXX: don't cut and paste this
744 case 8: format
= ISL_FORMAT_R8_UINT
; break;
745 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
746 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
747 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
748 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
749 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
750 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
751 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
753 unreachable("Unknown format bpb");
756 /* No aux surfaces for non-renderable surfaces */
757 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
760 isl_color_value_unpack(&color
, format
, data
);
762 clear_color(ice
, p_res
, level
, box
, true, format
,
763 ISL_SWIZZLE_IDENTITY
, color
);
768 * The pipe->clear_render_target() driver hook.
770 * This clears the given render target surface.
773 iris_clear_render_target(struct pipe_context
*ctx
,
774 struct pipe_surface
*psurf
,
775 const union pipe_color_union
*p_color
,
776 unsigned dst_x
, unsigned dst_y
,
777 unsigned width
, unsigned height
,
778 bool render_condition_enabled
)
780 struct iris_context
*ice
= (void *) ctx
;
781 struct iris_surface
*isurf
= (void *) psurf
;
782 struct pipe_box box
= {
785 .z
= psurf
->u
.tex
.first_layer
,
788 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
791 /* pipe_color_union and isl_color_value are interchangeable */
792 union isl_color_value
*color
= (void *) p_color
;
794 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
795 render_condition_enabled
,
796 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
800 * The pipe->clear_depth_stencil() driver hook.
802 * This clears the given depth/stencil surface.
805 iris_clear_depth_stencil(struct pipe_context
*ctx
,
806 struct pipe_surface
*psurf
,
810 unsigned dst_x
, unsigned dst_y
,
811 unsigned width
, unsigned height
,
812 bool render_condition_enabled
)
814 struct iris_context
*ice
= (void *) ctx
;
815 struct pipe_box box
= {
818 .z
= psurf
->u
.tex
.first_layer
,
821 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
824 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
826 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
827 render_condition_enabled
,
828 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
833 iris_init_clear_functions(struct pipe_context
*ctx
)
835 ctx
->clear
= iris_clear
;
836 ctx
->clear_texture
= iris_clear_texture
;
837 ctx
->clear_render_target
= iris_clear_render_target
;
838 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;