2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
81 /* Check for partial clear */
82 if (box
->x
> 0 || box
->y
> 0 ||
83 box
->width
< p_res
->width0
||
84 box
->height
< p_res
->height0
) {
88 /* We store clear colors as floats or uints as needed. If there are
89 * texture views in play, the formats will not properly be respected
90 * during resolves because the resolve operations only know about the
91 * resource and not the renderbuffer.
93 if (isl_format_srgb_to_linear(render_format
) !=
94 isl_format_srgb_to_linear(format
)) {
98 /* XXX: if (irb->mt->supports_fast_clear)
99 * see intel_miptree_create_for_dri_image()
102 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
108 static union isl_color_value
109 convert_fast_clear_color(struct iris_context
*ice
,
110 struct iris_resource
*res
,
111 enum isl_format render_format
,
112 const union isl_color_value color
)
114 union isl_color_value override_color
= color
;
115 struct pipe_resource
*p_res
= (void *) res
;
117 const enum pipe_format format
= p_res
->format
;
118 const struct util_format_description
*desc
=
119 util_format_description(format
);
120 unsigned colormask
= util_format_colormask(desc
);
122 if (util_format_is_intensity(format
) ||
123 util_format_is_luminance(format
) ||
124 util_format_is_luminance_alpha(format
)) {
125 override_color
.u32
[1] = override_color
.u32
[0];
126 override_color
.u32
[2] = override_color
.u32
[0];
127 if (util_format_is_intensity(format
))
128 override_color
.u32
[3] = override_color
.u32
[0];
130 for (int chan
= 0; chan
< 3; chan
++) {
131 if (!(colormask
& (1 << chan
)))
132 override_color
.u32
[chan
] = 0;
136 if (util_format_is_unorm(format
)) {
137 for (int i
= 0; i
< 4; i
++)
138 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
139 } else if (util_format_is_snorm(format
)) {
140 for (int i
= 0; i
< 4; i
++)
141 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
142 } else if (util_format_is_pure_uint(format
)) {
143 for (int i
= 0; i
< 4; i
++) {
144 unsigned bits
= util_format_get_component_bits(
145 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
147 uint32_t max
= (1u << bits
) - 1;
148 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
151 } else if (util_format_is_pure_sint(format
)) {
152 for (int i
= 0; i
< 4; i
++) {
153 unsigned bits
= util_format_get_component_bits(
154 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
156 int32_t max
= (1 << (bits
- 1)) - 1;
157 int32_t min
= -(1 << (bits
- 1));
158 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
161 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
162 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
163 /* these packed float formats only store unsigned values */
164 for (int i
= 0; i
< 4; i
++)
165 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
168 if (!(colormask
& 1 << 3)) {
169 if (util_format_is_pure_integer(format
))
170 override_color
.u32
[3] = 1;
172 override_color
.f32
[3] = 1.0f
;
175 /* Handle linear to SRGB conversion */
176 if (isl_format_is_srgb(render_format
)) {
177 for (int i
= 0; i
< 3; i
++) {
178 override_color
.f32
[i
] =
179 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
183 return override_color
;
187 fast_clear_color(struct iris_context
*ice
,
188 struct iris_resource
*res
,
190 const struct pipe_box
*box
,
191 enum isl_format format
,
192 union isl_color_value color
,
193 enum blorp_batch_flags blorp_flags
)
195 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
196 struct pipe_resource
*p_res
= (void *) res
;
197 const enum isl_aux_state aux_state
=
198 iris_resource_get_aux_state(res
, level
, box
->z
);
200 color
= convert_fast_clear_color(ice
, res
, format
, color
);
202 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
206 /* We decided that we are going to fast clear, and the color is
207 * changing. But if we have a predicate bit set, the predication
208 * affects whether we should clear or not, and if we shouldn't, we
209 * also shouldn't update the clear color.
211 * However, we can't simply predicate-update the clear color (the
212 * commands don't support that). And we would lose track of the
213 * color, preventing us from doing some optimizations later.
215 * Since changing the clear color when the predication bit is enabled
216 * is not something that should happen often, we stall on the CPU here
217 * to resolve the predication, and then proceed.
219 iris_resolve_conditional_render(ice
);
220 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
223 /* If we are clearing to a new clear value, we need to resolve fast
224 * clears from other levels/layers first, since we can't have different
225 * levels/layers with different fast clear colors.
227 for (unsigned res_lvl
= 0; res_lvl
< res
->surf
.levels
; res_lvl
++) {
228 const unsigned level_layers
=
229 iris_get_num_logical_layers(res
, res_lvl
);
230 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
231 if (res_lvl
== level
&&
233 layer
< box
->z
+ box
->depth
) {
234 /* We're going to clear this layer anyway. Leave it alone. */
238 enum isl_aux_state aux_state
=
239 iris_resource_get_aux_state(res
, res_lvl
, layer
);
241 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
242 aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
&&
243 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
244 /* This slice doesn't have any fast-cleared bits. */
248 /* If we got here, then the level may have fast-clear bits that use
249 * the old clear value. We need to do a color resolve to get rid
250 * of their use of the clear color before we can change it.
251 * Fortunately, few applications ever change their clear color at
252 * different levels/layers, so this shouldn't happen often.
254 iris_resource_prepare_access(ice
, batch
, res
,
255 res_lvl
, 1, layer
, 1,
258 perf_debug(&ice
->dbg
,
259 "Resolving resource (%p) level %d, layer %d: color changing from "
260 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
261 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
263 res
->aux
.clear_color
.f32
[0],
264 res
->aux
.clear_color
.f32
[1],
265 res
->aux
.clear_color
.f32
[2],
266 res
->aux
.clear_color
.f32
[3],
267 color
.f32
[0], color
.f32
[1], color
.f32
[2], color
.f32
[3]);
272 iris_resource_set_clear_color(ice
, res
, color
);
274 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
275 * changed, the clear is redundant and can be skipped.
277 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
280 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
282 * "Any transition from any value in {Clear, Render, Resolve} to a
283 * different value in {Clear, Render, Resolve} requires end of pipe
286 * In other words, fast clear ops are not properly synchronized with
287 * other drawing. We need to use a PIPE_CONTROL to ensure that the
288 * contents of the previous draw hit the render target before we resolve
289 * and again afterwards to ensure that the resolve is complete before we
290 * do any more regular drawing.
292 iris_emit_end_of_pipe_sync(batch
,
293 "fast clear: pre-flush",
294 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
296 /* If we reach this point, we need to fast clear to change the state to
297 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
299 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
301 struct blorp_batch blorp_batch
;
302 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
304 struct blorp_surf surf
;
305 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
308 /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of
309 * the clear color during the fast clear, if the surface format is of sRGB
310 * type. We use the linear version of the surface format here to prevent
311 * that from happening, since we already do our own linear -> sRGB
312 * conversion in convert_fast_clear_color().
314 blorp_fast_clear(&blorp_batch
, &surf
, isl_format_srgb_to_linear(format
),
315 level
, box
->z
, box
->depth
,
316 box
->x
, box
->y
, box
->x
+ box
->width
,
317 box
->y
+ box
->height
);
318 blorp_batch_finish(&blorp_batch
);
319 iris_emit_end_of_pipe_sync(batch
,
320 "fast clear: post flush",
321 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
323 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
324 box
->depth
, ISL_AUX_STATE_CLEAR
);
325 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
330 clear_color(struct iris_context
*ice
,
331 struct pipe_resource
*p_res
,
333 const struct pipe_box
*box
,
334 bool render_condition_enabled
,
335 enum isl_format format
,
336 struct isl_swizzle swizzle
,
337 union isl_color_value color
)
339 struct iris_resource
*res
= (void *) p_res
;
341 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
342 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
343 enum blorp_batch_flags blorp_flags
= 0;
345 if (render_condition_enabled
) {
346 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
349 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
350 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
353 if (p_res
->target
== PIPE_BUFFER
)
354 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
356 iris_batch_maybe_flush(batch
, 1500);
358 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
359 res
->surf
.format
, format
, color
);
360 if (can_fast_clear
) {
361 fast_clear_color(ice
, res
, level
, box
, format
, color
,
366 bool color_write_disable
[4] = { false, false, false, false };
367 enum isl_aux_usage aux_usage
=
368 iris_resource_render_aux_usage(ice
, res
, format
,
371 iris_resource_prepare_render(ice
, batch
, res
, level
,
372 box
->z
, box
->depth
, aux_usage
);
374 struct blorp_surf surf
;
375 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
378 struct blorp_batch blorp_batch
;
379 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
381 if (!isl_format_supports_rendering(devinfo
, format
) &&
382 isl_format_is_rgbx(format
))
383 format
= isl_format_rgbx_to_rgba(format
);
385 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
386 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
387 box
->x
+ box
->width
, box
->y
+ box
->height
,
388 color
, color_write_disable
);
390 blorp_batch_finish(&blorp_batch
);
391 iris_flush_and_dirty_for_history(ice
, batch
, res
,
392 PIPE_CONTROL_RENDER_TARGET_FLUSH
,
393 "cache history: post color clear");
395 iris_resource_finish_render(ice
, res
, level
,
396 box
->z
, box
->depth
, aux_usage
);
400 can_fast_clear_depth(struct iris_context
*ice
,
401 struct iris_resource
*res
,
403 const struct pipe_box
*box
,
406 struct pipe_resource
*p_res
= (void *) res
;
408 /* Check for partial clears */
409 if (box
->x
> 0 || box
->y
> 0 ||
410 box
->width
< u_minify(p_res
->width0
, level
) ||
411 box
->height
< u_minify(p_res
->height0
, level
)) {
415 if (!(res
->aux
.has_hiz
& (1 << level
)))
422 fast_clear_depth(struct iris_context
*ice
,
423 struct iris_resource
*res
,
425 const struct pipe_box
*box
,
428 struct pipe_resource
*p_res
= (void *) res
;
429 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
431 /* Quantize the clear value to what can be stored in the actual depth
432 * buffer. This makes the following check more accurate because it now
433 * checks if the actual depth bits will match. It also prevents us from
434 * getting a too-accurate depth value during depth testing or when sampling
437 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
438 const uint32_t depth_max
= (1 << nbits
) - 1;
439 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
440 (unsigned)(depth
* depth_max
) / (float)depth_max
;
442 bool update_clear_depth
= false;
444 /* If we're clearing to a new clear value, then we need to resolve any clear
445 * flags out of the HiZ buffer into the real depth buffer.
447 if (res
->aux
.clear_color
.f32
[0] != depth
) {
448 /* We decided that we are going to fast clear, and the color is
449 * changing. But if we have a predicate bit set, the predication
450 * affects whether we should clear or not, and if we shouldn't, we
451 * also shouldn't update the clear color.
453 * However, we can't simply predicate-update the clear color (the
454 * commands don't support that). And we would lose track of the
455 * color, preventing us from doing some optimizations later.
457 * For depth clears, things are even more complicated, because here we
458 * resolve the other levels/layers if they have a different color than
459 * the current one. That resolve can be predicated, but we also set those
460 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
461 * Keeping track of the aux state when predication is involved is just
462 * even more complex, so the easiest thing to do when the fast clear
463 * depth is changing is to stall on the CPU and resolve the predication.
465 iris_resolve_conditional_render(ice
);
466 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
469 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
470 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
473 const unsigned level_layers
=
474 iris_get_num_logical_layers(res
, res_level
);
475 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
476 if (res_level
== level
&&
478 layer
< box
->z
+ box
->depth
) {
479 /* We're going to clear this layer anyway. Leave it alone. */
483 enum isl_aux_state aux_state
=
484 iris_resource_get_aux_state(res
, res_level
, layer
);
486 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
487 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
488 /* This slice doesn't have any fast-cleared bits. */
492 /* If we got here, then the level may have fast-clear bits that
493 * use the old clear value. We need to do a depth resolve to get
494 * rid of their use of the clear value before we can change it.
495 * Fortunately, few applications ever change their depth clear
496 * value so this shouldn't happen often.
498 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
499 ISL_AUX_OP_FULL_RESOLVE
, false);
500 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
501 ISL_AUX_STATE_RESOLVED
);
504 const union isl_color_value clear_value
= { .f32
= {depth
, } };
505 iris_resource_set_clear_color(ice
, res
, clear_value
);
506 update_clear_depth
= true;
509 for (unsigned l
= 0; l
< box
->depth
; l
++) {
510 enum isl_aux_state aux_state
=
511 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
512 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
513 iris_hiz_exec(ice
, batch
, res
, level
,
514 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
519 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
520 ISL_AUX_STATE_CLEAR
);
521 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
525 clear_depth_stencil(struct iris_context
*ice
,
526 struct pipe_resource
*p_res
,
528 const struct pipe_box
*box
,
529 bool render_condition_enabled
,
535 struct iris_resource
*res
= (void *) p_res
;
537 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
538 enum blorp_batch_flags blorp_flags
= 0;
540 if (render_condition_enabled
) {
541 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
544 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
545 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
548 iris_batch_maybe_flush(batch
, 1500);
550 struct iris_resource
*z_res
;
551 struct iris_resource
*stencil_res
;
552 struct blorp_surf z_surf
;
553 struct blorp_surf stencil_surf
;
555 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
556 if (z_res
&& clear_depth
&&
557 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
558 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
559 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
560 "cache history: post fast Z clear");
565 /* At this point, we might have fast cleared the depth buffer. So if there's
566 * no stencil clear pending, return early.
568 if (!(clear_depth
|| clear_stencil
)) {
573 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
574 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
575 z_res
->aux
.usage
, level
, true);
578 struct blorp_batch blorp_batch
;
579 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
582 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
583 &stencil_res
->base
, stencil_res
->aux
.usage
,
587 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
588 level
, box
->z
, box
->depth
,
591 box
->y
+ box
->height
,
592 clear_depth
&& z_res
, depth
,
593 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
595 blorp_batch_finish(&blorp_batch
);
596 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
597 "cache history: post slow ZS clear");
600 iris_resource_finish_depth(ice
, z_res
, level
,
601 box
->z
, box
->depth
, true);
606 * The pipe->clear() driver hook.
608 * This clears buffers attached to the current draw framebuffer.
611 iris_clear(struct pipe_context
*ctx
,
613 const union pipe_color_union
*p_color
,
617 struct iris_context
*ice
= (void *) ctx
;
618 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
620 assert(buffers
!= 0);
622 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
623 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
624 struct pipe_box box
= {
625 .width
= cso_fb
->width
,
626 .height
= cso_fb
->height
,
627 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
628 .z
= psurf
->u
.tex
.first_layer
,
631 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
632 buffers
& PIPE_CLEAR_DEPTH
,
633 buffers
& PIPE_CLEAR_STENCIL
,
637 if (buffers
& PIPE_CLEAR_COLOR
) {
638 /* pipe_color_union and isl_color_value are interchangeable */
639 union isl_color_value
*color
= (void *) p_color
;
641 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
642 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
643 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
644 struct iris_surface
*isurf
= (void *) psurf
;
645 struct pipe_box box
= {
646 .width
= cso_fb
->width
,
647 .height
= cso_fb
->height
,
648 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
649 .z
= psurf
->u
.tex
.first_layer
,
652 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
653 true, isurf
->view
.format
, isurf
->view
.swizzle
,
661 * The pipe->clear_texture() driver hook.
663 * This clears the given texture resource.
666 iris_clear_texture(struct pipe_context
*ctx
,
667 struct pipe_resource
*p_res
,
669 const struct pipe_box
*box
,
672 struct iris_context
*ice
= (void *) ctx
;
673 struct iris_screen
*screen
= (void *) ctx
->screen
;
674 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
676 if (util_format_is_depth_or_stencil(p_res
->format
)) {
677 const struct util_format_description
*fmt_desc
=
678 util_format_description(p_res
->format
);
683 if (fmt_desc
->unpack_z_float
)
684 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
686 if (fmt_desc
->unpack_s_8uint
)
687 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
689 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
692 union isl_color_value color
;
693 struct iris_resource
*res
= (void *) p_res
;
694 enum isl_format format
= res
->surf
.format
;
696 if (!isl_format_supports_rendering(devinfo
, format
)) {
697 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
698 // XXX: actually just get_copy_format_for_bpb from BLORP
699 // XXX: don't cut and paste this
701 case 8: format
= ISL_FORMAT_R8_UINT
; break;
702 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
703 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
704 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
705 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
706 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
707 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
708 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
710 unreachable("Unknown format bpb");
713 /* No aux surfaces for non-renderable surfaces */
714 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
717 isl_color_value_unpack(&color
, format
, data
);
719 clear_color(ice
, p_res
, level
, box
, true, format
,
720 ISL_SWIZZLE_IDENTITY
, color
);
725 * The pipe->clear_render_target() driver hook.
727 * This clears the given render target surface.
730 iris_clear_render_target(struct pipe_context
*ctx
,
731 struct pipe_surface
*psurf
,
732 const union pipe_color_union
*p_color
,
733 unsigned dst_x
, unsigned dst_y
,
734 unsigned width
, unsigned height
,
735 bool render_condition_enabled
)
737 struct iris_context
*ice
= (void *) ctx
;
738 struct iris_surface
*isurf
= (void *) psurf
;
739 struct pipe_box box
= {
742 .z
= psurf
->u
.tex
.first_layer
,
745 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
748 /* pipe_color_union and isl_color_value are interchangeable */
749 union isl_color_value
*color
= (void *) p_color
;
751 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
752 render_condition_enabled
,
753 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
757 * The pipe->clear_depth_stencil() driver hook.
759 * This clears the given depth/stencil surface.
762 iris_clear_depth_stencil(struct pipe_context
*ctx
,
763 struct pipe_surface
*psurf
,
767 unsigned dst_x
, unsigned dst_y
,
768 unsigned width
, unsigned height
,
769 bool render_condition_enabled
)
771 struct iris_context
*ice
= (void *) ctx
;
772 struct pipe_box box
= {
775 .z
= psurf
->u
.tex
.first_layer
,
778 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
781 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
783 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
784 render_condition_enabled
,
785 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
790 iris_init_clear_functions(struct pipe_context
*ctx
)
792 ctx
->clear
= iris_clear
;
793 ctx
->clear_texture
= iris_clear_texture
;
794 ctx
->clear_render_target
= iris_clear_render_target
;
795 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;