9be67608ebe56a81d72e8a9019cba97cd86396a9
[mesa.git] / src / gallium / drivers / iris / iris_clear.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <errno.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37
38 /**
39 * The pipe->clear() driver hook.
40 *
41 * This clears buffers attached to the current draw framebuffer.
42 */
43 static void
44 iris_clear(struct pipe_context *ctx,
45 unsigned buffers,
46 const union pipe_color_union *p_color,
47 double depth,
48 unsigned stencil)
49 {
50 struct iris_context *ice = (void *) ctx;
51 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
52 assert(buffers != 0);
53
54 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
55
56 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
57 return;
58
59 enum blorp_batch_flags blorp_flags = 0;
60 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
61 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
62
63 iris_batch_maybe_flush(batch, 1500);
64
65 struct blorp_batch blorp_batch;
66 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
67
68 if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
69 struct pipe_surface *psurf = cso_fb->zsbuf;
70 struct iris_resource *z_res;
71 struct iris_resource *stencil_res;
72 struct blorp_surf z_surf;
73 struct blorp_surf stencil_surf;
74 const unsigned num_layers =
75 psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1;
76
77 iris_get_depth_stencil_resources(psurf->texture, &z_res, &stencil_res);
78
79 if (z_res) {
80 iris_blorp_surf_for_resource(&z_surf, &z_res->base,
81 ISL_AUX_USAGE_NONE, true);
82 }
83
84 if (stencil_res) {
85 iris_blorp_surf_for_resource(&stencil_surf, &stencil_res->base,
86 ISL_AUX_USAGE_NONE, true);
87 }
88
89 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
90 psurf->u.tex.level, psurf->u.tex.first_layer,
91 num_layers, 0, 0,
92 cso_fb->width, cso_fb->height,
93 (buffers & PIPE_CLEAR_DEPTH) != 0, depth,
94 (buffers & PIPE_CLEAR_STENCIL) ? 0xff : 0,
95 stencil);
96 }
97
98 if (buffers & PIPE_CLEAR_COLOR) {
99 /* pipe_color_union and isl_color_value are interchangeable */
100 union isl_color_value *clear_color = (void *) p_color;
101 bool color_write_disable[4] = { false, false, false, false };
102
103 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
104 if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
105 struct pipe_surface *psurf = cso_fb->cbufs[i];
106 struct iris_surface *isurf = (void *) psurf;
107 struct blorp_surf surf;
108
109 iris_blorp_surf_for_resource(&surf, psurf->texture,
110 ISL_AUX_USAGE_NONE, true);
111
112 blorp_clear(&blorp_batch, &surf, isurf->view.format,
113 ISL_SWIZZLE_IDENTITY,
114 psurf->u.tex.level, psurf->u.tex.first_layer,
115 psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
116 0, 0, cso_fb->width, cso_fb->height,
117 *clear_color, color_write_disable);
118 }
119 }
120 }
121
122 blorp_batch_finish(&blorp_batch);
123 }
124
125 static void
126 iris_clear_texture(struct pipe_context *ctx,
127 struct pipe_resource *p_res,
128 unsigned level,
129 const struct pipe_box *box,
130 const void *data)
131 {
132 struct iris_context *ice = (void *) ctx;
133 struct iris_resource *res = (void *) p_res;
134
135 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
136 const struct gen_device_info *devinfo = &batch->screen->devinfo;
137
138 iris_batch_maybe_flush(batch, 1500);
139
140 struct blorp_batch blorp_batch;
141 blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0);
142
143 if (util_format_is_depth_or_stencil(p_res->format)) {
144 const struct util_format_description *fmt_desc =
145 util_format_description(p_res->format);
146
147 struct iris_resource *z_res;
148 struct iris_resource *stencil_res;
149 struct blorp_surf z_surf;
150 struct blorp_surf stencil_surf;
151
152 float depth = 0.0;
153 uint8_t stencil = 0;
154
155 iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
156
157 if (z_res) {
158 iris_blorp_surf_for_resource(&z_surf, &z_res->base,
159 ISL_AUX_USAGE_NONE, true);
160 fmt_desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
161 }
162
163 if (stencil_res) {
164 iris_blorp_surf_for_resource(&stencil_surf, &stencil_res->base,
165 ISL_AUX_USAGE_NONE, true);
166 fmt_desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
167 }
168
169 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
170 level, box->z, box->depth,
171 box->x, box->y,
172 box->x + box->width,
173 box->y + box->height,
174 z_res != NULL, depth,
175 stencil_res ? 0xff : 0, stencil);
176 } else {
177 union isl_color_value color;
178 bool color_write_disable[4] = { false, false, false, false };
179 struct blorp_surf surf;
180 iris_blorp_surf_for_resource(&surf, p_res, ISL_AUX_USAGE_NONE, true);
181
182 enum isl_format format = res->surf.format;
183
184 if (!isl_format_supports_rendering(devinfo, format) &&
185 isl_format_is_rgbx(format))
186 format = isl_format_rgbx_to_rgba(format);
187
188 if (!isl_format_supports_rendering(devinfo, format)) {
189 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
190 // XXX: actually just get_copy_format_for_bpb from BLORP
191 // XXX: don't cut and paste this
192 switch (fmtl->bpb) {
193 case 8: format = ISL_FORMAT_R8_UINT; break;
194 case 16: format = ISL_FORMAT_R8G8_UINT; break;
195 case 24: format = ISL_FORMAT_R8G8B8_UINT; break;
196 case 32: format = ISL_FORMAT_R8G8B8A8_UINT; break;
197 case 48: format = ISL_FORMAT_R16G16B16_UINT; break;
198 case 64: format = ISL_FORMAT_R16G16B16A16_UINT; break;
199 case 96: format = ISL_FORMAT_R32G32B32_UINT; break;
200 case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
201 default:
202 unreachable("Unknown format bpb");
203 }
204 }
205
206 isl_color_value_unpack(&color, format, data);
207
208 blorp_clear(&blorp_batch, &surf, format, ISL_SWIZZLE_IDENTITY,
209 level, box->z, box->depth, box->x, box->y,
210 box->x + box->width, box->y + box->height,
211 color, color_write_disable);
212 }
213
214 blorp_batch_finish(&blorp_batch);
215 }
216
217
218 static void
219 iris_clear_render_target(struct pipe_context *ctx,
220 struct pipe_surface *dst,
221 const union pipe_color_union *color,
222 unsigned dst_x, unsigned dst_y,
223 unsigned width, unsigned height,
224 bool render_condition_enabled)
225 {
226 fprintf(stderr, "XXX: iris_clear_render_target\n");
227 }
228
229 static void
230 iris_clear_depth_stencil(struct pipe_context *ctx,
231 struct pipe_surface *dst,
232 unsigned clear_flags,
233 double depth,
234 unsigned stencil,
235 unsigned dst_x, unsigned dst_y,
236 unsigned width, unsigned height,
237 bool render_condition_enabled)
238 {
239 fprintf(stderr, "XXX: iris_clear_depth_stencil\n");
240 }
241
242 void
243 iris_init_clear_functions(struct pipe_context *ctx)
244 {
245 ctx->clear = iris_clear;
246 ctx->clear_texture = iris_clear_texture;
247 ctx->clear_render_target = iris_clear_render_target;
248 ctx->clear_depth_stencil = iris_clear_depth_stencil;
249 }