src/gallium/drivers/iris/iris_clear.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_format.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "util/ralloc.h"
  33 #include "iris_context.h"
  34 #include "iris_resource.h"
  35 #include "iris_screen.h"
  36 #include "intel/compiler/brw_compiler.h"
  37
  38 static void
  39 clear_color(struct iris_context *ice,
  40             struct pipe_resource *p_res,
  41             unsigned level,
  42             const struct pipe_box *box,
  43             bool render_condition_enabled,
  44             enum isl_format format,
  45             struct isl_swizzle swizzle,
  46             union isl_color_value color)
  47 {
  48    struct iris_resource *res = (void *) p_res;
  49
  50    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
  51    const struct gen_device_info *devinfo = &batch->screen->devinfo;
  52    enum blorp_batch_flags blorp_flags = 0;
  53
  54    if (render_condition_enabled) {
  55       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
  56          return;
  57
  58       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
  59          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
  60    }
  61
  62    iris_batch_maybe_flush(batch, 1500);
  63
  64    struct blorp_batch blorp_batch;
  65    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
  66
  67    bool color_write_disable[4] = { false, false, false, false };
  68    enum isl_aux_usage aux_usage =
  69       iris_resource_render_aux_usage(ice, res, format,
  70                                      false, false);
  71
  72    iris_resource_prepare_render(ice, batch, res, level,
  73                                 box->z, box->depth, aux_usage);
  74
  75    struct blorp_surf surf;
  76    iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level,
  77                                 true);
  78
  79    if (!isl_format_supports_rendering(devinfo, format) &&
  80        isl_format_is_rgbx(format))
  81       format = isl_format_rgbx_to_rgba(format);
  82
  83    blorp_clear(&blorp_batch, &surf, format, swizzle,
  84                level, box->z, box->depth, box->x, box->y,
  85                box->x + box->width, box->y + box->height,
  86                color, color_write_disable);
  87
  88    blorp_batch_finish(&blorp_batch);
  89    iris_flush_and_dirty_for_history(ice, batch, res);
  90
  91    iris_resource_finish_render(ice, res, level,
  92                                box->z, box->depth, aux_usage);
  93 }
  94
  95 static bool
  96 can_fast_clear_depth(struct iris_context *ice,
  97                      struct iris_resource *res,
  98                      unsigned level,
  99                      const struct pipe_box *box,
 100                      float depth)
 101 {
 102    struct pipe_resource *p_res = (void *) res;
 103
 104    /* Check for partial clears */
 105    if (box->x > 0 || box->y > 0 ||
 106        box->width < u_minify(p_res->width0, level) ||
 107        box->height < u_minify(p_res->height0, level)) {
 108       return false;
 109    }
 110
 111    if (!(res->aux.has_hiz & (1 << level)))
 112       return false;
 113
 114    return true;
 115 }
 116
 117 static void
 118 fast_clear_depth(struct iris_context *ice,
 119                  struct iris_resource *res,
 120                  unsigned level,
 121                  const struct pipe_box *box,
 122                  float depth)
 123 {
 124    struct pipe_resource *p_res = (void *) res;
 125    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 126
 127    /* Quantize the clear value to what can be stored in the actual depth
 128     * buffer.  This makes the following check more accurate because it now
 129     * checks if the actual depth bits will match.  It also prevents us from
 130     * getting a too-accurate depth value during depth testing or when sampling
 131     * with HiZ enabled.
 132     */
 133    const unsigned nbits = p_res->format == PIPE_FORMAT_Z16_UNORM ? 16 : 24;
 134    const uint32_t depth_max = (1 << nbits) - 1;
 135    depth = p_res->format == PIPE_FORMAT_Z32_FLOAT ? depth :
 136       (unsigned)(depth * depth_max) / (float)depth_max;
 137
 138    /* If we're clearing to a new clear value, then we need to resolve any clear
 139     * flags out of the HiZ buffer into the real depth buffer.
 140     */
 141    if (res->aux.clear_color.f32[0] != depth) {
 142       for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) {
 143          if (!(res->aux.has_hiz & (1 << res_level)))
 144             continue;
 145
 146          const unsigned level_layers =
 147             iris_get_num_logical_layers(res, res_level);
 148          for (unsigned layer = 0; layer < level_layers; layer++) {
 149             if (res_level == level &&
 150                 layer >= box->z &&
 151                 layer < box->z + box->depth) {
 152                /* We're going to clear this layer anyway.  Leave it alone. */
 153                continue;
 154             }
 155
 156             enum isl_aux_state aux_state =
 157                iris_resource_get_aux_state(res, res_level, layer);
 158
 159             if (aux_state != ISL_AUX_STATE_CLEAR &&
 160                 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
 161                /* This slice doesn't have any fast-cleared bits. */
 162                continue;
 163             }
 164
 165             /* If we got here, then the level may have fast-clear bits that
 166              * use the old clear value.  We need to do a depth resolve to get
 167              * rid of their use of the clear value before we can change it.
 168              * Fortunately, few applications ever change their depth clear
 169              * value so this shouldn't happen often.
 170              */
 171             iris_hiz_exec(ice, batch, res, res_level, layer, 1,
 172                           ISL_AUX_OP_FULL_RESOLVE);
 173             iris_resource_set_aux_state(ice, res, res_level, layer, 1,
 174                                         ISL_AUX_STATE_RESOLVED);
 175          }
 176       }
 177       const union isl_color_value clear_color = { .f32 = {depth, } };
 178       iris_resource_set_clear_color(ice, res, clear_color);
 179    }
 180
 181    for (unsigned l = 0; l < box->depth; l++) {
 182       enum isl_aux_state aux_state =
 183          iris_resource_get_aux_state(res, level, box->z + l);
 184       if (aux_state != ISL_AUX_STATE_CLEAR) {
 185          iris_hiz_exec(ice, batch, res, level,
 186                        box->z + l, 1, ISL_AUX_OP_FAST_CLEAR);
 187       }
 188    }
 189
 190    iris_resource_set_aux_state(ice, res, level, box->z, box->depth,
 191                                ISL_AUX_STATE_CLEAR);
 192    ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
 193 }
 194
 195 static void
 196 clear_depth_stencil(struct iris_context *ice,
 197                     struct pipe_resource *p_res,
 198                     unsigned level,
 199                     const struct pipe_box *box,
 200                     bool render_condition_enabled,
 201                     bool clear_depth,
 202                     bool clear_stencil,
 203                     float depth,
 204                     uint8_t stencil)
 205 {
 206    struct iris_resource *res = (void *) p_res;
 207
 208    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 209    enum blorp_batch_flags blorp_flags = 0;
 210
 211    if (render_condition_enabled) {
 212       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
 213          return;
 214
 215       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
 216          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
 217    }
 218
 219    iris_batch_maybe_flush(batch, 1500);
 220
 221    struct iris_resource *z_res;
 222    struct iris_resource *stencil_res;
 223    struct blorp_surf z_surf;
 224    struct blorp_surf stencil_surf;
 225
 226    iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
 227    if (z_res && clear_depth &&
 228        can_fast_clear_depth(ice, z_res, level, box, depth)) {
 229       fast_clear_depth(ice, z_res, level, box, depth);
 230       iris_flush_and_dirty_for_history(ice, batch, res);
 231       clear_depth = false;
 232       z_res = false;
 233    }
 234
 235    /* At this point, we might have fast cleared the depth buffer. So if there's
 236     * no stencil clear pending, return early.
 237     */
 238    if (!(clear_depth || clear_stencil)) {
 239       return;
 240    }
 241
 242    if (z_res) {
 243       iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth);
 244       iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base,
 245                                    z_res->aux.usage, level, true);
 246    }
 247
 248    struct blorp_batch blorp_batch;
 249    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
 250
 251    if (stencil_res) {
 252       iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf,
 253                                    &stencil_res->base, stencil_res->aux.usage,
 254                                    level, true);
 255    }
 256
 257    blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
 258                              level, box->z, box->depth,
 259                              box->x, box->y,
 260                              box->x + box->width,
 261                              box->y + box->height,
 262                              clear_depth && z_res, depth,
 263                              clear_stencil && stencil_res ? 0xff : 0, stencil);
 264
 265    blorp_batch_finish(&blorp_batch);
 266    iris_flush_and_dirty_for_history(ice, batch, res);
 267
 268    if (z_res) {
 269       iris_resource_finish_depth(ice, z_res, level,
 270                                  box->z, box->depth, true);
 271    }
 272 }
 273
 274 /**
 275  * The pipe->clear() driver hook.
 276  *
 277  * This clears buffers attached to the current draw framebuffer.
 278  */
 279 static void
 280 iris_clear(struct pipe_context *ctx,
 281            unsigned buffers,
 282            const union pipe_color_union *p_color,
 283            double depth,
 284            unsigned stencil)
 285 {
 286    struct iris_context *ice = (void *) ctx;
 287    struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
 288
 289    assert(buffers != 0);
 290
 291    if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
 292       struct pipe_surface *psurf = cso_fb->zsbuf;
 293       struct pipe_box box = {
 294          .width = cso_fb->width,
 295          .height = cso_fb->height,
 296          .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 297          .z = psurf->u.tex.first_layer,
 298       };
 299
 300       clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true,
 301                           buffers & PIPE_CLEAR_DEPTH,
 302                           buffers & PIPE_CLEAR_STENCIL,
 303                           depth, stencil);
 304    }
 305
 306    if (buffers & PIPE_CLEAR_COLOR) {
 307       /* pipe_color_union and isl_color_value are interchangeable */
 308       union isl_color_value *color = (void *) p_color;
 309
 310       for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
 311          if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
 312             struct pipe_surface *psurf = cso_fb->cbufs[i];
 313             struct iris_surface *isurf = (void *) psurf;
 314             struct pipe_box box = {
 315                .width = cso_fb->width,
 316                .height = cso_fb->height,
 317                .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 318                .z = psurf->u.tex.first_layer,
 319             };
 320
 321             clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 322                         true, isurf->view.format, isurf->view.swizzle,
 323                         *color);
 324          }
 325       }
 326    }
 327 }
 328
 329 /**
 330  * The pipe->clear_texture() driver hook.
 331  *
 332  * This clears the given texture resource.
 333  */
 334 static void
 335 iris_clear_texture(struct pipe_context *ctx,
 336                    struct pipe_resource *p_res,
 337                    unsigned level,
 338                    const struct pipe_box *box,
 339                    const void *data)
 340 {
 341    struct iris_context *ice = (void *) ctx;
 342    struct iris_screen *screen = (void *) ctx->screen;
 343    const struct gen_device_info *devinfo = &screen->devinfo;
 344
 345    if (util_format_is_depth_or_stencil(p_res->format)) {
 346       const struct util_format_description *fmt_desc =
 347          util_format_description(p_res->format);
 348
 349       float depth = 0.0;
 350       uint8_t stencil = 0;
 351
 352       if (fmt_desc->unpack_z_float)
 353          fmt_desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
 354
 355       if (fmt_desc->unpack_s_8uint)
 356          fmt_desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
 357
 358       clear_depth_stencil(ice, p_res, level, box, true, true, true,
 359                           depth, stencil);
 360    } else {
 361       union isl_color_value color;
 362       struct iris_resource *res = (void *) p_res;
 363       enum isl_format format = res->surf.format;
 364
 365       if (!isl_format_supports_rendering(devinfo, format)) {
 366          const struct isl_format_layout *fmtl = isl_format_get_layout(format);
 367          // XXX: actually just get_copy_format_for_bpb from BLORP
 368          // XXX: don't cut and paste this
 369          switch (fmtl->bpb) {
 370          case 8:   format = ISL_FORMAT_R8_UINT;           break;
 371          case 16:  format = ISL_FORMAT_R8G8_UINT;         break;
 372          case 24:  format = ISL_FORMAT_R8G8B8_UINT;       break;
 373          case 32:  format = ISL_FORMAT_R8G8B8A8_UINT;     break;
 374          case 48:  format = ISL_FORMAT_R16G16B16_UINT;    break;
 375          case 64:  format = ISL_FORMAT_R16G16B16A16_UINT; break;
 376          case 96:  format = ISL_FORMAT_R32G32B32_UINT;    break;
 377          case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
 378          default:
 379             unreachable("Unknown format bpb");
 380          }
 381
 382          /* No aux surfaces for non-renderable surfaces */
 383          assert(res->aux.usage == ISL_AUX_USAGE_NONE);
 384       }
 385
 386       isl_color_value_unpack(&color, format, data);
 387
 388       clear_color(ice, p_res, level, box, true, format,
 389                   ISL_SWIZZLE_IDENTITY, color);
 390    }
 391 }
 392
 393 /**
 394  * The pipe->clear_render_target() driver hook.
 395  *
 396  * This clears the given render target surface.
 397  */
 398 static void
 399 iris_clear_render_target(struct pipe_context *ctx,
 400                          struct pipe_surface *psurf,
 401                          const union pipe_color_union *p_color,
 402                          unsigned dst_x, unsigned dst_y,
 403                          unsigned width, unsigned height,
 404                          bool render_condition_enabled)
 405 {
 406    struct iris_context *ice = (void *) ctx;
 407    struct iris_surface *isurf = (void *) psurf;
 408    struct pipe_box box = {
 409       .x = dst_x,
 410       .y = dst_y,
 411       .z = psurf->u.tex.first_layer,
 412       .width = width,
 413       .height = height,
 414       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 415    };
 416
 417    /* pipe_color_union and isl_color_value are interchangeable */
 418    union isl_color_value *color = (void *) p_color;
 419
 420    clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 421                render_condition_enabled,
 422                isurf->view.format, isurf->view.swizzle, *color);
 423 }
 424
 425 /**
 426  * The pipe->clear_depth_stencil() driver hook.
 427  *
 428  * This clears the given depth/stencil surface.
 429  */
 430 static void
 431 iris_clear_depth_stencil(struct pipe_context *ctx,
 432                          struct pipe_surface *psurf,
 433                          unsigned flags,
 434                          double depth,
 435                          unsigned stencil,
 436                          unsigned dst_x, unsigned dst_y,
 437                          unsigned width, unsigned height,
 438                          bool render_condition_enabled)
 439 {
 440    struct iris_context *ice = (void *) ctx;
 441    struct pipe_box box = {
 442       .x = dst_x,
 443       .y = dst_y,
 444       .z = psurf->u.tex.first_layer,
 445       .width = width,
 446       .height = height,
 447       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 448    };
 449
 450    assert(util_format_is_depth_or_stencil(psurf->texture->format));
 451
 452    clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box,
 453                        render_condition_enabled,
 454                        flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL,
 455                        depth, stencil);
 456 }
 457
 458 void
 459 iris_init_clear_functions(struct pipe_context *ctx)
 460 {
 461    ctx->clear = iris_clear;
 462    ctx->clear_texture = iris_clear_texture;
 463    ctx->clear_render_target = iris_clear_render_target;
 464    ctx->clear_depth_stencil = iris_clear_depth_stencil;
 465 }