src/gallium/drivers/iris/iris_clear.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_format.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "util/ralloc.h"
  33 #include "iris_context.h"
  34 #include "iris_resource.h"
  35 #include "iris_screen.h"
  36 #include "intel/compiler/brw_compiler.h"
  37
  38 static void
  39 clear_color(struct iris_context *ice,
  40             struct pipe_resource *p_res,
  41             unsigned level,
  42             const struct pipe_box *box,
  43             bool render_condition_enabled,
  44             enum isl_format format,
  45             union isl_color_value color)
  46 {
  47    struct iris_resource *res = (void *) p_res;
  48
  49    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
  50    const struct gen_device_info *devinfo = &batch->screen->devinfo;
  51    enum blorp_batch_flags blorp_flags = 0;
  52
  53    if (render_condition_enabled) {
  54       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
  55          return;
  56
  57       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
  58          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
  59    }
  60
  61    iris_batch_maybe_flush(batch, 1500);
  62
  63    struct blorp_batch blorp_batch;
  64    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
  65
  66    bool color_write_disable[4] = { false, false, false, false };
  67    enum isl_aux_usage aux_usage =
  68       iris_resource_render_aux_usage(ice, res, format,
  69                                      false, false);
  70
  71    iris_resource_prepare_render(ice, batch, res, level,
  72                                 box->z, box->depth, aux_usage);
  73
  74    struct blorp_surf surf;
  75    iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level,
  76                                 true);
  77
  78    if (!isl_format_supports_rendering(devinfo, format) &&
  79        isl_format_is_rgbx(format))
  80       format = isl_format_rgbx_to_rgba(format);
  81
  82    blorp_clear(&blorp_batch, &surf, format, ISL_SWIZZLE_IDENTITY,
  83                level, box->z, box->depth, box->x, box->y,
  84                box->x + box->width, box->y + box->height,
  85                color, color_write_disable);
  86
  87    blorp_batch_finish(&blorp_batch);
  88    iris_flush_and_dirty_for_history(ice, batch, res);
  89
  90    iris_resource_finish_render(ice, res, level,
  91                                box->z, box->depth, aux_usage);
  92 }
  93
  94
  95 static void
  96 clear_depth_stencil(struct iris_context *ice,
  97                     struct pipe_resource *p_res,
  98                     unsigned level,
  99                     const struct pipe_box *box,
 100                     bool render_condition_enabled,
 101                     bool clear_depth,
 102                     bool clear_stencil,
 103                     float depth,
 104                     uint8_t stencil)
 105 {
 106    struct iris_resource *res = (void *) p_res;
 107
 108    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 109    enum blorp_batch_flags blorp_flags = 0;
 110
 111    if (render_condition_enabled) {
 112       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
 113          return;
 114
 115       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
 116          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
 117    }
 118
 119    iris_batch_maybe_flush(batch, 1500);
 120
 121    struct blorp_batch blorp_batch;
 122    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
 123
 124    struct iris_resource *z_res;
 125    struct iris_resource *stencil_res;
 126    struct blorp_surf z_surf;
 127    struct blorp_surf stencil_surf;
 128
 129    iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
 130
 131    if (z_res) {
 132       iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth);
 133       iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base,
 134                                    z_res->aux.usage, level, true);
 135    }
 136
 137    if (stencil_res) {
 138       iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf,
 139                                    &stencil_res->base, stencil_res->aux.usage,
 140                                    level, true);
 141    }
 142
 143    blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
 144                              level, box->z, box->depth,
 145                              box->x, box->y,
 146                              box->x + box->width,
 147                              box->y + box->height,
 148                              clear_depth && z_res, depth,
 149                              clear_stencil && stencil_res ? 0xff : 0, stencil);
 150
 151    blorp_batch_finish(&blorp_batch);
 152    iris_flush_and_dirty_for_history(ice, batch, res);
 153
 154    if (z_res) {
 155       iris_resource_finish_depth(ice, z_res, level,
 156                                  box->z, box->depth, true);
 157    }
 158 }
 159
 160 /**
 161  * The pipe->clear() driver hook.
 162  *
 163  * This clears buffers attached to the current draw framebuffer.
 164  */
 165 static void
 166 iris_clear(struct pipe_context *ctx,
 167            unsigned buffers,
 168            const union pipe_color_union *p_color,
 169            double depth,
 170            unsigned stencil)
 171 {
 172    struct iris_context *ice = (void *) ctx;
 173    struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
 174
 175    assert(buffers != 0);
 176
 177    if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
 178       struct pipe_surface *psurf = cso_fb->zsbuf;
 179       struct pipe_box box = {
 180          .width = cso_fb->width,
 181          .height = cso_fb->height,
 182          .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 183          .z = psurf->u.tex.first_layer,
 184       };
 185
 186       clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true,
 187                           buffers & PIPE_CLEAR_DEPTH,
 188                           buffers & PIPE_CLEAR_STENCIL,
 189                           depth, stencil);
 190    }
 191
 192    if (buffers & PIPE_CLEAR_COLOR) {
 193       /* pipe_color_union and isl_color_value are interchangeable */
 194       union isl_color_value *color = (void *) p_color;
 195
 196       for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
 197          if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
 198             struct pipe_surface *psurf = cso_fb->cbufs[i];
 199             struct iris_surface *isurf = (void *) psurf;
 200             struct pipe_box box = {
 201                .width = cso_fb->width,
 202                .height = cso_fb->height,
 203                .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 204                .z = psurf->u.tex.first_layer,
 205             };
 206
 207             clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 208                         true, isurf->view.format, *color);
 209          }
 210       }
 211    }
 212 }
 213
 214 /**
 215  * The pipe->clear_texture() driver hook.
 216  *
 217  * This clears the given texture resource.
 218  */
 219 static void
 220 iris_clear_texture(struct pipe_context *ctx,
 221                    struct pipe_resource *p_res,
 222                    unsigned level,
 223                    const struct pipe_box *box,
 224                    const void *data)
 225 {
 226    struct iris_context *ice = (void *) ctx;
 227    struct iris_screen *screen = (void *) ctx->screen;
 228    const struct gen_device_info *devinfo = &screen->devinfo;
 229
 230    if (util_format_is_depth_or_stencil(p_res->format)) {
 231       const struct util_format_description *fmt_desc =
 232          util_format_description(p_res->format);
 233
 234       float depth = 0.0;
 235       uint8_t stencil = 0;
 236
 237       if (fmt_desc->unpack_z_float)
 238          fmt_desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
 239
 240       if (fmt_desc->unpack_s_8uint)
 241          fmt_desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
 242
 243       clear_depth_stencil(ice, p_res, level, box, true, true, true,
 244                           depth, stencil);
 245    } else {
 246       union isl_color_value color;
 247       struct iris_resource *res = (void *) p_res;
 248       enum isl_format format = res->surf.format;
 249
 250       if (!isl_format_supports_rendering(devinfo, format)) {
 251          const struct isl_format_layout *fmtl = isl_format_get_layout(format);
 252          // XXX: actually just get_copy_format_for_bpb from BLORP
 253          // XXX: don't cut and paste this
 254          switch (fmtl->bpb) {
 255          case 8:   format = ISL_FORMAT_R8_UINT;           break;
 256          case 16:  format = ISL_FORMAT_R8G8_UINT;         break;
 257          case 24:  format = ISL_FORMAT_R8G8B8_UINT;       break;
 258          case 32:  format = ISL_FORMAT_R8G8B8A8_UINT;     break;
 259          case 48:  format = ISL_FORMAT_R16G16B16_UINT;    break;
 260          case 64:  format = ISL_FORMAT_R16G16B16A16_UINT; break;
 261          case 96:  format = ISL_FORMAT_R32G32B32_UINT;    break;
 262          case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
 263          default:
 264             unreachable("Unknown format bpb");
 265          }
 266
 267          /* No aux surfaces for non-renderable surfaces */
 268          assert(res->aux.usage == ISL_AUX_USAGE_NONE);
 269       }
 270
 271       isl_color_value_unpack(&color, format, data);
 272
 273       clear_color(ice, p_res, level, box, true, format, color);
 274    }
 275 }
 276
 277 /**
 278  * The pipe->clear_render_target() driver hook.
 279  *
 280  * This clears the given render target surface.
 281  */
 282 static void
 283 iris_clear_render_target(struct pipe_context *ctx,
 284                          struct pipe_surface *psurf,
 285                          const union pipe_color_union *p_color,
 286                          unsigned dst_x, unsigned dst_y,
 287                          unsigned width, unsigned height,
 288                          bool render_condition_enabled)
 289 {
 290    struct iris_context *ice = (void *) ctx;
 291    struct iris_surface *isurf = (void *) psurf;
 292    struct pipe_box box = {
 293       .x = dst_x,
 294       .y = dst_y,
 295       .z = psurf->u.tex.first_layer,
 296       .width = width,
 297       .height = height,
 298       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 299    };
 300
 301    /* pipe_color_union and isl_color_value are interchangeable */
 302    union isl_color_value *color = (void *) p_color;
 303
 304    clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 305                render_condition_enabled,
 306                isurf->view.format, *color);
 307 }
 308
 309 /**
 310  * The pipe->clear_depth_stencil() driver hook.
 311  *
 312  * This clears the given depth/stencil surface.
 313  */
 314 static void
 315 iris_clear_depth_stencil(struct pipe_context *ctx,
 316                          struct pipe_surface *psurf,
 317                          unsigned flags,
 318                          double depth,
 319                          unsigned stencil,
 320                          unsigned dst_x, unsigned dst_y,
 321                          unsigned width, unsigned height,
 322                          bool render_condition_enabled)
 323 {
 324    struct iris_context *ice = (void *) ctx;
 325    struct pipe_box box = {
 326       .x = dst_x,
 327       .y = dst_y,
 328       .z = psurf->u.tex.first_layer,
 329       .width = width,
 330       .height = height,
 331       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 332    };
 333
 334    assert(util_format_is_depth_or_stencil(psurf->texture->format));
 335
 336    clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box,
 337                        render_condition_enabled,
 338                        flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL,
 339                        depth, stencil);
 340 }
 341
 342 void
 343 iris_init_clear_functions(struct pipe_context *ctx)
 344 {
 345    ctx->clear = iris_clear;
 346    ctx->clear_texture = iris_clear_texture;
 347    ctx->clear_render_target = iris_clear_render_target;
 348    ctx->clear_depth_stencil = iris_clear_depth_stencil;
 349 }