2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
39 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
40 enum isl_format format
,
41 const union isl_color_value color
)
43 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
44 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
46 if (isl_format_has_int_channel(format
)) {
47 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s\n",
48 isl_format_get_name(format
));
52 for (int i
= 0; i
< 4; i
++) {
53 if (!isl_format_has_color_component(format
, i
)) {
57 if (devinfo
->gen
< 9 &&
58 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
67 can_fast_clear_color(struct iris_context
*ice
,
68 struct pipe_resource
*p_res
,
70 const struct pipe_box
*box
,
71 enum isl_format render_format
,
72 union isl_color_value color
)
74 struct iris_resource
*res
= (void *) p_res
;
76 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
79 if (!isl_aux_usage_has_fast_clears(res
->aux
.usage
))
82 /* Check for partial clear */
83 if (box
->x
> 0 || box
->y
> 0 ||
84 box
->width
< minify(p_res
->width0
, level
) ||
85 box
->height
< minify(p_res
->height0
, level
)) {
89 /* Disable sRGB fast-clears for non-0/1 color values. For texturing and
90 * draw calls, HW expects the clear color to be in two different color
91 * spaces after sRGB fast-clears - sRGB in the former and linear in the
92 * latter. By limiting the allowable values to 0/1, both color space
93 * requirements are satisfied.
95 if (isl_format_is_srgb(render_format
) &&
96 !isl_color_value_is_zero_one(color
, render_format
)) {
100 /* We store clear colors as floats or uints as needed. If there are
101 * texture views in play, the formats will not properly be respected
102 * during resolves because the resolve operations only know about the
103 * resource and not the renderbuffer.
105 if (!iris_render_formats_color_compatible(render_format
, res
->surf
.format
,
110 /* XXX: if (irb->mt->supports_fast_clear)
111 * see intel_miptree_create_for_dri_image()
114 if (!iris_is_color_fast_clear_compatible(ice
, res
->surf
.format
, color
))
120 static union isl_color_value
121 convert_fast_clear_color(struct iris_context
*ice
,
122 struct iris_resource
*res
,
123 const union isl_color_value color
)
125 union isl_color_value override_color
= color
;
126 struct pipe_resource
*p_res
= (void *) res
;
128 const enum pipe_format format
= p_res
->format
;
129 const struct util_format_description
*desc
=
130 util_format_description(format
);
131 unsigned colormask
= util_format_colormask(desc
);
133 if (util_format_is_intensity(format
) ||
134 util_format_is_luminance(format
) ||
135 util_format_is_luminance_alpha(format
)) {
136 override_color
.u32
[1] = override_color
.u32
[0];
137 override_color
.u32
[2] = override_color
.u32
[0];
138 if (util_format_is_intensity(format
))
139 override_color
.u32
[3] = override_color
.u32
[0];
141 for (int chan
= 0; chan
< 3; chan
++) {
142 if (!(colormask
& (1 << chan
)))
143 override_color
.u32
[chan
] = 0;
147 if (util_format_is_unorm(format
)) {
148 for (int i
= 0; i
< 4; i
++)
149 override_color
.f32
[i
] = SATURATE(override_color
.f32
[i
]);
150 } else if (util_format_is_snorm(format
)) {
151 for (int i
= 0; i
< 4; i
++)
152 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
153 } else if (util_format_is_pure_uint(format
)) {
154 for (int i
= 0; i
< 4; i
++) {
155 unsigned bits
= util_format_get_component_bits(
156 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
158 uint32_t max
= (1u << bits
) - 1;
159 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
162 } else if (util_format_is_pure_sint(format
)) {
163 for (int i
= 0; i
< 4; i
++) {
164 unsigned bits
= util_format_get_component_bits(
165 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
168 int32_t max
= (1 << (bits
- 1)) - 1;
169 int32_t min
= -(1 << (bits
- 1));
170 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
173 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
174 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
175 /* these packed float formats only store unsigned values */
176 for (int i
= 0; i
< 4; i
++)
177 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
180 if (!(colormask
& 1 << 3)) {
181 if (util_format_is_pure_integer(format
))
182 override_color
.u32
[3] = 1;
184 override_color
.f32
[3] = 1.0f
;
187 return override_color
;
191 fast_clear_color(struct iris_context
*ice
,
192 struct iris_resource
*res
,
194 const struct pipe_box
*box
,
195 enum isl_format format
,
196 union isl_color_value color
,
197 enum blorp_batch_flags blorp_flags
)
199 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
200 struct pipe_resource
*p_res
= (void *) res
;
201 const enum isl_aux_state aux_state
=
202 iris_resource_get_aux_state(res
, level
, box
->z
);
204 color
= convert_fast_clear_color(ice
, res
, color
);
206 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
210 /* We decided that we are going to fast clear, and the color is
211 * changing. But if we have a predicate bit set, the predication
212 * affects whether we should clear or not, and if we shouldn't, we
213 * also shouldn't update the clear color.
215 * However, we can't simply predicate-update the clear color (the
216 * commands don't support that). And we would lose track of the
217 * color, preventing us from doing some optimizations later.
219 * Since changing the clear color when the predication bit is enabled
220 * is not something that should happen often, we stall on the CPU here
221 * to resolve the predication, and then proceed.
223 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
224 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
227 /* If we are clearing to a new clear value, we need to resolve fast
228 * clears from other levels/layers first, since we can't have different
229 * levels/layers with different fast clear colors.
231 for (unsigned res_lvl
= 0; res_lvl
< res
->surf
.levels
; res_lvl
++) {
232 const unsigned level_layers
=
233 iris_get_num_logical_layers(res
, res_lvl
);
234 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
235 if (res_lvl
== level
&&
237 layer
< box
->z
+ box
->depth
) {
238 /* We're going to clear this layer anyway. Leave it alone. */
242 enum isl_aux_state aux_state
=
243 iris_resource_get_aux_state(res
, res_lvl
, layer
);
245 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
246 aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
&&
247 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
248 /* This slice doesn't have any fast-cleared bits. */
252 /* If we got here, then the level may have fast-clear bits that use
253 * the old clear value. We need to do a color resolve to get rid
254 * of their use of the clear color before we can change it.
255 * Fortunately, few applications ever change their clear color at
256 * different levels/layers, so this shouldn't happen often.
258 iris_resource_prepare_access(ice
, res
,
259 res_lvl
, 1, layer
, 1,
262 perf_debug(&ice
->dbg
,
263 "Resolving resource (%p) level %d, layer %d: color changing from "
264 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
265 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
267 res
->aux
.clear_color
.f32
[0],
268 res
->aux
.clear_color
.f32
[1],
269 res
->aux
.clear_color
.f32
[2],
270 res
->aux
.clear_color
.f32
[3],
271 color
.f32
[0], color
.f32
[1], color
.f32
[2], color
.f32
[3]);
276 iris_resource_set_clear_color(ice
, res
, color
);
278 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
279 * changed, the clear is redundant and can be skipped.
281 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
284 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
286 * "Any transition from any value in {Clear, Render, Resolve} to a
287 * different value in {Clear, Render, Resolve} requires end of pipe
290 * In other words, fast clear ops are not properly synchronized with
291 * other drawing. We need to use a PIPE_CONTROL to ensure that the
292 * contents of the previous draw hit the render target before we resolve
293 * and again afterwards to ensure that the resolve is complete before we
294 * do any more regular drawing.
296 iris_emit_end_of_pipe_sync(batch
,
297 "fast clear: pre-flush",
298 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
300 iris_batch_sync_region_start(batch
);
302 /* If we reach this point, we need to fast clear to change the state to
303 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
305 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
307 struct blorp_batch blorp_batch
;
308 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
310 struct blorp_surf surf
;
311 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
312 p_res
, res
->aux
.usage
, level
, true);
314 blorp_fast_clear(&blorp_batch
, &surf
, format
, ISL_SWIZZLE_IDENTITY
,
315 level
, box
->z
, box
->depth
,
316 box
->x
, box
->y
, box
->x
+ box
->width
,
317 box
->y
+ box
->height
);
318 blorp_batch_finish(&blorp_batch
);
319 iris_emit_end_of_pipe_sync(batch
,
320 "fast clear: post flush",
321 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
322 iris_batch_sync_region_end(batch
);
324 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
325 box
->depth
, ISL_AUX_STATE_CLEAR
);
326 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
327 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
332 clear_color(struct iris_context
*ice
,
333 struct pipe_resource
*p_res
,
335 const struct pipe_box
*box
,
336 bool render_condition_enabled
,
337 enum isl_format format
,
338 struct isl_swizzle swizzle
,
339 union isl_color_value color
)
341 struct iris_resource
*res
= (void *) p_res
;
343 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
344 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
345 enum blorp_batch_flags blorp_flags
= 0;
347 if (render_condition_enabled
) {
348 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
351 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
352 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
355 if (p_res
->target
== PIPE_BUFFER
)
356 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
358 iris_batch_maybe_flush(batch
, 1500);
360 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
362 if (can_fast_clear
) {
363 fast_clear_color(ice
, res
, level
, box
, format
, color
,
368 bool color_write_disable
[4] = { false, false, false, false };
369 enum isl_aux_usage aux_usage
=
370 iris_resource_render_aux_usage(ice
, res
, format
, false);
372 iris_resource_prepare_render(ice
, batch
, res
, level
,
373 box
->z
, box
->depth
, aux_usage
);
374 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_RENDER_WRITE
);
376 struct blorp_surf surf
;
377 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
378 p_res
, aux_usage
, level
, true);
380 iris_batch_sync_region_start(batch
);
382 struct blorp_batch blorp_batch
;
383 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
385 if (!isl_format_supports_rendering(devinfo
, format
) &&
386 isl_format_is_rgbx(format
))
387 format
= isl_format_rgbx_to_rgba(format
);
389 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
390 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
391 box
->x
+ box
->width
, box
->y
+ box
->height
,
392 color
, color_write_disable
);
394 blorp_batch_finish(&blorp_batch
);
395 iris_batch_sync_region_end(batch
);
397 iris_flush_and_dirty_for_history(ice
, batch
, res
,
398 PIPE_CONTROL_RENDER_TARGET_FLUSH
,
399 "cache history: post color clear");
401 iris_resource_finish_render(ice
, res
, level
,
402 box
->z
, box
->depth
, aux_usage
);
406 can_fast_clear_depth(struct iris_context
*ice
,
407 struct iris_resource
*res
,
409 const struct pipe_box
*box
,
412 struct pipe_resource
*p_res
= (void *) res
;
413 struct pipe_context
*ctx
= (void *) ice
;
414 struct iris_screen
*screen
= (void *) ctx
->screen
;
415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
417 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
420 /* Check for partial clears */
421 if (box
->x
> 0 || box
->y
> 0 ||
422 box
->width
< u_minify(p_res
->width0
, level
) ||
423 box
->height
< u_minify(p_res
->height0
, level
)) {
427 if (!(res
->aux
.has_hiz
& (1 << level
)))
430 return blorp_can_hiz_clear_depth(devinfo
, &res
->surf
, res
->aux
.usage
,
431 level
, box
->z
, box
->x
, box
->y
,
433 box
->y
+ box
->height
);
437 fast_clear_depth(struct iris_context
*ice
,
438 struct iris_resource
*res
,
440 const struct pipe_box
*box
,
443 struct pipe_resource
*p_res
= (void *) res
;
444 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
446 /* Quantize the clear value to what can be stored in the actual depth
447 * buffer. This makes the following check more accurate because it now
448 * checks if the actual depth bits will match. It also prevents us from
449 * getting a too-accurate depth value during depth testing or when sampling
452 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
453 const uint32_t depth_max
= (1 << nbits
) - 1;
454 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
455 (unsigned)(depth
* depth_max
) / (float)depth_max
;
457 bool update_clear_depth
= false;
459 /* If we're clearing to a new clear value, then we need to resolve any clear
460 * flags out of the HiZ buffer into the real depth buffer.
462 if (res
->aux
.clear_color
.f32
[0] != depth
) {
463 /* We decided that we are going to fast clear, and the color is
464 * changing. But if we have a predicate bit set, the predication
465 * affects whether we should clear or not, and if we shouldn't, we
466 * also shouldn't update the clear color.
468 * However, we can't simply predicate-update the clear color (the
469 * commands don't support that). And we would lose track of the
470 * color, preventing us from doing some optimizations later.
472 * For depth clears, things are even more complicated, because here we
473 * resolve the other levels/layers if they have a different color than
474 * the current one. That resolve can be predicated, but we also set those
475 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
476 * Keeping track of the aux state when predication is involved is just
477 * even more complex, so the easiest thing to do when the fast clear
478 * depth is changing is to stall on the CPU and resolve the predication.
480 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
481 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
484 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
485 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
488 const unsigned level_layers
=
489 iris_get_num_logical_layers(res
, res_level
);
490 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
491 if (res_level
== level
&&
493 layer
< box
->z
+ box
->depth
) {
494 /* We're going to clear this layer anyway. Leave it alone. */
498 enum isl_aux_state aux_state
=
499 iris_resource_get_aux_state(res
, res_level
, layer
);
501 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
502 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
503 /* This slice doesn't have any fast-cleared bits. */
507 /* If we got here, then the level may have fast-clear bits that
508 * use the old clear value. We need to do a depth resolve to get
509 * rid of their use of the clear value before we can change it.
510 * Fortunately, few applications ever change their depth clear
511 * value so this shouldn't happen often.
513 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
514 ISL_AUX_OP_FULL_RESOLVE
, false);
515 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
516 ISL_AUX_STATE_RESOLVED
);
519 const union isl_color_value clear_value
= { .f32
= {depth
, } };
520 iris_resource_set_clear_color(ice
, res
, clear_value
);
521 update_clear_depth
= true;
524 for (unsigned l
= 0; l
< box
->depth
; l
++) {
525 enum isl_aux_state aux_state
=
526 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
527 if (update_clear_depth
|| aux_state
!= ISL_AUX_STATE_CLEAR
) {
528 if (aux_state
== ISL_AUX_STATE_CLEAR
) {
529 perf_debug(&ice
->dbg
, "Performing HiZ clear just to update the "
530 "depth clear value\n");
532 iris_hiz_exec(ice
, batch
, res
, level
,
533 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
538 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
539 ISL_AUX_STATE_CLEAR
);
540 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
544 clear_depth_stencil(struct iris_context
*ice
,
545 struct pipe_resource
*p_res
,
547 const struct pipe_box
*box
,
548 bool render_condition_enabled
,
554 struct iris_resource
*res
= (void *) p_res
;
556 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
557 enum blorp_batch_flags blorp_flags
= 0;
559 if (render_condition_enabled
) {
560 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
563 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
564 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
567 iris_batch_maybe_flush(batch
, 1500);
569 struct iris_resource
*z_res
;
570 struct iris_resource
*stencil_res
;
571 struct blorp_surf z_surf
;
572 struct blorp_surf stencil_surf
;
574 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
575 if (z_res
&& clear_depth
&&
576 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
577 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
578 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
579 "cache history: post fast Z clear");
584 /* At this point, we might have fast cleared the depth buffer. So if there's
585 * no stencil clear pending, return early.
587 if (!(clear_depth
|| (clear_stencil
&& stencil_res
))) {
591 if (clear_depth
&& z_res
) {
592 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
593 iris_emit_buffer_barrier_for(batch
, z_res
->bo
, IRIS_DOMAIN_DEPTH_WRITE
);
594 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
595 &z_surf
, &z_res
->base
, z_res
->aux
.usage
,
599 uint8_t stencil_mask
= clear_stencil
&& stencil_res
? 0xff : 0;
601 iris_resource_prepare_access(ice
, stencil_res
, level
, 1, box
->z
,
602 box
->depth
, stencil_res
->aux
.usage
, false);
603 iris_emit_buffer_barrier_for(batch
, stencil_res
->bo
,
604 IRIS_DOMAIN_DEPTH_WRITE
);
605 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
606 &stencil_surf
, &stencil_res
->base
,
607 stencil_res
->aux
.usage
, level
, true);
610 iris_batch_sync_region_start(batch
);
612 struct blorp_batch blorp_batch
;
613 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
615 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
616 level
, box
->z
, box
->depth
,
619 box
->y
+ box
->height
,
620 clear_depth
&& z_res
, depth
,
621 stencil_mask
, stencil
);
623 blorp_batch_finish(&blorp_batch
);
624 iris_batch_sync_region_end(batch
);
626 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
627 "cache history: post slow ZS clear");
629 if (clear_depth
&& z_res
) {
630 iris_resource_finish_depth(ice
, z_res
, level
,
631 box
->z
, box
->depth
, true);
635 iris_resource_finish_write(ice
, stencil_res
, level
, box
->z
, box
->depth
,
636 stencil_res
->aux
.usage
);
641 * The pipe->clear() driver hook.
643 * This clears buffers attached to the current draw framebuffer.
646 iris_clear(struct pipe_context
*ctx
,
648 const struct pipe_scissor_state
*scissor_state
,
649 const union pipe_color_union
*p_color
,
653 struct iris_context
*ice
= (void *) ctx
;
654 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
656 assert(buffers
!= 0);
658 struct pipe_box box
= {
659 .width
= cso_fb
->width
,
660 .height
= cso_fb
->height
,
664 box
.x
= scissor_state
->minx
;
665 box
.y
= scissor_state
->miny
;
666 box
.width
= MIN2(box
.width
, scissor_state
->maxx
- scissor_state
->minx
);
667 box
.height
= MIN2(box
.height
, scissor_state
->maxy
- scissor_state
->miny
);
670 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
671 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
673 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1;
674 box
.z
= psurf
->u
.tex
.first_layer
,
675 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
676 buffers
& PIPE_CLEAR_DEPTH
,
677 buffers
& PIPE_CLEAR_STENCIL
,
681 if (buffers
& PIPE_CLEAR_COLOR
) {
682 /* pipe_color_union and isl_color_value are interchangeable */
683 union isl_color_value
*color
= (void *) p_color
;
685 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
686 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
687 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
688 struct iris_surface
*isurf
= (void *) psurf
;
689 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
690 box
.z
= psurf
->u
.tex
.first_layer
,
692 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
693 true, isurf
->view
.format
, isurf
->view
.swizzle
,
701 * The pipe->clear_texture() driver hook.
703 * This clears the given texture resource.
706 iris_clear_texture(struct pipe_context
*ctx
,
707 struct pipe_resource
*p_res
,
709 const struct pipe_box
*box
,
712 struct iris_context
*ice
= (void *) ctx
;
713 struct iris_screen
*screen
= (void *) ctx
->screen
;
714 struct iris_resource
*res
= (void *) p_res
;
715 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
717 if (iris_resource_unfinished_aux_import(res
))
718 iris_resource_finish_aux_import(ctx
->screen
, res
);
720 if (util_format_is_depth_or_stencil(p_res
->format
)) {
721 const struct util_format_unpack_description
*unpack
=
722 util_format_unpack_description(p_res
->format
);
727 if (unpack
->unpack_z_float
)
728 util_format_unpack_z_float(p_res
->format
, &depth
, data
, 1);
730 if (unpack
->unpack_s_8uint
)
731 util_format_unpack_s_8uint(p_res
->format
, &stencil
, data
, 1);
733 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
736 union isl_color_value color
;
737 struct iris_resource
*res
= (void *) p_res
;
738 enum isl_format format
= res
->surf
.format
;
740 if (!isl_format_supports_rendering(devinfo
, format
)) {
741 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
742 // XXX: actually just get_copy_format_for_bpb from BLORP
743 // XXX: don't cut and paste this
745 case 8: format
= ISL_FORMAT_R8_UINT
; break;
746 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
747 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
748 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
749 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
750 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
751 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
752 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
754 unreachable("Unknown format bpb");
757 /* No aux surfaces for non-renderable surfaces */
758 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
761 isl_color_value_unpack(&color
, format
, data
);
763 clear_color(ice
, p_res
, level
, box
, true, format
,
764 ISL_SWIZZLE_IDENTITY
, color
);
769 * The pipe->clear_render_target() driver hook.
771 * This clears the given render target surface.
774 iris_clear_render_target(struct pipe_context
*ctx
,
775 struct pipe_surface
*psurf
,
776 const union pipe_color_union
*p_color
,
777 unsigned dst_x
, unsigned dst_y
,
778 unsigned width
, unsigned height
,
779 bool render_condition_enabled
)
781 struct iris_context
*ice
= (void *) ctx
;
782 struct iris_surface
*isurf
= (void *) psurf
;
783 struct pipe_box box
= {
786 .z
= psurf
->u
.tex
.first_layer
,
789 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
792 /* pipe_color_union and isl_color_value are interchangeable */
793 union isl_color_value
*color
= (void *) p_color
;
795 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
796 render_condition_enabled
,
797 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
801 * The pipe->clear_depth_stencil() driver hook.
803 * This clears the given depth/stencil surface.
806 iris_clear_depth_stencil(struct pipe_context
*ctx
,
807 struct pipe_surface
*psurf
,
811 unsigned dst_x
, unsigned dst_y
,
812 unsigned width
, unsigned height
,
813 bool render_condition_enabled
)
815 struct iris_context
*ice
= (void *) ctx
;
816 struct pipe_box box
= {
819 .z
= psurf
->u
.tex
.first_layer
,
822 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
825 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
827 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
828 render_condition_enabled
,
829 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
834 iris_init_clear_functions(struct pipe_context
*ctx
)
836 ctx
->clear
= iris_clear
;
837 ctx
->clear_texture
= iris_clear_texture
;
838 ctx
->clear_render_target
= iris_clear_render_target
;
839 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;