src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "drm-uapi/i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_defines.h"
  36 #include "common/gen_sample_positions.h"
  37
  38 /**
  39  * For debugging purposes, this returns a time in seconds.
  40  */
  41 double
  42 get_time(void)
  43 {
  44    struct timespec tp;
  45
  46    clock_gettime(CLOCK_MONOTONIC, &tp);
  47
  48    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  49 }
  50
  51 /**
  52  * The pipe->set_debug_callback() driver hook.
  53  */
  54 static void
  55 iris_set_debug_callback(struct pipe_context *ctx,
  56                         const struct pipe_debug_callback *cb)
  57 {
  58    struct iris_context *ice = (struct iris_context *)ctx;
  59
  60    if (cb)
  61       ice->dbg = *cb;
  62    else
  63       memset(&ice->dbg, 0, sizeof(ice->dbg));
  64 }
  65
  66 /**
  67  * Called from the batch module when it detects a GPU hang.
  68  *
  69  * In this case, we've lost our GEM context, and can't rely on any existing
  70  * state on the GPU.  We must mark everything dirty and wipe away any saved
  71  * assumptions about the last known state of the GPU.
  72  */
  73 void
  74 iris_lost_context_state(struct iris_batch *batch)
  75 {
  76    /* The batch module doesn't have an iris_context, because we want to
  77     * avoid introducing lots of layering violations.  Unfortunately, here
  78     * we do need to inform the context of batch catastrophe.  We know the
  79     * batch is one of our context's, so hackily claw our way back.
  80     */
  81    struct iris_context *ice = NULL;
  82
  83    if (batch->name == IRIS_BATCH_RENDER) {
  84       ice = container_of(batch, ice, batches[IRIS_BATCH_RENDER]);
  85       assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
  86
  87       ice->vtbl.init_render_context(batch);
  88    } else if (batch->name == IRIS_BATCH_COMPUTE) {
  89       ice = container_of(batch, ice, batches[IRIS_BATCH_COMPUTE]);
  90       assert(&ice->batches[IRIS_BATCH_COMPUTE] == batch);
  91
  92       ice->vtbl.init_compute_context(batch);
  93    } else {
  94       unreachable("unhandled batch reset");
  95    }
  96
  97    ice->state.dirty = ~0ull;
  98    ice->state.current_hash_scale = 0;
  99    memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
 100    batch->last_surface_base_address = ~0ull;
 101    ice->vtbl.lost_genx_state(ice, batch);
 102 }
 103
 104 static enum pipe_reset_status
 105 iris_get_device_reset_status(struct pipe_context *ctx)
 106 {
 107    struct iris_context *ice = (struct iris_context *)ctx;
 108
 109    enum pipe_reset_status worst_reset = PIPE_NO_RESET;
 110
 111    /* Check the reset status of each batch's hardware context, and take the
 112     * worst status (if one was guilty, proclaim guilt).
 113     */
 114    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 115       /* This will also recreate the hardware contexts as necessary, so any
 116        * future queries will show no resets.  We only want to report once.
 117        */
 118       enum pipe_reset_status batch_reset =
 119          iris_batch_check_for_reset(&ice->batches[i]);
 120
 121       if (batch_reset == PIPE_NO_RESET)
 122          continue;
 123
 124       if (worst_reset == PIPE_NO_RESET) {
 125          worst_reset = batch_reset;
 126       } else {
 127          /* GUILTY < INNOCENT < UNKNOWN */
 128          worst_reset = MIN2(worst_reset, batch_reset);
 129       }
 130    }
 131
 132    if (worst_reset != PIPE_NO_RESET && ice->reset.reset)
 133       ice->reset.reset(ice->reset.data, worst_reset);
 134
 135    return worst_reset;
 136 }
 137
 138 static void
 139 iris_set_device_reset_callback(struct pipe_context *ctx,
 140                                const struct pipe_device_reset_callback *cb)
 141 {
 142    struct iris_context *ice = (struct iris_context *)ctx;
 143
 144    if (cb)
 145       ice->reset = *cb;
 146    else
 147       memset(&ice->reset, 0, sizeof(ice->reset));
 148 }
 149
 150 static void
 151 iris_get_sample_position(struct pipe_context *ctx,
 152                          unsigned sample_count,
 153                          unsigned sample_index,
 154                          float *out_value)
 155 {
 156    union {
 157       struct {
 158          float x[16];
 159          float y[16];
 160       } a;
 161       struct {
 162          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
 163                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
 164                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
 165                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
 166          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
 167                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
 168                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
 169                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
 170       } v;
 171    } u;
 172    switch (sample_count) {
 173    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
 174    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
 175    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
 176    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
 177    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
 178    default: unreachable("invalid sample count");
 179    }
 180
 181    out_value[0] = u.a.x[sample_index];
 182    out_value[1] = u.a.y[sample_index];
 183 }
 184
 185 /**
 186  * Destroy a context, freeing any associated memory.
 187  */
 188 static void
 189 iris_destroy_context(struct pipe_context *ctx)
 190 {
 191    struct iris_context *ice = (struct iris_context *)ctx;
 192
 193    if (ctx->stream_uploader)
 194       u_upload_destroy(ctx->stream_uploader);
 195
 196    ice->vtbl.destroy_state(ice);
 197    iris_destroy_program_cache(ice);
 198    iris_destroy_border_color_pool(ice);
 199    u_upload_destroy(ice->state.surface_uploader);
 200    u_upload_destroy(ice->state.dynamic_uploader);
 201    u_upload_destroy(ice->query_buffer_uploader);
 202
 203    slab_destroy_child(&ice->transfer_pool);
 204
 205    iris_batch_free(&ice->batches[IRIS_BATCH_RENDER]);
 206    iris_batch_free(&ice->batches[IRIS_BATCH_COMPUTE]);
 207    iris_destroy_binder(&ice->state.binder);
 208
 209    ralloc_free(ice);
 210 }
 211
 212 #define genX_call(devinfo, func, ...)             \
 213    switch (devinfo->gen) {                        \
 214    case 12:                                       \
 215       gen12_##func(__VA_ARGS__);                  \
 216       break;                                      \
 217    case 11:                                       \
 218       gen11_##func(__VA_ARGS__);                  \
 219       break;                                      \
 220    case 10:                                       \
 221       gen10_##func(__VA_ARGS__);                  \
 222       break;                                      \
 223    case 9:                                        \
 224       gen9_##func(__VA_ARGS__);                   \
 225       break;                                      \
 226    case 8:                                        \
 227       gen8_##func(__VA_ARGS__);                   \
 228       break;                                      \
 229    default:                                       \
 230       unreachable("Unknown hardware generation"); \
 231    }
 232
 233 /**
 234  * Create a context.
 235  *
 236  * This is where each context begins.
 237  */
 238 struct pipe_context *
 239 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 240 {
 241    struct iris_screen *screen = (struct iris_screen*)pscreen;
 242    const struct gen_device_info *devinfo = &screen->devinfo;
 243    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 244
 245    if (!ice)
 246       return NULL;
 247
 248    struct pipe_context *ctx = &ice->ctx;
 249
 250    ctx->screen = pscreen;
 251    ctx->priv = priv;
 252
 253    ctx->stream_uploader = u_upload_create_default(ctx);
 254    if (!ctx->stream_uploader) {
 255       free(ctx);
 256       return NULL;
 257    }
 258    ctx->const_uploader = ctx->stream_uploader;
 259
 260    ctx->destroy = iris_destroy_context;
 261    ctx->set_debug_callback = iris_set_debug_callback;
 262    ctx->set_device_reset_callback = iris_set_device_reset_callback;
 263    ctx->get_device_reset_status = iris_get_device_reset_status;
 264    ctx->get_sample_position = iris_get_sample_position;
 265
 266    ice->shaders.urb_size = devinfo->urb.size;
 267
 268    iris_init_context_fence_functions(ctx);
 269    iris_init_blit_functions(ctx);
 270    iris_init_clear_functions(ctx);
 271    iris_init_program_functions(ctx);
 272    iris_init_resource_functions(ctx);
 273    iris_init_flush_functions(ctx);
 274
 275    iris_init_program_cache(ice);
 276    iris_init_border_color_pool(ice);
 277    iris_init_binder(ice);
 278
 279    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 280
 281    ice->state.surface_uploader =
 282       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 283                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 284    ice->state.dynamic_uploader =
 285       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 286                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 287
 288    ice->query_buffer_uploader =
 289       u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
 290                       0);
 291
 292    genX_call(devinfo, init_state, ice);
 293    genX_call(devinfo, init_blorp, ice);
 294    genX_call(devinfo, init_query, ice);
 295
 296    int priority = 0;
 297    if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
 298       priority = GEN_CONTEXT_HIGH_PRIORITY;
 299    if (flags & PIPE_CONTEXT_LOW_PRIORITY)
 300       priority = GEN_CONTEXT_LOW_PRIORITY;
 301
 302    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 303       ice->state.sizes = _mesa_hash_table_u64_create(ice);
 304
 305    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 306       iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg,
 307                       &ice->reset, ice->state.sizes,
 308                       ice->batches, (enum iris_batch_name) i,
 309                       I915_EXEC_RENDER, priority);
 310    }
 311
 312    ice->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
 313    ice->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
 314
 315    return ctx;
 316 }