src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "drm-uapi/i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_defines.h"
  36 #include "common/gen_sample_positions.h"
  37
  38 /**
  39  * For debugging purposes, this returns a time in seconds.
  40  */
  41 double
  42 get_time(void)
  43 {
  44    struct timespec tp;
  45
  46    clock_gettime(CLOCK_MONOTONIC, &tp);
  47
  48    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  49 }
  50
  51 /**
  52  * The pipe->set_debug_callback() driver hook.
  53  */
  54 static void
  55 iris_set_debug_callback(struct pipe_context *ctx,
  56                         const struct pipe_debug_callback *cb)
  57 {
  58    struct iris_context *ice = (struct iris_context *)ctx;
  59
  60    if (cb)
  61       ice->dbg = *cb;
  62    else
  63       memset(&ice->dbg, 0, sizeof(ice->dbg));
  64 }
  65
  66 /**
  67  * Called from the batch module when it detects a GPU hang.
  68  *
  69  * In this case, we've lost our GEM context, and can't rely on any existing
  70  * state on the GPU.  We must mark everything dirty and wipe away any saved
  71  * assumptions about the last known state of the GPU.
  72  */
  73 void
  74 iris_lost_context_state(struct iris_batch *batch)
  75 {
  76    /* The batch module doesn't have an iris_context, because we want to
  77     * avoid introducing lots of layering violations.  Unfortunately, here
  78     * we do need to inform the context of batch catastrophe.  We know the
  79     * batch is one of our context's, so hackily claw our way back.
  80     */
  81    struct iris_context *ice = NULL;
  82    struct iris_screen *screen;
  83
  84    if (batch->name == IRIS_BATCH_RENDER) {
  85       ice = container_of(batch, ice, batches[IRIS_BATCH_RENDER]);
  86       assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
  87       screen = (void *) ice->ctx.screen;
  88
  89       ice->vtbl.init_render_context(screen, batch, &ice->vtbl, &ice->dbg);
  90    } else if (batch->name == IRIS_BATCH_COMPUTE) {
  91       ice = container_of(batch, ice, batches[IRIS_BATCH_COMPUTE]);
  92       assert(&ice->batches[IRIS_BATCH_COMPUTE] == batch);
  93       screen = (void *) ice->ctx.screen;
  94
  95       ice->vtbl.init_compute_context(screen, batch, &ice->vtbl, &ice->dbg);
  96    } else {
  97       unreachable("unhandled batch reset");
  98    }
  99
 100    ice->state.dirty = ~0ull;
 101    memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
 102 }
 103
 104 static void
 105 iris_set_device_reset_callback(struct pipe_context *ctx,
 106                                const struct pipe_device_reset_callback *cb)
 107 {
 108    struct iris_context *ice = (struct iris_context *)ctx;
 109
 110    if (cb)
 111       ice->reset = *cb;
 112    else
 113       memset(&ice->reset, 0, sizeof(ice->reset));
 114 }
 115
 116 static void
 117 iris_get_sample_position(struct pipe_context *ctx,
 118                          unsigned sample_count,
 119                          unsigned sample_index,
 120                          float *out_value)
 121 {
 122    union {
 123       struct {
 124          float x[16];
 125          float y[16];
 126       } a;
 127       struct {
 128          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
 129                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
 130                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
 131                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
 132          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
 133                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
 134                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
 135                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
 136       } v;
 137    } u;
 138    switch (sample_count) {
 139    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
 140    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
 141    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
 142    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
 143    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
 144    default: unreachable("invalid sample count");
 145    }
 146
 147    out_value[0] = u.a.x[sample_index];
 148    out_value[1] = u.a.y[sample_index];
 149 }
 150
 151 /**
 152  * Destroy a context, freeing any associated memory.
 153  */
 154 static void
 155 iris_destroy_context(struct pipe_context *ctx)
 156 {
 157    struct iris_context *ice = (struct iris_context *)ctx;
 158
 159    if (ctx->stream_uploader)
 160       u_upload_destroy(ctx->stream_uploader);
 161
 162    ice->vtbl.destroy_state(ice);
 163    iris_destroy_program_cache(ice);
 164    iris_destroy_border_color_pool(ice);
 165    u_upload_destroy(ice->state.surface_uploader);
 166    u_upload_destroy(ice->state.dynamic_uploader);
 167    u_upload_destroy(ice->query_buffer_uploader);
 168
 169    slab_destroy_child(&ice->transfer_pool);
 170
 171    iris_batch_free(&ice->batches[IRIS_BATCH_RENDER]);
 172    iris_batch_free(&ice->batches[IRIS_BATCH_COMPUTE]);
 173    iris_destroy_binder(&ice->state.binder);
 174
 175    ralloc_free(ice);
 176 }
 177
 178 #define genX_call(devinfo, func, ...)             \
 179    switch (devinfo->gen) {                        \
 180    case 11:                                       \
 181       gen11_##func(__VA_ARGS__);                  \
 182       break;                                      \
 183    case 10:                                       \
 184       gen10_##func(__VA_ARGS__);                  \
 185       break;                                      \
 186    case 9:                                        \
 187       gen9_##func(__VA_ARGS__);                   \
 188       break;                                      \
 189    case 8:                                        \
 190       gen8_##func(__VA_ARGS__);                   \
 191       break;                                      \
 192    default:                                       \
 193       unreachable("Unknown hardware generation"); \
 194    }
 195
 196 /**
 197  * Create a context.
 198  *
 199  * This is where each context begins.
 200  */
 201 struct pipe_context *
 202 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 203 {
 204    struct iris_screen *screen = (struct iris_screen*)pscreen;
 205    const struct gen_device_info *devinfo = &screen->devinfo;
 206    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 207
 208    if (!ice)
 209       return NULL;
 210
 211    struct pipe_context *ctx = &ice->ctx;
 212
 213    ctx->screen = pscreen;
 214    ctx->priv = priv;
 215
 216    ctx->stream_uploader = u_upload_create_default(ctx);
 217    if (!ctx->stream_uploader) {
 218       free(ctx);
 219       return NULL;
 220    }
 221    ctx->const_uploader = ctx->stream_uploader;
 222
 223    ctx->destroy = iris_destroy_context;
 224    ctx->set_debug_callback = iris_set_debug_callback;
 225    ctx->set_device_reset_callback = iris_set_device_reset_callback;
 226    ctx->get_sample_position = iris_get_sample_position;
 227
 228    ice->shaders.urb_size = devinfo->urb.size;
 229
 230    iris_init_context_fence_functions(ctx);
 231    iris_init_blit_functions(ctx);
 232    iris_init_clear_functions(ctx);
 233    iris_init_program_functions(ctx);
 234    iris_init_resource_functions(ctx);
 235    iris_init_query_functions(ctx);
 236    iris_init_flush_functions(ctx);
 237
 238    iris_init_program_cache(ice);
 239    iris_init_border_color_pool(ice);
 240    iris_init_binder(ice);
 241
 242    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 243
 244    ice->state.surface_uploader =
 245       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 246                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 247    ice->state.dynamic_uploader =
 248       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 249                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 250
 251    ice->query_buffer_uploader =
 252       u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
 253                       0);
 254
 255    genX_call(devinfo, init_state, ice);
 256    genX_call(devinfo, init_blorp, ice);
 257
 258    int priority = 0;
 259    if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
 260       priority = GEN_CONTEXT_HIGH_PRIORITY;
 261    if (flags & PIPE_CONTEXT_LOW_PRIORITY)
 262       priority = GEN_CONTEXT_LOW_PRIORITY;
 263
 264    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 265       iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg,
 266                       &ice->reset, ice->batches, (enum iris_batch_name) i,
 267                       I915_EXEC_RENDER, priority);
 268    }
 269
 270    ice->vtbl.init_render_context(screen, &ice->batches[IRIS_BATCH_RENDER],
 271                                  &ice->vtbl, &ice->dbg);
 272    ice->vtbl.init_compute_context(screen, &ice->batches[IRIS_BATCH_COMPUTE],
 273                                   &ice->vtbl, &ice->dbg);
 274
 275    return ctx;
 276 }