src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "drm-uapi/i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_defines.h"
  36 #include "common/gen_sample_positions.h"
  37
  38 /**
  39  * For debugging purposes, this returns a time in seconds.
  40  */
  41 double
  42 get_time(void)
  43 {
  44    struct timespec tp;
  45
  46    clock_gettime(CLOCK_MONOTONIC, &tp);
  47
  48    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  49 }
  50
  51 /**
  52  * The pipe->set_debug_callback() driver hook.
  53  */
  54 static void
  55 iris_set_debug_callback(struct pipe_context *ctx,
  56                         const struct pipe_debug_callback *cb)
  57 {
  58    struct iris_context *ice = (struct iris_context *)ctx;
  59
  60    if (cb)
  61       ice->dbg = *cb;
  62    else
  63       memset(&ice->dbg, 0, sizeof(ice->dbg));
  64 }
  65
  66 /**
  67  * Called from the batch module when it detects a GPU hang.
  68  *
  69  * In this case, we've lost our GEM context, and can't rely on any existing
  70  * state on the GPU.  We must mark everything dirty and wipe away any saved
  71  * assumptions about the last known state of the GPU.
  72  */
  73 void
  74 iris_lost_context_state(struct iris_batch *batch)
  75 {
  76    /* The batch module doesn't have an iris_context, because we want to
  77     * avoid introducing lots of layering violations.  Unfortunately, here
  78     * we do need to inform the context of batch catastrophe.  We know the
  79     * batch is one of our context's, so hackily claw our way back.
  80     */
  81    struct iris_context *ice = NULL;
  82    struct iris_screen *screen;
  83
  84    if (batch->name == IRIS_BATCH_RENDER) {
  85       ice = container_of(batch, ice, batches[IRIS_BATCH_RENDER]);
  86       assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
  87       screen = (void *) ice->ctx.screen;
  88
  89       ice->vtbl.init_render_context(screen, batch, &ice->vtbl, &ice->dbg);
  90    } else if (batch->name == IRIS_BATCH_COMPUTE) {
  91       ice = container_of(batch, ice, batches[IRIS_BATCH_COMPUTE]);
  92       assert(&ice->batches[IRIS_BATCH_COMPUTE] == batch);
  93       screen = (void *) ice->ctx.screen;
  94
  95       ice->vtbl.init_compute_context(screen, batch, &ice->vtbl, &ice->dbg);
  96    } else {
  97       unreachable("unhandled batch reset");
  98    }
  99
 100    ice->state.dirty = ~0ull;
 101    memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
 102 }
 103
 104 static void
 105 iris_get_sample_position(struct pipe_context *ctx,
 106                          unsigned sample_count,
 107                          unsigned sample_index,
 108                          float *out_value)
 109 {
 110    union {
 111       struct {
 112          float x[16];
 113          float y[16];
 114       } a;
 115       struct {
 116          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
 117                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
 118                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
 119                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
 120          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
 121                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
 122                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
 123                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
 124       } v;
 125    } u;
 126    switch (sample_count) {
 127    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
 128    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
 129    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
 130    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
 131    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
 132    default: unreachable("invalid sample count");
 133    }
 134
 135    out_value[0] = u.a.x[sample_index];
 136    out_value[1] = u.a.y[sample_index];
 137 }
 138
 139 /**
 140  * Destroy a context, freeing any associated memory.
 141  */
 142 static void
 143 iris_destroy_context(struct pipe_context *ctx)
 144 {
 145    struct iris_context *ice = (struct iris_context *)ctx;
 146
 147    if (ctx->stream_uploader)
 148       u_upload_destroy(ctx->stream_uploader);
 149
 150    ice->vtbl.destroy_state(ice);
 151    iris_destroy_program_cache(ice);
 152    iris_destroy_border_color_pool(ice);
 153    u_upload_destroy(ice->state.surface_uploader);
 154    u_upload_destroy(ice->state.dynamic_uploader);
 155    u_upload_destroy(ice->query_buffer_uploader);
 156
 157    slab_destroy_child(&ice->transfer_pool);
 158
 159    iris_batch_free(&ice->batches[IRIS_BATCH_RENDER]);
 160    iris_batch_free(&ice->batches[IRIS_BATCH_COMPUTE]);
 161    iris_destroy_binder(&ice->state.binder);
 162
 163    ralloc_free(ice);
 164 }
 165
 166 #define genX_call(devinfo, func, ...)             \
 167    switch (devinfo->gen) {                        \
 168    case 11:                                       \
 169       gen11_##func(__VA_ARGS__);                  \
 170       break;                                      \
 171    case 10:                                       \
 172       gen10_##func(__VA_ARGS__);                  \
 173       break;                                      \
 174    case 9:                                        \
 175       gen9_##func(__VA_ARGS__);                   \
 176       break;                                      \
 177    case 8:                                        \
 178       gen8_##func(__VA_ARGS__);                   \
 179       break;                                      \
 180    default:                                       \
 181       unreachable("Unknown hardware generation"); \
 182    }
 183
 184 /**
 185  * Create a context.
 186  *
 187  * This is where each context begins.
 188  */
 189 struct pipe_context *
 190 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 191 {
 192    struct iris_screen *screen = (struct iris_screen*)pscreen;
 193    const struct gen_device_info *devinfo = &screen->devinfo;
 194    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 195
 196    if (!ice)
 197       return NULL;
 198
 199    struct pipe_context *ctx = &ice->ctx;
 200
 201    ctx->screen = pscreen;
 202    ctx->priv = priv;
 203
 204    ctx->stream_uploader = u_upload_create_default(ctx);
 205    if (!ctx->stream_uploader) {
 206       free(ctx);
 207       return NULL;
 208    }
 209    ctx->const_uploader = ctx->stream_uploader;
 210
 211    ctx->destroy = iris_destroy_context;
 212    ctx->set_debug_callback = iris_set_debug_callback;
 213    ctx->get_sample_position = iris_get_sample_position;
 214
 215    ice->shaders.urb_size = devinfo->urb.size;
 216
 217    iris_init_context_fence_functions(ctx);
 218    iris_init_blit_functions(ctx);
 219    iris_init_clear_functions(ctx);
 220    iris_init_program_functions(ctx);
 221    iris_init_resource_functions(ctx);
 222    iris_init_query_functions(ctx);
 223    iris_init_flush_functions(ctx);
 224
 225    iris_init_program_cache(ice);
 226    iris_init_border_color_pool(ice);
 227    iris_init_binder(ice);
 228
 229    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 230
 231    ice->state.surface_uploader =
 232       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 233                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 234    ice->state.dynamic_uploader =
 235       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 236                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 237
 238    ice->query_buffer_uploader =
 239       u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
 240                       0);
 241
 242    genX_call(devinfo, init_state, ice);
 243    genX_call(devinfo, init_blorp, ice);
 244
 245    int priority = 0;
 246    if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
 247       priority = GEN_CONTEXT_HIGH_PRIORITY;
 248    if (flags & PIPE_CONTEXT_LOW_PRIORITY)
 249       priority = GEN_CONTEXT_LOW_PRIORITY;
 250
 251    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 252       iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg,
 253                       ice->batches, (enum iris_batch_name) i,
 254                       I915_EXEC_RENDER, priority);
 255    }
 256
 257    ice->vtbl.init_render_context(screen, &ice->batches[IRIS_BATCH_RENDER],
 258                                  &ice->vtbl, &ice->dbg);
 259    ice->vtbl.init_compute_context(screen, &ice->batches[IRIS_BATCH_COMPUTE],
 260                                   &ice->vtbl, &ice->dbg);
 261
 262    return ctx;
 263 }