2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "util/ralloc.h"
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_upload_mgr.h"
31 #include "drm-uapi/i915_drm.h"
32 #include "iris_context.h"
33 #include "iris_resource.h"
34 #include "iris_screen.h"
35 #include "common/gen_defines.h"
36 #include "common/gen_sample_positions.h"
39 * For debugging purposes, this returns a time in seconds.
46 clock_gettime(CLOCK_MONOTONIC
, &tp
);
48 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
52 * The pipe->set_debug_callback() driver hook.
55 iris_set_debug_callback(struct pipe_context
*ctx
,
56 const struct pipe_debug_callback
*cb
)
58 struct iris_context
*ice
= (struct iris_context
*)ctx
;
63 memset(&ice
->dbg
, 0, sizeof(ice
->dbg
));
67 * Called from the batch module when it detects a GPU hang.
69 * In this case, we've lost our GEM context, and can't rely on any existing
70 * state on the GPU. We must mark everything dirty and wipe away any saved
71 * assumptions about the last known state of the GPU.
74 iris_lost_context_state(struct iris_batch
*batch
)
76 /* The batch module doesn't have an iris_context, because we want to
77 * avoid introducing lots of layering violations. Unfortunately, here
78 * we do need to inform the context of batch catastrophe. We know the
79 * batch is one of our context's, so hackily claw our way back.
81 struct iris_context
*ice
= NULL
;
82 struct iris_screen
*screen
;
84 if (batch
->name
== IRIS_BATCH_RENDER
) {
85 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
86 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
87 screen
= (void *) ice
->ctx
.screen
;
89 ice
->vtbl
.init_render_context(screen
, batch
, &ice
->vtbl
, &ice
->dbg
);
90 } else if (batch
->name
== IRIS_BATCH_COMPUTE
) {
91 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_COMPUTE
]);
92 assert(&ice
->batches
[IRIS_BATCH_COMPUTE
] == batch
);
93 screen
= (void *) ice
->ctx
.screen
;
95 ice
->vtbl
.init_compute_context(screen
, batch
, &ice
->vtbl
, &ice
->dbg
);
97 unreachable("unhandled batch reset");
100 ice
->state
.dirty
= ~0ull;
101 memset(ice
->state
.last_grid
, 0, sizeof(ice
->state
.last_grid
));
104 static enum pipe_reset_status
105 iris_get_device_reset_status(struct pipe_context
*ctx
)
107 struct iris_context
*ice
= (struct iris_context
*)ctx
;
109 enum pipe_reset_status worst_reset
= PIPE_NO_RESET
;
111 /* Check the reset status of each batch's hardware context, and take the
112 * worst status (if one was guilty, proclaim guilt).
114 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
115 /* This will also recreate the hardware contexts as necessary, so any
116 * future queries will show no resets. We only want to report once.
118 enum pipe_reset_status batch_reset
=
119 iris_batch_check_for_reset(&ice
->batches
[i
]);
121 if (batch_reset
== PIPE_NO_RESET
)
124 if (worst_reset
== PIPE_NO_RESET
) {
125 worst_reset
= batch_reset
;
127 /* GUILTY < INNOCENT < UNKNOWN */
128 worst_reset
= MIN2(worst_reset
, batch_reset
);
132 if (worst_reset
!= PIPE_NO_RESET
&& ice
->reset
.reset
)
133 ice
->reset
.reset(ice
->reset
.data
, worst_reset
);
139 iris_set_device_reset_callback(struct pipe_context
*ctx
,
140 const struct pipe_device_reset_callback
*cb
)
142 struct iris_context
*ice
= (struct iris_context
*)ctx
;
147 memset(&ice
->reset
, 0, sizeof(ice
->reset
));
151 iris_get_sample_position(struct pipe_context
*ctx
,
152 unsigned sample_count
,
153 unsigned sample_index
,
162 float _0XOffset
, _1XOffset
, _2XOffset
, _3XOffset
,
163 _4XOffset
, _5XOffset
, _6XOffset
, _7XOffset
,
164 _8XOffset
, _9XOffset
, _10XOffset
, _11XOffset
,
165 _12XOffset
, _13XOffset
, _14XOffset
, _15XOffset
;
166 float _0YOffset
, _1YOffset
, _2YOffset
, _3YOffset
,
167 _4YOffset
, _5YOffset
, _6YOffset
, _7YOffset
,
168 _8YOffset
, _9YOffset
, _10YOffset
, _11YOffset
,
169 _12YOffset
, _13YOffset
, _14YOffset
, _15YOffset
;
172 switch (sample_count
) {
173 case 1: GEN_SAMPLE_POS_1X(u
.v
._
); break;
174 case 2: GEN_SAMPLE_POS_2X(u
.v
._
); break;
175 case 4: GEN_SAMPLE_POS_4X(u
.v
._
); break;
176 case 8: GEN_SAMPLE_POS_8X(u
.v
._
); break;
177 case 16: GEN_SAMPLE_POS_16X(u
.v
._
); break;
178 default: unreachable("invalid sample count");
181 out_value
[0] = u
.a
.x
[sample_index
];
182 out_value
[1] = u
.a
.y
[sample_index
];
186 * Destroy a context, freeing any associated memory.
189 iris_destroy_context(struct pipe_context
*ctx
)
191 struct iris_context
*ice
= (struct iris_context
*)ctx
;
193 if (ctx
->stream_uploader
)
194 u_upload_destroy(ctx
->stream_uploader
);
196 ice
->vtbl
.destroy_state(ice
);
197 iris_destroy_program_cache(ice
);
198 iris_destroy_border_color_pool(ice
);
199 u_upload_destroy(ice
->state
.surface_uploader
);
200 u_upload_destroy(ice
->state
.dynamic_uploader
);
201 u_upload_destroy(ice
->query_buffer_uploader
);
203 slab_destroy_child(&ice
->transfer_pool
);
205 iris_batch_free(&ice
->batches
[IRIS_BATCH_RENDER
]);
206 iris_batch_free(&ice
->batches
[IRIS_BATCH_COMPUTE
]);
207 iris_destroy_binder(&ice
->state
.binder
);
212 #define genX_call(devinfo, func, ...) \
213 switch (devinfo->gen) { \
215 gen11_##func(__VA_ARGS__); \
218 gen10_##func(__VA_ARGS__); \
221 gen9_##func(__VA_ARGS__); \
224 gen8_##func(__VA_ARGS__); \
227 unreachable("Unknown hardware generation"); \
233 * This is where each context begins.
235 struct pipe_context
*
236 iris_create_context(struct pipe_screen
*pscreen
, void *priv
, unsigned flags
)
238 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
239 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
240 struct iris_context
*ice
= rzalloc(NULL
, struct iris_context
);
245 struct pipe_context
*ctx
= &ice
->ctx
;
247 ctx
->screen
= pscreen
;
250 ctx
->stream_uploader
= u_upload_create_default(ctx
);
251 if (!ctx
->stream_uploader
) {
255 ctx
->const_uploader
= ctx
->stream_uploader
;
257 ctx
->destroy
= iris_destroy_context
;
258 ctx
->set_debug_callback
= iris_set_debug_callback
;
259 ctx
->set_device_reset_callback
= iris_set_device_reset_callback
;
260 ctx
->get_device_reset_status
= iris_get_device_reset_status
;
261 ctx
->get_sample_position
= iris_get_sample_position
;
263 ice
->shaders
.urb_size
= devinfo
->urb
.size
;
265 iris_init_context_fence_functions(ctx
);
266 iris_init_blit_functions(ctx
);
267 iris_init_clear_functions(ctx
);
268 iris_init_program_functions(ctx
);
269 iris_init_resource_functions(ctx
);
270 iris_init_query_functions(ctx
);
271 iris_init_flush_functions(ctx
);
273 iris_init_program_cache(ice
);
274 iris_init_border_color_pool(ice
);
275 iris_init_binder(ice
);
277 slab_create_child(&ice
->transfer_pool
, &screen
->transfer_pool
);
279 ice
->state
.surface_uploader
=
280 u_upload_create(ctx
, 16384, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
,
281 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
);
282 ice
->state
.dynamic_uploader
=
283 u_upload_create(ctx
, 16384, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
,
284 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
);
286 ice
->query_buffer_uploader
=
287 u_upload_create(ctx
, 4096, PIPE_BIND_CUSTOM
, PIPE_USAGE_STAGING
,
290 genX_call(devinfo
, init_state
, ice
);
291 genX_call(devinfo
, init_blorp
, ice
);
294 if (flags
& PIPE_CONTEXT_HIGH_PRIORITY
)
295 priority
= GEN_CONTEXT_HIGH_PRIORITY
;
296 if (flags
& PIPE_CONTEXT_LOW_PRIORITY
)
297 priority
= GEN_CONTEXT_LOW_PRIORITY
;
299 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
300 ice
->state
.sizes
= _mesa_hash_table_u64_create(ice
);
302 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
303 iris_init_batch(&ice
->batches
[i
], screen
, &ice
->vtbl
, &ice
->dbg
,
304 &ice
->reset
, ice
->state
.sizes
,
305 ice
->batches
, (enum iris_batch_name
) i
,
306 I915_EXEC_RENDER
, priority
);
309 ice
->vtbl
.init_render_context(screen
, &ice
->batches
[IRIS_BATCH_RENDER
],
310 &ice
->vtbl
, &ice
->dbg
);
311 ice
->vtbl
.init_compute_context(screen
, &ice
->batches
[IRIS_BATCH_COMPUTE
],
312 &ice
->vtbl
, &ice
->dbg
);