src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "drm-uapi/i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_defines.h"
  36 #include "common/gen_sample_positions.h"
  37
  38 /**
  39  * For debugging purposes, this returns a time in seconds.
  40  */
  41 double
  42 get_time(void)
  43 {
  44    struct timespec tp;
  45
  46    clock_gettime(CLOCK_MONOTONIC, &tp);
  47
  48    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  49 }
  50
  51 /**
  52  * The pipe->set_debug_callback() driver hook.
  53  */
  54 static void
  55 iris_set_debug_callback(struct pipe_context *ctx,
  56                         const struct pipe_debug_callback *cb)
  57 {
  58    struct iris_context *ice = (struct iris_context *)ctx;
  59
  60    if (cb)
  61       ice->dbg = *cb;
  62    else
  63       memset(&ice->dbg, 0, sizeof(ice->dbg));
  64 }
  65
  66 static void
  67 iris_get_sample_position(struct pipe_context *ctx,
  68                          unsigned sample_count,
  69                          unsigned sample_index,
  70                          float *out_value)
  71 {
  72    union {
  73       struct {
  74          float x[16];
  75          float y[16];
  76       } a;
  77       struct {
  78          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
  79                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
  80                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
  81                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
  82          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
  83                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
  84                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
  85                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
  86       } v;
  87    } u;
  88    switch (sample_count) {
  89    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
  90    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
  91    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
  92    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
  93    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
  94    default: unreachable("invalid sample count");
  95    }
  96
  97    out_value[0] = u.a.x[sample_index];
  98    out_value[1] = u.a.y[sample_index];
  99 }
 100
 101 /**
 102  * Destroy a context, freeing any associated memory.
 103  */
 104 static void
 105 iris_destroy_context(struct pipe_context *ctx)
 106 {
 107    struct iris_context *ice = (struct iris_context *)ctx;
 108
 109    if (ctx->stream_uploader)
 110       u_upload_destroy(ctx->stream_uploader);
 111
 112    ice->vtbl.destroy_state(ice);
 113    iris_destroy_program_cache(ice);
 114    iris_destroy_border_color_pool(ice);
 115    u_upload_destroy(ice->state.surface_uploader);
 116    u_upload_destroy(ice->state.dynamic_uploader);
 117    u_upload_destroy(ice->query_buffer_uploader);
 118
 119    slab_destroy_child(&ice->transfer_pool);
 120
 121    iris_batch_free(&ice->batches[IRIS_BATCH_RENDER]);
 122    iris_batch_free(&ice->batches[IRIS_BATCH_COMPUTE]);
 123    iris_destroy_binder(&ice->state.binder);
 124
 125    ralloc_free(ice);
 126 }
 127
 128 #define genX_call(devinfo, func, ...)             \
 129    switch (devinfo->gen) {                        \
 130    case 11:                                       \
 131       gen11_##func(__VA_ARGS__);                  \
 132       break;                                      \
 133    case 10:                                       \
 134       gen10_##func(__VA_ARGS__);                  \
 135       break;                                      \
 136    case 9:                                        \
 137       gen9_##func(__VA_ARGS__);                   \
 138       break;                                      \
 139    case 8:                                        \
 140       gen8_##func(__VA_ARGS__);                   \
 141       break;                                      \
 142    default:                                       \
 143       unreachable("Unknown hardware generation"); \
 144    }
 145
 146 /**
 147  * Create a context.
 148  *
 149  * This is where each context begins.
 150  */
 151 struct pipe_context *
 152 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 153 {
 154    struct iris_screen *screen = (struct iris_screen*)pscreen;
 155    const struct gen_device_info *devinfo = &screen->devinfo;
 156    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 157
 158    if (!ice)
 159       return NULL;
 160
 161    struct pipe_context *ctx = &ice->ctx;
 162
 163    ctx->screen = pscreen;
 164    ctx->priv = priv;
 165
 166    ctx->stream_uploader = u_upload_create_default(ctx);
 167    if (!ctx->stream_uploader) {
 168       free(ctx);
 169       return NULL;
 170    }
 171    ctx->const_uploader = ctx->stream_uploader;
 172
 173    ctx->destroy = iris_destroy_context;
 174    ctx->set_debug_callback = iris_set_debug_callback;
 175    ctx->get_sample_position = iris_get_sample_position;
 176
 177    ice->shaders.urb_size = devinfo->urb.size;
 178
 179    iris_init_context_fence_functions(ctx);
 180    iris_init_blit_functions(ctx);
 181    iris_init_clear_functions(ctx);
 182    iris_init_program_functions(ctx);
 183    iris_init_resource_functions(ctx);
 184    iris_init_query_functions(ctx);
 185    iris_init_flush_functions(ctx);
 186
 187    iris_init_program_cache(ice);
 188    iris_init_border_color_pool(ice);
 189    iris_init_binder(ice);
 190
 191    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 192
 193    ice->state.surface_uploader =
 194       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 195                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 196    ice->state.dynamic_uploader =
 197       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 198                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 199
 200    ice->query_buffer_uploader =
 201       u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
 202                       0);
 203
 204    genX_call(devinfo, init_state, ice);
 205    genX_call(devinfo, init_blorp, ice);
 206
 207    int priority = 0;
 208    if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
 209       priority = GEN_CONTEXT_HIGH_PRIORITY;
 210    if (flags & PIPE_CONTEXT_LOW_PRIORITY)
 211       priority = GEN_CONTEXT_LOW_PRIORITY;
 212
 213    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 214       iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg,
 215                       ice->batches, (enum iris_batch_name) i,
 216                       I915_EXEC_RENDER, priority);
 217    }
 218
 219    ice->vtbl.init_render_context(screen, &ice->batches[IRIS_BATCH_RENDER],
 220                                  &ice->vtbl, &ice->dbg);
 221    ice->vtbl.init_compute_context(screen, &ice->batches[IRIS_BATCH_COMPUTE],
 222                                   &ice->vtbl, &ice->dbg);
 223
 224    return ctx;
 225 }