src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/format/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "drm-uapi/i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_defines.h"
  36 #include "common/gen_sample_positions.h"
  37
  38 /**
  39  * For debugging purposes, this returns a time in seconds.
  40  */
  41 double
  42 get_time(void)
  43 {
  44    struct timespec tp;
  45
  46    clock_gettime(CLOCK_MONOTONIC, &tp);
  47
  48    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  49 }
  50
  51 /**
  52  * The pipe->set_debug_callback() driver hook.
  53  */
  54 static void
  55 iris_set_debug_callback(struct pipe_context *ctx,
  56                         const struct pipe_debug_callback *cb)
  57 {
  58    struct iris_context *ice = (struct iris_context *)ctx;
  59
  60    if (cb)
  61       ice->dbg = *cb;
  62    else
  63       memset(&ice->dbg, 0, sizeof(ice->dbg));
  64 }
  65
  66 /**
  67  * Called from the batch module when it detects a GPU hang.
  68  *
  69  * In this case, we've lost our GEM context, and can't rely on any existing
  70  * state on the GPU.  We must mark everything dirty and wipe away any saved
  71  * assumptions about the last known state of the GPU.
  72  */
  73 void
  74 iris_lost_context_state(struct iris_batch *batch)
  75 {
  76    /* The batch module doesn't have an iris_context, because we want to
  77     * avoid introducing lots of layering violations.  Unfortunately, here
  78     * we do need to inform the context of batch catastrophe.  We know the
  79     * batch is one of our context's, so hackily claw our way back.
  80     */
  81    struct iris_context *ice = NULL;
  82
  83    if (batch->name == IRIS_BATCH_RENDER) {
  84       ice = container_of(batch, ice, batches[IRIS_BATCH_RENDER]);
  85       assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
  86
  87       batch->screen->vtbl.init_render_context(batch);
  88    } else if (batch->name == IRIS_BATCH_COMPUTE) {
  89       ice = container_of(batch, ice, batches[IRIS_BATCH_COMPUTE]);
  90       assert(&ice->batches[IRIS_BATCH_COMPUTE] == batch);
  91
  92       batch->screen->vtbl.init_compute_context(batch);
  93    } else {
  94       unreachable("unhandled batch reset");
  95    }
  96
  97    ice->state.dirty = ~0ull;
  98    ice->state.current_hash_scale = 0;
  99    memset(ice->state.last_block, 0, sizeof(ice->state.last_block));
 100    memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
 101    batch->last_surface_base_address = ~0ull;
 102    batch->last_aux_map_state = 0;
 103    batch->screen->vtbl.lost_genx_state(ice, batch);
 104 }
 105
 106 static enum pipe_reset_status
 107 iris_get_device_reset_status(struct pipe_context *ctx)
 108 {
 109    struct iris_context *ice = (struct iris_context *)ctx;
 110
 111    enum pipe_reset_status worst_reset = PIPE_NO_RESET;
 112
 113    /* Check the reset status of each batch's hardware context, and take the
 114     * worst status (if one was guilty, proclaim guilt).
 115     */
 116    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 117       /* This will also recreate the hardware contexts as necessary, so any
 118        * future queries will show no resets.  We only want to report once.
 119        */
 120       enum pipe_reset_status batch_reset =
 121          iris_batch_check_for_reset(&ice->batches[i]);
 122
 123       if (batch_reset == PIPE_NO_RESET)
 124          continue;
 125
 126       if (worst_reset == PIPE_NO_RESET) {
 127          worst_reset = batch_reset;
 128       } else {
 129          /* GUILTY < INNOCENT < UNKNOWN */
 130          worst_reset = MIN2(worst_reset, batch_reset);
 131       }
 132    }
 133
 134    if (worst_reset != PIPE_NO_RESET && ice->reset.reset)
 135       ice->reset.reset(ice->reset.data, worst_reset);
 136
 137    return worst_reset;
 138 }
 139
 140 static void
 141 iris_set_device_reset_callback(struct pipe_context *ctx,
 142                                const struct pipe_device_reset_callback *cb)
 143 {
 144    struct iris_context *ice = (struct iris_context *)ctx;
 145
 146    if (cb)
 147       ice->reset = *cb;
 148    else
 149       memset(&ice->reset, 0, sizeof(ice->reset));
 150 }
 151
 152 static void
 153 iris_get_sample_position(struct pipe_context *ctx,
 154                          unsigned sample_count,
 155                          unsigned sample_index,
 156                          float *out_value)
 157 {
 158    union {
 159       struct {
 160          float x[16];
 161          float y[16];
 162       } a;
 163       struct {
 164          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
 165                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
 166                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
 167                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
 168          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
 169                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
 170                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
 171                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
 172       } v;
 173    } u;
 174    switch (sample_count) {
 175    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
 176    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
 177    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
 178    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
 179    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
 180    default: unreachable("invalid sample count");
 181    }
 182
 183    out_value[0] = u.a.x[sample_index];
 184    out_value[1] = u.a.y[sample_index];
 185 }
 186
 187 /**
 188  * Destroy a context, freeing any associated memory.
 189  */
 190 static void
 191 iris_destroy_context(struct pipe_context *ctx)
 192 {
 193    struct iris_context *ice = (struct iris_context *)ctx;
 194    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
 195
 196    if (ctx->stream_uploader)
 197       u_upload_destroy(ctx->stream_uploader);
 198
 199    screen->vtbl.destroy_state(ice);
 200    iris_destroy_program_cache(ice);
 201    iris_destroy_border_color_pool(ice);
 202    u_upload_destroy(ice->state.surface_uploader);
 203    u_upload_destroy(ice->state.dynamic_uploader);
 204    u_upload_destroy(ice->query_buffer_uploader);
 205
 206    iris_batch_free(&ice->batches[IRIS_BATCH_RENDER]);
 207    iris_batch_free(&ice->batches[IRIS_BATCH_COMPUTE]);
 208    iris_destroy_binder(&ice->state.binder);
 209
 210    slab_destroy_child(&ice->transfer_pool);
 211
 212    ralloc_free(ice);
 213 }
 214
 215 #define genX_call(devinfo, func, ...)             \
 216    switch (devinfo->gen) {                        \
 217    case 12:                                       \
 218       gen12_##func(__VA_ARGS__);                  \
 219       break;                                      \
 220    case 11:                                       \
 221       gen11_##func(__VA_ARGS__);                  \
 222       break;                                      \
 223    case 10:                                       \
 224       gen10_##func(__VA_ARGS__);                  \
 225       break;                                      \
 226    case 9:                                        \
 227       gen9_##func(__VA_ARGS__);                   \
 228       break;                                      \
 229    case 8:                                        \
 230       gen8_##func(__VA_ARGS__);                   \
 231       break;                                      \
 232    default:                                       \
 233       unreachable("Unknown hardware generation"); \
 234    }
 235
 236 /**
 237  * Create a context.
 238  *
 239  * This is where each context begins.
 240  */
 241 struct pipe_context *
 242 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 243 {
 244    struct iris_screen *screen = (struct iris_screen*)pscreen;
 245    const struct gen_device_info *devinfo = &screen->devinfo;
 246    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 247
 248    if (!ice)
 249       return NULL;
 250
 251    struct pipe_context *ctx = &ice->ctx;
 252
 253    ctx->screen = pscreen;
 254    ctx->priv = priv;
 255
 256    ctx->stream_uploader = u_upload_create_default(ctx);
 257    if (!ctx->stream_uploader) {
 258       free(ctx);
 259       return NULL;
 260    }
 261    ctx->const_uploader = ctx->stream_uploader;
 262
 263    ctx->destroy = iris_destroy_context;
 264    ctx->set_debug_callback = iris_set_debug_callback;
 265    ctx->set_device_reset_callback = iris_set_device_reset_callback;
 266    ctx->get_device_reset_status = iris_get_device_reset_status;
 267    ctx->get_sample_position = iris_get_sample_position;
 268
 269    iris_init_context_fence_functions(ctx);
 270    iris_init_blit_functions(ctx);
 271    iris_init_clear_functions(ctx);
 272    iris_init_program_functions(ctx);
 273    iris_init_resource_functions(ctx);
 274    iris_init_flush_functions(ctx);
 275    iris_init_perfquery_functions(ctx);
 276
 277    iris_init_program_cache(ice);
 278    iris_init_border_color_pool(ice);
 279    iris_init_binder(ice);
 280
 281    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 282
 283    ice->state.surface_uploader =
 284       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 285                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 286    ice->state.dynamic_uploader =
 287       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 288                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 289
 290    ice->query_buffer_uploader =
 291       u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
 292                       0);
 293
 294    genX_call(devinfo, init_state, ice);
 295    genX_call(devinfo, init_blorp, ice);
 296    genX_call(devinfo, init_query, ice);
 297
 298    int priority = 0;
 299    if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
 300       priority = GEN_CONTEXT_HIGH_PRIORITY;
 301    if (flags & PIPE_CONTEXT_LOW_PRIORITY)
 302       priority = GEN_CONTEXT_LOW_PRIORITY;
 303
 304    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 305       ice->state.sizes = _mesa_hash_table_u64_create(ice);
 306
 307    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 308       iris_init_batch(ice, (enum iris_batch_name) i, priority);
 309    }
 310
 311    screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
 312    screen->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
 313
 314    return ctx;
 315 }