src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_sample_positions.h"
  36
  37 /**
  38  * For debugging purposes, this returns a time in seconds.
  39  */
  40 double
  41 get_time(void)
  42 {
  43    struct timespec tp;
  44
  45    clock_gettime(CLOCK_MONOTONIC, &tp);
  46
  47    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  48 }
  49
  50 /**
  51  * The pipe->set_debug_callback() driver hook.
  52  */
  53 static void
  54 iris_set_debug_callback(struct pipe_context *ctx,
  55                         const struct pipe_debug_callback *cb)
  56 {
  57    struct iris_context *ice = (struct iris_context *)ctx;
  58
  59    if (cb)
  60       ice->dbg = *cb;
  61    else
  62       memset(&ice->dbg, 0, sizeof(ice->dbg));
  63 }
  64
  65 static void
  66 iris_get_sample_position(struct pipe_context *ctx,
  67                          unsigned sample_count,
  68                          unsigned sample_index,
  69                          float *out_value)
  70 {
  71    union {
  72       struct {
  73          float x[16];
  74          float y[16];
  75       } a;
  76       struct {
  77          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
  78                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
  79                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
  80                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
  81          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
  82                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
  83                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
  84                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
  85       } v;
  86    } u;
  87    switch (sample_count) {
  88    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
  89    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
  90    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
  91    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
  92    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
  93    default: unreachable("invalid sample count");
  94    }
  95
  96    out_value[0] = u.a.x[sample_index];
  97    out_value[1] = u.a.y[sample_index];
  98 }
  99
 100 /**
 101  * Destroy a context, freeing any associated memory.
 102  */
 103 static void
 104 iris_destroy_context(struct pipe_context *ctx)
 105 {
 106    struct iris_context *ice = (struct iris_context *)ctx;
 107
 108    if (ctx->stream_uploader)
 109       u_upload_destroy(ctx->stream_uploader);
 110
 111    ice->vtbl.destroy_state(ice);
 112    iris_destroy_program_cache(ice);
 113    u_upload_destroy(ice->state.surface_uploader);
 114    u_upload_destroy(ice->state.dynamic_uploader);
 115
 116    slab_destroy_child(&ice->transfer_pool);
 117
 118    iris_batch_free(&ice->render_batch);
 119    iris_batch_free(&ice->compute_batch);
 120    iris_destroy_binder(&ice->state.binder);
 121
 122    ralloc_free(ice);
 123 }
 124
 125 #define genX_call(devinfo, func, ...)             \
 126    switch (devinfo->gen) {                        \
 127    case 11:                                       \
 128       gen11_##func(__VA_ARGS__);                  \
 129       break;                                      \
 130    case 10:                                       \
 131       gen10_##func(__VA_ARGS__);                  \
 132       break;                                      \
 133    case 9:                                        \
 134       gen9_##func(__VA_ARGS__);                   \
 135       break;                                      \
 136    default:                                       \
 137       unreachable("Unknown hardware generation"); \
 138    }
 139
 140 /**
 141  * Create a context.
 142  *
 143  * This is where each context begins.
 144  */
 145 struct pipe_context *
 146 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 147 {
 148    struct iris_screen *screen = (struct iris_screen*)pscreen;
 149    const struct gen_device_info *devinfo = &screen->devinfo;
 150    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 151
 152    if (!ice)
 153       return NULL;
 154
 155    struct pipe_context *ctx = &ice->ctx;
 156
 157    ctx->screen = pscreen;
 158    ctx->priv = priv;
 159
 160    ctx->stream_uploader = u_upload_create_default(ctx);
 161    if (!ctx->stream_uploader) {
 162       free(ctx);
 163       return NULL;
 164    }
 165    ctx->const_uploader = ctx->stream_uploader;
 166
 167    ctx->destroy = iris_destroy_context;
 168    ctx->set_debug_callback = iris_set_debug_callback;
 169    ctx->get_sample_position = iris_get_sample_position;
 170
 171    ice->shaders.urb_size = devinfo->urb.size;
 172
 173    iris_init_context_fence_functions(ctx);
 174    iris_init_blit_functions(ctx);
 175    iris_init_clear_functions(ctx);
 176    iris_init_program_functions(ctx);
 177    iris_init_resource_functions(ctx);
 178    iris_init_query_functions(ctx);
 179    iris_init_flush_functions(ctx);
 180
 181    iris_init_program_cache(ice);
 182    iris_init_border_color_pool(ice);
 183    iris_init_binder(ice);
 184
 185    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 186
 187    ice->state.surface_uploader =
 188       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 189                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 190    ice->state.dynamic_uploader =
 191       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 192                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 193
 194    genX_call(devinfo, init_state, ice);
 195    genX_call(devinfo, init_blorp, ice);
 196
 197    struct iris_batch *batches[IRIS_BATCH_COUNT] = {
 198       &ice->render_batch,
 199       &ice->compute_batch,
 200    };
 201    const char *batch_names[IRIS_BATCH_COUNT] = { "render", "compute", };
 202
 203    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
 204       iris_init_batch(batches[i], screen, &ice->vtbl, &ice->dbg,
 205                       batches, batch_names[i], I915_EXEC_RENDER);
 206    }
 207
 208    ice->vtbl.init_render_context(screen, &ice->render_batch, &ice->vtbl,
 209                                  &ice->dbg);
 210    ice->vtbl.init_compute_context(screen, &ice->compute_batch, &ice->vtbl,
 211                                   &ice->dbg);
 212
 213    return ctx;
 214 }