src/gallium/drivers/iris/iris_context.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <time.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/ralloc.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_upload_mgr.h"
  31 #include "i915_drm.h"
  32 #include "iris_context.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35 #include "common/gen_sample_positions.h"
  36
  37 static void
  38 iris_flush(struct pipe_context *ctx,
  39            struct pipe_fence_handle **fence,
  40            unsigned flags)
  41 {
  42    struct iris_context *ice = (struct iris_context *)ctx;
  43
  44    iris_batch_flush(&ice->render_batch);
  45
  46    // XXX: bogus!!!
  47    if (fence)
  48       *fence = NULL;
  49 }
  50
  51 /**
  52  * For debugging purposes, this returns a time in seconds.
  53  */
  54 double
  55 get_time(void)
  56 {
  57    struct timespec tp;
  58
  59    clock_gettime(CLOCK_MONOTONIC, &tp);
  60
  61    return tp.tv_sec + tp.tv_nsec / 1000000000.0;
  62 }
  63
  64 /**
  65  * The pipe->set_debug_callback() driver hook.
  66  */
  67 static void
  68 iris_set_debug_callback(struct pipe_context *ctx,
  69                         const struct pipe_debug_callback *cb)
  70 {
  71    struct iris_context *ice = (struct iris_context *)ctx;
  72
  73    if (cb)
  74       ice->dbg = *cb;
  75    else
  76       memset(&ice->dbg, 0, sizeof(ice->dbg));
  77 }
  78
  79 static void
  80 iris_get_sample_position(struct pipe_context *ctx,
  81                          unsigned sample_count,
  82                          unsigned sample_index,
  83                          float *out_value)
  84 {
  85    union {
  86       struct {
  87          float x[16];
  88          float y[16];
  89       } a;
  90       struct {
  91          float  _0XOffset,  _1XOffset,  _2XOffset,  _3XOffset,
  92                 _4XOffset,  _5XOffset,  _6XOffset,  _7XOffset,
  93                 _8XOffset,  _9XOffset, _10XOffset, _11XOffset,
  94                _12XOffset, _13XOffset, _14XOffset, _15XOffset;
  95          float  _0YOffset,  _1YOffset,  _2YOffset,  _3YOffset,
  96                 _4YOffset,  _5YOffset,  _6YOffset,  _7YOffset,
  97                 _8YOffset,  _9YOffset, _10YOffset, _11YOffset,
  98                _12YOffset, _13YOffset, _14YOffset, _15YOffset;
  99       } v;
 100    } u;
 101    switch (sample_count) {
 102    case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
 103    case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
 104    case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
 105    case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
 106    case 16: GEN_SAMPLE_POS_16X(u.v._); break;
 107    default: unreachable("invalid sample count");
 108    }
 109
 110    out_value[0] = u.a.x[sample_index];
 111    out_value[1] = u.a.y[sample_index];
 112 }
 113
 114 /**
 115  * Destroy a context, freeing any associated memory.
 116  */
 117 static void
 118 iris_destroy_context(struct pipe_context *ctx)
 119 {
 120    struct iris_context *ice = (struct iris_context *)ctx;
 121
 122    if (ctx->stream_uploader)
 123       u_upload_destroy(ctx->stream_uploader);
 124
 125    ice->vtbl.destroy_state(ice);
 126    iris_destroy_program_cache(ice);
 127    u_upload_destroy(ice->state.surface_uploader);
 128    u_upload_destroy(ice->state.dynamic_uploader);
 129
 130    slab_destroy_child(&ice->transfer_pool);
 131
 132    iris_batch_free(&ice->render_batch);
 133    iris_destroy_binder(&ice->state.binder);
 134
 135    ralloc_free(ice);
 136 }
 137
 138 #define genX_call(devinfo, func, ...)             \
 139    switch (devinfo->gen) {                        \
 140    case 11:                                       \
 141       gen11_##func(__VA_ARGS__);                  \
 142       break;                                      \
 143    case 10:                                       \
 144       gen10_##func(__VA_ARGS__);                  \
 145       break;                                      \
 146    case 9:                                        \
 147       gen9_##func(__VA_ARGS__);                   \
 148       break;                                      \
 149    default:                                       \
 150       unreachable("Unknown hardware generation"); \
 151    }
 152
 153 /**
 154  * Create a context.
 155  *
 156  * This is where each context begins.
 157  */
 158 struct pipe_context *
 159 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 160 {
 161    struct iris_screen *screen = (struct iris_screen*)pscreen;
 162    const struct gen_device_info *devinfo = &screen->devinfo;
 163    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 164
 165    if (!ice)
 166       return NULL;
 167
 168    struct pipe_context *ctx = &ice->ctx;
 169
 170    ctx->screen = pscreen;
 171    ctx->priv = priv;
 172
 173    ctx->stream_uploader = u_upload_create_default(ctx);
 174    if (!ctx->stream_uploader) {
 175       free(ctx);
 176       return NULL;
 177    }
 178    ctx->const_uploader = ctx->stream_uploader;
 179
 180    ctx->destroy = iris_destroy_context;
 181    ctx->flush = iris_flush;
 182    ctx->set_debug_callback = iris_set_debug_callback;
 183    ctx->get_sample_position = iris_get_sample_position;
 184
 185    ice->shaders.urb_size = devinfo->urb.size;
 186
 187    iris_init_blit_functions(ctx);
 188    iris_init_clear_functions(ctx);
 189    iris_init_program_functions(ctx);
 190    iris_init_resource_functions(ctx);
 191    iris_init_query_functions(ctx);
 192    iris_init_flush_functions(ctx);
 193
 194    iris_init_program_cache(ice);
 195    iris_init_border_color_pool(ice);
 196    iris_init_binder(ice);
 197
 198    slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
 199
 200    ice->state.surface_uploader =
 201       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 202                       IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
 203    ice->state.dynamic_uploader =
 204       u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
 205                       IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
 206
 207    genX_call(devinfo, init_state, ice);
 208    genX_call(devinfo, init_blorp, ice);
 209    ice->vtbl.init_render_context(screen, &ice->render_batch, &ice->vtbl,
 210                                  &ice->dbg);
 211    ice->vtbl.init_compute_context(screen, &ice->compute_batch, &ice->vtbl,
 212                                   &ice->dbg);
 213
 214    return ctx;
 215 }