2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "util/ralloc.h"
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_upload_mgr.h"
32 #include "iris_context.h"
33 #include "iris_resource.h"
34 #include "iris_screen.h"
35 #include "common/gen_sample_positions.h"
38 iris_flush(struct pipe_context
*ctx
,
39 struct pipe_fence_handle
**fence
,
42 struct iris_context
*ice
= (struct iris_context
*)ctx
;
44 iris_batch_flush(&ice
->render_batch
);
45 iris_batch_flush(&ice
->compute_batch
);
53 * For debugging purposes, this returns a time in seconds.
60 clock_gettime(CLOCK_MONOTONIC
, &tp
);
62 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
66 * The pipe->set_debug_callback() driver hook.
69 iris_set_debug_callback(struct pipe_context
*ctx
,
70 const struct pipe_debug_callback
*cb
)
72 struct iris_context
*ice
= (struct iris_context
*)ctx
;
77 memset(&ice
->dbg
, 0, sizeof(ice
->dbg
));
81 iris_get_sample_position(struct pipe_context
*ctx
,
82 unsigned sample_count
,
83 unsigned sample_index
,
92 float _0XOffset
, _1XOffset
, _2XOffset
, _3XOffset
,
93 _4XOffset
, _5XOffset
, _6XOffset
, _7XOffset
,
94 _8XOffset
, _9XOffset
, _10XOffset
, _11XOffset
,
95 _12XOffset
, _13XOffset
, _14XOffset
, _15XOffset
;
96 float _0YOffset
, _1YOffset
, _2YOffset
, _3YOffset
,
97 _4YOffset
, _5YOffset
, _6YOffset
, _7YOffset
,
98 _8YOffset
, _9YOffset
, _10YOffset
, _11YOffset
,
99 _12YOffset
, _13YOffset
, _14YOffset
, _15YOffset
;
102 switch (sample_count
) {
103 case 1: GEN_SAMPLE_POS_1X(u
.v
._
); break;
104 case 2: GEN_SAMPLE_POS_2X(u
.v
._
); break;
105 case 4: GEN_SAMPLE_POS_4X(u
.v
._
); break;
106 case 8: GEN_SAMPLE_POS_8X(u
.v
._
); break;
107 case 16: GEN_SAMPLE_POS_16X(u
.v
._
); break;
108 default: unreachable("invalid sample count");
111 out_value
[0] = u
.a
.x
[sample_index
];
112 out_value
[1] = u
.a
.y
[sample_index
];
116 * Destroy a context, freeing any associated memory.
119 iris_destroy_context(struct pipe_context
*ctx
)
121 struct iris_context
*ice
= (struct iris_context
*)ctx
;
123 if (ctx
->stream_uploader
)
124 u_upload_destroy(ctx
->stream_uploader
);
126 ice
->vtbl
.destroy_state(ice
);
127 iris_destroy_program_cache(ice
);
128 u_upload_destroy(ice
->state
.surface_uploader
);
129 u_upload_destroy(ice
->state
.dynamic_uploader
);
131 slab_destroy_child(&ice
->transfer_pool
);
133 iris_batch_free(&ice
->render_batch
);
134 iris_destroy_binder(&ice
->state
.binder
);
139 #define genX_call(devinfo, func, ...) \
140 switch (devinfo->gen) { \
142 gen11_##func(__VA_ARGS__); \
145 gen10_##func(__VA_ARGS__); \
148 gen9_##func(__VA_ARGS__); \
151 unreachable("Unknown hardware generation"); \
157 * This is where each context begins.
159 struct pipe_context
*
160 iris_create_context(struct pipe_screen
*pscreen
, void *priv
, unsigned flags
)
162 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
163 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
164 struct iris_context
*ice
= rzalloc(NULL
, struct iris_context
);
169 struct pipe_context
*ctx
= &ice
->ctx
;
171 ctx
->screen
= pscreen
;
174 ctx
->stream_uploader
= u_upload_create_default(ctx
);
175 if (!ctx
->stream_uploader
) {
179 ctx
->const_uploader
= ctx
->stream_uploader
;
181 ctx
->destroy
= iris_destroy_context
;
182 ctx
->flush
= iris_flush
;
183 ctx
->set_debug_callback
= iris_set_debug_callback
;
184 ctx
->get_sample_position
= iris_get_sample_position
;
186 ice
->shaders
.urb_size
= devinfo
->urb
.size
;
188 iris_init_blit_functions(ctx
);
189 iris_init_clear_functions(ctx
);
190 iris_init_program_functions(ctx
);
191 iris_init_resource_functions(ctx
);
192 iris_init_query_functions(ctx
);
193 iris_init_flush_functions(ctx
);
195 iris_init_program_cache(ice
);
196 iris_init_border_color_pool(ice
);
197 iris_init_binder(ice
);
199 slab_create_child(&ice
->transfer_pool
, &screen
->transfer_pool
);
201 ice
->state
.surface_uploader
=
202 u_upload_create(ctx
, 16384, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
,
203 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
);
204 ice
->state
.dynamic_uploader
=
205 u_upload_create(ctx
, 16384, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
,
206 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
);
208 genX_call(devinfo
, init_state
, ice
);
209 genX_call(devinfo
, init_blorp
, ice
);
210 ice
->vtbl
.init_render_context(screen
, &ice
->render_batch
, &ice
->vtbl
,
212 ice
->vtbl
.init_compute_context(screen
, &ice
->compute_batch
, &ice
->vtbl
,