src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  57 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  58 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  59 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  60 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  61 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  62
  63 /**
  64  * Dirty flags.  When state changes, we flag some combination of these
  65  * to indicate that particular GPU commands need to be re-emitted.
  66  *
  67  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  68  * in rare cases they map to a group of related packets that need to be
  69  * emitted together.
  70  *
  71  * See iris_upload_render_state().
  72  */
  73 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  74 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  75 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  76 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  77 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  78 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  79 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  80 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  81 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  82 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  83 #define IRIS_DIRTY_SBE                      (1ull << 10)
  84 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  85 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  86 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  87 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  88 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  89 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  90 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  91 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  92 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  93 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  94 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  95 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  96 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  97 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  98 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  99 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 100 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 101 #define IRIS_DIRTY_VS                       (1ull << 28)
 102 #define IRIS_DIRTY_TCS                      (1ull << 29)
 103 #define IRIS_DIRTY_TES                      (1ull << 30)
 104 #define IRIS_DIRTY_GS                       (1ull << 31)
 105 #define IRIS_DIRTY_FS                       (1ull << 32)
 106 #define IRIS_DIRTY_CS                       (1ull << 33)
 107 #define IRIS_DIRTY_URB                      (1ull << 34)
 108 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 109 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 110 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 111 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 112 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 113 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 114 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 115 #define IRIS_DIRTY_WM                       (1ull << 42)
 116 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 117 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 118 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 119 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 120 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 121 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 122 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 123 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 124 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 125 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 126 #define IRIS_DIRTY_VF                       (1ull << 53)
 127 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 128
 129 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 130                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 131                                     IRIS_DIRTY_UNCOMPILED_CS | \
 132                                     IRIS_DIRTY_CONSTANTS_CS | \
 133                                     IRIS_DIRTY_BINDINGS_CS)
 134
 135 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 136
 137 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 138                                  IRIS_DIRTY_BINDINGS_TCS | \
 139                                  IRIS_DIRTY_BINDINGS_TES | \
 140                                  IRIS_DIRTY_BINDINGS_GS  | \
 141                                  IRIS_DIRTY_BINDINGS_FS  | \
 142                                  IRIS_DIRTY_BINDINGS_CS)
 143
 144 /**
 145  * Non-orthogonal state (NOS) dependency flags.
 146  *
 147  * Shader programs may depend on non-orthogonal state.  These flags are
 148  * used to indicate that a shader's key depends on the state provided by
 149  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 150  * cause the driver to re-compute the shader key, possibly triggering a
 151  * shader recompile.
 152  */
 153 enum iris_nos_dep {
 154    IRIS_NOS_FRAMEBUFFER,
 155    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 156    IRIS_NOS_RASTERIZER,
 157    IRIS_NOS_BLEND,
 158    IRIS_NOS_LAST_VUE_MAP,
 159
 160    IRIS_NOS_COUNT,
 161 };
 162
 163 struct iris_depth_stencil_alpha_state;
 164
 165 /**
 166  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 167  */
 168 enum iris_program_cache_id {
 169    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 170    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 171    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 172    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 173    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 174    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 175    IRIS_CACHE_BLORP,
 176 };
 177
 178 /** @{
 179  *
 180  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 181  * synchronization, pipelined memory writes, and so on.
 182  *
 183  * The bits here are not the actual hardware values.  The actual fields
 184  * move between various generations, so we just have flags for each
 185  * potential operation, and use genxml to encode the actual packet.
 186  */
 187 enum pipe_control_flags
 188 {
 189    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 190    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 191    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 192    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 193    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 194    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 195    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 196    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 197    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 198    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 199    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 200    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 201    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 202    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 203    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 204    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 205    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 206    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 207    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 208    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 209    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 210    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 211    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 212    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 213 };
 214
 215 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 216    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 217     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 218     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 219
 220 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 221    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 222     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 223     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 224     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 225     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 226
 227 enum iris_predicate_state {
 228    /* The first two states are used if we can determine whether to draw
 229     * without having to look at the values in the query object buffer. This
 230     * will happen if there is no conditional render in progress, if the query
 231     * object is already completed or if something else has already added
 232     * samples to the preliminary result.
 233     */
 234    IRIS_PREDICATE_STATE_RENDER,
 235    IRIS_PREDICATE_STATE_DONT_RENDER,
 236
 237    /* In this case whether to draw or not depends on the result of an
 238     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 239     */
 240    IRIS_PREDICATE_STATE_USE_BIT,
 241 };
 242
 243 /** @} */
 244
 245 /**
 246  * A compiled shader variant, containing a pointer to the GPU assembly,
 247  * as well as program data and other packets needed by state upload.
 248  *
 249  * There can be several iris_compiled_shader variants per API-level shader
 250  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 251  */
 252 struct iris_compiled_shader {
 253    /** Reference to the uploaded assembly. */
 254    struct iris_state_ref assembly;
 255
 256    /** Pointer to the assembly in the BO's map. */
 257    void *map;
 258
 259    /** The program data (owned by the program cache hash table) */
 260    struct brw_stage_prog_data *prog_data;
 261
 262    /** A list of system values to be uploaded as uniforms. */
 263    enum brw_param_builtin *system_values;
 264    unsigned num_system_values;
 265
 266    /** Number of constbufs expected by the shader. */
 267    unsigned num_cbufs;
 268
 269    /**
 270     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 271     * (the VUE-based information for transform feedback outputs).
 272     */
 273    uint32_t *streamout;
 274
 275    /**
 276     * Shader packets and other data derived from prog_data.  These must be
 277     * completely determined from prog_data.
 278     */
 279    uint8_t derived_data[0];
 280 };
 281
 282 /**
 283  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 284  */
 285 struct iris_const_buffer {
 286    /** The resource and offset for the actual constant data */
 287    struct iris_state_ref data;
 288
 289    /** The resource and offset for the SURFACE_STATE for pull access. */
 290    struct iris_state_ref surface_state;
 291 };
 292
 293 /**
 294  * API context state that is replicated per shader stage.
 295  */
 296 struct iris_shader_state {
 297    /** Uniform Buffers */
 298    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 299
 300    struct pipe_constant_buffer cbuf0;
 301    bool cbuf0_needs_upload;
 302
 303    /** Shader Storage Buffers */
 304    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 305    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 306
 307    /** Shader Storage Images (image load store) */
 308    struct {
 309       struct pipe_resource *res;
 310       struct iris_state_ref surface_state;
 311       unsigned access;
 312
 313       /** Gen8-only uniform data for image lowering */
 314       struct brw_image_param param;
 315    } image[PIPE_MAX_SHADER_IMAGES];
 316
 317    struct iris_state_ref sampler_table;
 318    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 319    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 320
 321    /** Bitfield of which image views are bound (non-null). */
 322    uint32_t bound_image_views;
 323
 324    /** Bitfield of which sampler views are bound (non-null). */
 325    uint32_t bound_sampler_views;
 326 };
 327
 328 /**
 329  * Gallium CSO for stream output (transform feedback) targets.
 330  */
 331 struct iris_stream_output_target {
 332    struct pipe_stream_output_target base;
 333
 334    /** Storage holding the offset where we're writing in the buffer */
 335    struct iris_state_ref offset;
 336
 337    /** Stride (dwords-per-vertex) during this transform feedback operation */
 338    uint16_t stride;
 339 };
 340
 341 /**
 342  * Virtual table for generation-specific (genxml) function calls.
 343  */
 344 struct iris_vtable {
 345    void (*destroy_state)(struct iris_context *ice);
 346    void (*init_render_context)(struct iris_screen *screen,
 347                                struct iris_batch *batch,
 348                                struct iris_vtable *vtbl,
 349                                struct pipe_debug_callback *dbg);
 350    void (*init_compute_context)(struct iris_screen *screen,
 351                                 struct iris_batch *batch,
 352                                 struct iris_vtable *vtbl,
 353                                 struct pipe_debug_callback *dbg);
 354    void (*upload_render_state)(struct iris_context *ice,
 355                                struct iris_batch *batch,
 356                                const struct pipe_draw_info *draw);
 357    void (*update_surface_base_address)(struct iris_batch *batch,
 358                                        struct iris_binder *binder);
 359    void (*upload_compute_state)(struct iris_context *ice,
 360                                 struct iris_batch *batch,
 361                                 const struct pipe_grid_info *grid);
 362    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 363                                uint32_t src);
 364    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 365                                uint32_t src);
 366    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 367                                uint32_t val);
 368    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 369                                uint64_t val);
 370    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 371                                struct iris_bo *bo, uint32_t offset);
 372    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 373                                struct iris_bo *bo, uint32_t offset);
 374    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 375                                 struct iris_bo *bo, uint32_t offset,
 376                                 bool predicated);
 377    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 378                                 struct iris_bo *bo, uint32_t offset,
 379                                 bool predicated);
 380    void (*store_data_imm32)(struct iris_batch *batch,
 381                             struct iris_bo *bo, uint32_t offset,
 382                             uint32_t value);
 383    void (*store_data_imm64)(struct iris_batch *batch,
 384                             struct iris_bo *bo, uint32_t offset,
 385                             uint64_t value);
 386    void (*copy_mem_mem)(struct iris_batch *batch,
 387                         struct iris_bo *dst_bo, uint32_t dst_offset,
 388                         struct iris_bo *src_bo, uint32_t src_offset,
 389                         unsigned bytes);
 390    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 391                                  struct iris_bo *bo, uint32_t offset,
 392                                  uint64_t imm);
 393
 394    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 395    void (*store_derived_program_state)(struct iris_context *ice,
 396                                        enum iris_program_cache_id cache_id,
 397                                        struct iris_compiled_shader *shader);
 398    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 399                                     const struct brw_vue_map *vue_map);
 400    void (*populate_vs_key)(const struct iris_context *ice,
 401                            const struct shader_info *info,
 402                            struct brw_vs_prog_key *key);
 403    void (*populate_tcs_key)(const struct iris_context *ice,
 404                             struct brw_tcs_prog_key *key);
 405    void (*populate_tes_key)(const struct iris_context *ice,
 406                             struct brw_tes_prog_key *key);
 407    void (*populate_gs_key)(const struct iris_context *ice,
 408                            struct brw_gs_prog_key *key);
 409    void (*populate_fs_key)(const struct iris_context *ice,
 410                            struct brw_wm_prog_key *key);
 411    void (*populate_cs_key)(const struct iris_context *ice,
 412                            struct brw_cs_prog_key *key);
 413 };
 414
 415 /**
 416  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 417  *
 418  * See iris_border_color.c for more information.
 419  */
 420 struct iris_border_color_pool {
 421    struct iris_bo *bo;
 422    void *map;
 423    unsigned insert_point;
 424
 425    /** Map from border colors to offsets in the buffer. */
 426    struct hash_table *ht;
 427 };
 428
 429 /**
 430  * The API context (derived from pipe_context).
 431  *
 432  * Most driver state is tracked here.
 433  */
 434 struct iris_context {
 435    struct pipe_context ctx;
 436
 437    /** A debug callback for KHR_debug output. */
 438    struct pipe_debug_callback dbg;
 439
 440    /** Slab allocator for iris_transfer_map objects. */
 441    struct slab_child_pool transfer_pool;
 442
 443    struct iris_vtable vtbl;
 444
 445    struct blorp_context blorp;
 446
 447    struct iris_batch batches[IRIS_BATCH_COUNT];
 448
 449    struct {
 450       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 451       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 452       struct brw_vue_map *last_vue_map;
 453
 454       struct u_upload_mgr *uploader;
 455       struct hash_table *cache;
 456
 457       unsigned urb_size;
 458
 459       /**
 460        * Scratch buffers for various sizes and stages.
 461        *
 462        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 463        * and shader stage.
 464        */
 465       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 466    } shaders;
 467
 468    struct {
 469       uint64_t dirty;
 470       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 471
 472       unsigned num_viewports;
 473       unsigned sample_mask;
 474       struct iris_blend_state *cso_blend;
 475       struct iris_rasterizer_state *cso_rast;
 476       struct iris_depth_stencil_alpha_state *cso_zsa;
 477       struct iris_vertex_element_state *cso_vertex_elements;
 478       struct pipe_blend_color blend_color;
 479       struct pipe_poly_stipple poly_stipple;
 480       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 481       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 482       struct pipe_stencil_ref stencil_ref;
 483       struct pipe_framebuffer_state framebuffer;
 484       struct pipe_clip_state clip_planes;
 485
 486       float default_outer_level[4];
 487       float default_inner_level[2];
 488
 489       /** Bitfield of which vertex buffers are bound (non-null). */
 490       uint64_t bound_vertex_buffers;
 491
 492       bool primitive_restart;
 493       unsigned cut_index;
 494       enum pipe_prim_type prim_mode:8;
 495       uint8_t vertices_per_patch;
 496
 497       /** The last compute grid size */
 498       uint32_t last_grid[3];
 499       /** Reference to the BO containing the compute grid size */
 500       struct iris_state_ref grid_size;
 501       /** Reference to the SURFACE_STATE for the compute grid resource */
 502       struct iris_state_ref grid_surf_state;
 503
 504       /** Bitfield of whether color blending is enabled for RT[i] */
 505       uint8_t blend_enables;
 506
 507       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 508       bool depth_writes_enabled;
 509
 510       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 511       bool stencil_writes_enabled;
 512
 513       /** GenX-specific current state */
 514       struct iris_genx_state *genx;
 515
 516       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 517
 518       /** Do any samplers (for any stage) need border color? */
 519       bool need_border_colors;
 520
 521       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 522       bool streamout_active;
 523
 524       bool statistics_counters_enabled;
 525
 526       /** Current conditional rendering mode */
 527       enum iris_predicate_state predicate;
 528
 529       /**
 530        * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
 531        * render context that needs to be uploaded to the compute context.
 532        */
 533       struct iris_bo *compute_predicate;
 534
 535       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 536       bool prims_generated_query_active;
 537
 538       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 539       uint32_t *streamout;
 540
 541       /** Current strides for each streamout buffer */
 542       uint16_t *streamout_strides;
 543
 544       /** The SURFACE_STATE for a 1x1x1 null surface. */
 545       struct iris_state_ref unbound_tex;
 546
 547       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 548       struct iris_state_ref null_fb;
 549
 550       struct u_upload_mgr *surface_uploader;
 551       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 552       // "I'm streaming this out at draw time and never want it again!"
 553       struct u_upload_mgr *dynamic_uploader;
 554
 555       struct iris_binder binder;
 556
 557       struct iris_border_color_pool border_color_pool;
 558
 559       /** The high 16-bits of the last VBO/index buffer addresses */
 560       uint16_t last_vbo_high_bits[33];
 561       uint16_t last_index_bo_high_bits;
 562
 563       /**
 564        * Resources containing streamed state which our render context
 565        * currently points to.  Used to re-add these to the validation
 566        * list when we start a new batch and haven't resubmitted commands.
 567        */
 568       struct {
 569          struct pipe_resource *cc_vp;
 570          struct pipe_resource *sf_cl_vp;
 571          struct pipe_resource *color_calc;
 572          struct pipe_resource *scissor;
 573          struct pipe_resource *blend;
 574          struct pipe_resource *index_buffer;
 575       } last_res;
 576    } state;
 577 };
 578
 579 #define perf_debug(dbg, ...) do {                      \
 580    if (INTEL_DEBUG & DEBUG_PERF)                       \
 581       dbg_printf(__VA_ARGS__);                         \
 582    if (unlikely(dbg))                                  \
 583       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 584 } while(0)
 585
 586 double get_time(void);
 587
 588 struct pipe_context *
 589 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 590
 591 void iris_init_blit_functions(struct pipe_context *ctx);
 592 void iris_init_clear_functions(struct pipe_context *ctx);
 593 void iris_init_program_functions(struct pipe_context *ctx);
 594 void iris_init_resource_functions(struct pipe_context *ctx);
 595 void iris_init_query_functions(struct pipe_context *ctx);
 596 void iris_update_compiled_shaders(struct iris_context *ice);
 597 void iris_update_compiled_compute_shader(struct iris_context *ice);
 598 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 599                                     uint32_t *dst);
 600
 601
 602 /* iris_blit.c */
 603 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 604                                   struct pipe_resource *p_res,
 605                                   enum isl_aux_usage aux_usage,
 606                                   bool is_render_target);
 607
 608 /* iris_draw.c */
 609
 610 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 611 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 612
 613 /* iris_pipe_control.c */
 614
 615 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 616                                   uint32_t flags);
 617 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 618                                   struct iris_bo *bo, uint32_t offset,
 619                                   uint64_t imm);
 620 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 621                                 uint32_t flags);
 622
 623 void iris_init_flush_functions(struct pipe_context *ctx);
 624
 625 /* iris_blorp.c */
 626 void gen8_init_blorp(struct iris_context *ice);
 627 void gen9_init_blorp(struct iris_context *ice);
 628 void gen10_init_blorp(struct iris_context *ice);
 629 void gen11_init_blorp(struct iris_context *ice);
 630
 631 /* iris_border_color.c */
 632
 633 void iris_init_border_color_pool(struct iris_context *ice);
 634 void iris_destroy_border_color_pool(struct iris_context *ice);
 635 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 636 uint32_t iris_upload_border_color(struct iris_context *ice,
 637                                   union pipe_color_union *color);
 638
 639 /* iris_state.c */
 640 void gen8_init_state(struct iris_context *ice);
 641 void gen9_init_state(struct iris_context *ice);
 642 void gen10_init_state(struct iris_context *ice);
 643 void gen11_init_state(struct iris_context *ice);
 644
 645 /* iris_program.c */
 646 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 647                                                gl_shader_stage stage);
 648 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 649                                        unsigned per_thread_scratch,
 650                                        gl_shader_stage stage);
 651
 652 /* iris_program_cache.c */
 653
 654 void iris_init_program_cache(struct iris_context *ice);
 655 void iris_destroy_program_cache(struct iris_context *ice);
 656 void iris_print_program_cache(struct iris_context *ice);
 657 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 658                                                      enum iris_program_cache_id,
 659                                                      uint32_t key_size,
 660                                                      const void *key);
 661 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 662                                                 enum iris_program_cache_id,
 663                                                 uint32_t key_size,
 664                                                 const void *key,
 665                                                 const void *assembly,
 666                                                 struct brw_stage_prog_data *,
 667                                                 uint32_t *streamout,
 668                                                 enum brw_param_builtin *sysv,
 669                                                 unsigned num_system_values,
 670                                                 unsigned num_cbufs);
 671 const void *iris_find_previous_compile(const struct iris_context *ice,
 672                                        enum iris_program_cache_id cache_id,
 673                                        unsigned program_string_id);
 674 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 675                               const void *key,
 676                               uint32_t key_size,
 677                               uint32_t *kernel_out,
 678                               void *prog_data_out);
 679 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 680                               const void *key, uint32_t key_size,
 681                               const void *kernel, uint32_t kernel_size,
 682                               const struct brw_stage_prog_data *prog_data,
 683                               uint32_t prog_data_size,
 684                               uint32_t *kernel_out,
 685                               void *prog_data_out);
 686
 687 /* iris_query.c */
 688
 689 void iris_math_div32_gpr0(struct iris_context *ice,
 690                           struct iris_batch *batch,
 691                           uint32_t D);
 692
 693 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 694                              uint64_t gpu_timestamp);
 695
 696 /* iris_resolve.c */
 697
 698 void iris_predraw_resolve_inputs(struct iris_batch *batch,
 699                                  struct iris_shader_state *shs);
 700 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 701                                       struct iris_batch *batch);
 702 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 703                                            struct iris_batch *batch);
 704 void iris_cache_sets_clear(struct iris_batch *batch);
 705 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 706 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 707 void iris_cache_flush_for_render(struct iris_batch *batch,
 708                                  struct iris_bo *bo,
 709                                  enum isl_format format,
 710                                  enum isl_aux_usage aux_usage);
 711 void iris_render_cache_add_bo(struct iris_batch *batch,
 712                               struct iris_bo *bo,
 713                               enum isl_format format,
 714                               enum isl_aux_usage aux_usage);
 715 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 716 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 717
 718 #endif