2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_CONTEXT_H
24 #define IRIS_CONTEXT_H
26 #include "pipe/p_context.h"
27 #include "pipe/p_state.h"
28 #include "util/u_debug.h"
29 #include "intel/blorp/blorp.h"
30 #include "intel/dev/gen_debug.h"
31 #include "intel/compiler/brw_compiler.h"
32 #include "iris_batch.h"
33 #include "iris_binder.h"
34 #include "iris_fence.h"
35 #include "iris_resource.h"
36 #include "iris_screen.h"
43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
46 #define IRIS_MAX_ABOS 16
47 #define IRIS_MAX_SSBOS 16
48 #define IRIS_MAX_VIEWPORTS 16
49 #define IRIS_MAX_CLIP_PLANES 8
51 enum iris_param_domain
{
52 BRW_PARAM_DOMAIN_BUILTIN
= 0,
53 BRW_PARAM_DOMAIN_IMAGE
,
56 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
57 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
58 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
59 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
60 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
61 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
64 * Dirty flags. When state changes, we flag some combination of these
65 * to indicate that particular GPU commands need to be re-emitted.
67 * Each bit typically corresponds to a single 3DSTATE_* command packet, but
68 * in rare cases they map to a group of related packets that need to be
71 * See iris_upload_render_state().
73 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
74 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
75 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
76 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
77 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
78 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
79 #define IRIS_DIRTY_PS_BLEND (1ull << 6)
80 #define IRIS_DIRTY_BLEND_STATE (1ull << 7)
81 #define IRIS_DIRTY_RASTER (1ull << 8)
82 #define IRIS_DIRTY_CLIP (1ull << 9)
83 #define IRIS_DIRTY_SBE (1ull << 10)
84 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
85 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
86 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
87 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
88 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
89 #define IRIS_DIRTY_SAMPLER_STATES_VS (1ull << 16)
90 #define IRIS_DIRTY_SAMPLER_STATES_TCS (1ull << 17)
91 #define IRIS_DIRTY_SAMPLER_STATES_TES (1ull << 18)
92 #define IRIS_DIRTY_SAMPLER_STATES_GS (1ull << 19)
93 #define IRIS_DIRTY_SAMPLER_STATES_PS (1ull << 20)
94 #define IRIS_DIRTY_SAMPLER_STATES_CS (1ull << 21)
95 #define IRIS_DIRTY_UNCOMPILED_VS (1ull << 22)
96 #define IRIS_DIRTY_UNCOMPILED_TCS (1ull << 23)
97 #define IRIS_DIRTY_UNCOMPILED_TES (1ull << 24)
98 #define IRIS_DIRTY_UNCOMPILED_GS (1ull << 25)
99 #define IRIS_DIRTY_UNCOMPILED_FS (1ull << 26)
100 #define IRIS_DIRTY_UNCOMPILED_CS (1ull << 27)
101 #define IRIS_DIRTY_VS (1ull << 28)
102 #define IRIS_DIRTY_TCS (1ull << 29)
103 #define IRIS_DIRTY_TES (1ull << 30)
104 #define IRIS_DIRTY_GS (1ull << 31)
105 #define IRIS_DIRTY_FS (1ull << 32)
106 #define IRIS_DIRTY_CS (1ull << 33)
107 #define IRIS_DIRTY_URB (1ull << 34)
108 #define IRIS_DIRTY_CONSTANTS_VS (1ull << 35)
109 #define IRIS_DIRTY_CONSTANTS_TCS (1ull << 36)
110 #define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
111 #define IRIS_DIRTY_CONSTANTS_GS (1ull << 38)
112 #define IRIS_DIRTY_CONSTANTS_FS (1ull << 39)
113 #define IRIS_DIRTY_CONSTANTS_CS (1ull << 40)
114 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 41)
115 #define IRIS_DIRTY_WM (1ull << 42)
116 #define IRIS_DIRTY_BINDINGS_VS (1ull << 43)
117 #define IRIS_DIRTY_BINDINGS_TCS (1ull << 44)
118 #define IRIS_DIRTY_BINDINGS_TES (1ull << 45)
119 #define IRIS_DIRTY_BINDINGS_GS (1ull << 46)
120 #define IRIS_DIRTY_BINDINGS_FS (1ull << 47)
121 #define IRIS_DIRTY_BINDINGS_CS (1ull << 48)
122 #define IRIS_DIRTY_SO_BUFFERS (1ull << 49)
123 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 50)
124 #define IRIS_DIRTY_STREAMOUT (1ull << 51)
125 #define IRIS_DIRTY_VF_SGVS (1ull << 52)
126 #define IRIS_DIRTY_VF (1ull << 53)
127 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
128 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 55)
129 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
130 #define IRIS_DIRTY_VF_STATISTICS (1ull << 57)
132 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
133 IRIS_DIRTY_SAMPLER_STATES_CS | \
134 IRIS_DIRTY_UNCOMPILED_CS | \
135 IRIS_DIRTY_CONSTANTS_CS | \
136 IRIS_DIRTY_BINDINGS_CS | \
137 IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
139 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
141 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS | \
142 IRIS_DIRTY_BINDINGS_TCS | \
143 IRIS_DIRTY_BINDINGS_TES | \
144 IRIS_DIRTY_BINDINGS_GS | \
145 IRIS_DIRTY_BINDINGS_FS | \
146 IRIS_DIRTY_BINDINGS_CS)
149 * Non-orthogonal state (NOS) dependency flags.
151 * Shader programs may depend on non-orthogonal state. These flags are
152 * used to indicate that a shader's key depends on the state provided by
153 * a certain Gallium CSO. Changing any CSOs marked as a dependency will
154 * cause the driver to re-compute the shader key, possibly triggering a
158 IRIS_NOS_FRAMEBUFFER
,
159 IRIS_NOS_DEPTH_STENCIL_ALPHA
,
162 IRIS_NOS_LAST_VUE_MAP
,
167 struct iris_depth_stencil_alpha_state
;
170 * Cache IDs for the in-memory program cache (ice->shaders.cache).
172 enum iris_program_cache_id
{
173 IRIS_CACHE_VS
= MESA_SHADER_VERTEX
,
174 IRIS_CACHE_TCS
= MESA_SHADER_TESS_CTRL
,
175 IRIS_CACHE_TES
= MESA_SHADER_TESS_EVAL
,
176 IRIS_CACHE_GS
= MESA_SHADER_GEOMETRY
,
177 IRIS_CACHE_FS
= MESA_SHADER_FRAGMENT
,
178 IRIS_CACHE_CS
= MESA_SHADER_COMPUTE
,
184 * Defines for PIPE_CONTROL operations, which trigger cache flushes,
185 * synchronization, pipelined memory writes, and so on.
187 * The bits here are not the actual hardware values. The actual fields
188 * move between various generations, so we just have flags for each
189 * potential operation, and use genxml to encode the actual packet.
191 enum pipe_control_flags
193 PIPE_CONTROL_FLUSH_LLC
= (1 << 1),
194 PIPE_CONTROL_LRI_POST_SYNC_OP
= (1 << 2),
195 PIPE_CONTROL_STORE_DATA_INDEX
= (1 << 3),
196 PIPE_CONTROL_CS_STALL
= (1 << 4),
197 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
= (1 << 5),
198 PIPE_CONTROL_SYNC_GFDT
= (1 << 6),
199 PIPE_CONTROL_TLB_INVALIDATE
= (1 << 7),
200 PIPE_CONTROL_MEDIA_STATE_CLEAR
= (1 << 8),
201 PIPE_CONTROL_WRITE_IMMEDIATE
= (1 << 9),
202 PIPE_CONTROL_WRITE_DEPTH_COUNT
= (1 << 10),
203 PIPE_CONTROL_WRITE_TIMESTAMP
= (1 << 11),
204 PIPE_CONTROL_DEPTH_STALL
= (1 << 12),
205 PIPE_CONTROL_RENDER_TARGET_FLUSH
= (1 << 13),
206 PIPE_CONTROL_INSTRUCTION_INVALIDATE
= (1 << 14),
207 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
= (1 << 15),
208 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
= (1 << 16),
209 PIPE_CONTROL_NOTIFY_ENABLE
= (1 << 17),
210 PIPE_CONTROL_FLUSH_ENABLE
= (1 << 18),
211 PIPE_CONTROL_DATA_CACHE_FLUSH
= (1 << 19),
212 PIPE_CONTROL_VF_CACHE_INVALIDATE
= (1 << 20),
213 PIPE_CONTROL_CONST_CACHE_INVALIDATE
= (1 << 21),
214 PIPE_CONTROL_STATE_CACHE_INVALIDATE
= (1 << 22),
215 PIPE_CONTROL_STALL_AT_SCOREBOARD
= (1 << 23),
216 PIPE_CONTROL_DEPTH_CACHE_FLUSH
= (1 << 24),
219 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
220 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
221 PIPE_CONTROL_DATA_CACHE_FLUSH | \
222 PIPE_CONTROL_RENDER_TARGET_FLUSH)
224 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
225 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
226 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
227 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
228 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
229 PIPE_CONTROL_INSTRUCTION_INVALIDATE)
231 enum iris_predicate_state
{
232 /* The first two states are used if we can determine whether to draw
233 * without having to look at the values in the query object buffer. This
234 * will happen if there is no conditional render in progress, if the query
235 * object is already completed or if something else has already added
236 * samples to the preliminary result.
238 IRIS_PREDICATE_STATE_RENDER
,
239 IRIS_PREDICATE_STATE_DONT_RENDER
,
241 /* In this case whether to draw or not depends on the result of an
242 * MI_PREDICATE command so the predicate enable bit needs to be checked.
244 IRIS_PREDICATE_STATE_USE_BIT
,
250 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
251 * It primarily contains the NIR for the shader.
253 * Each API-facing shader can be compiled into multiple shader variants,
254 * based on non-orthogonal state dependencies, recorded in the shader key.
256 * See iris_compiled_shader, which represents a compiled shader variant.
258 struct iris_uncompiled_shader
{
259 struct nir_shader
*nir
;
261 struct pipe_stream_output_info stream_output
;
263 /* A SHA1 of the serialized NIR for the disk cache. */
264 unsigned char nir_sha1
[20];
268 /** Bitfield of (1 << IRIS_NOS_*) flags. */
271 /** Have any shader variants been compiled yet? */
274 /** Should we use ALT mode for math? Useful for ARB programs. */
277 /** Constant data scraped from the shader by nir_opt_large_constants */
278 struct pipe_resource
*const_data
;
280 /** Surface state for const_data */
281 struct iris_state_ref const_data_state
;
284 enum iris_surface_group
{
285 IRIS_SURFACE_GROUP_RENDER_TARGET
,
286 IRIS_SURFACE_GROUP_CS_WORK_GROUPS
,
287 IRIS_SURFACE_GROUP_TEXTURE
,
288 IRIS_SURFACE_GROUP_IMAGE
,
289 IRIS_SURFACE_GROUP_UBO
,
290 IRIS_SURFACE_GROUP_SSBO
,
292 IRIS_SURFACE_GROUP_COUNT
,
296 /* Invalid value for a binding table index. */
297 IRIS_SURFACE_NOT_USED
= 0xa0a0a0a0,
300 struct iris_binding_table
{
303 /** Number of surfaces in each group, before compacting. */
304 uint32_t sizes
[IRIS_SURFACE_GROUP_COUNT
];
306 /** Initial offset of each group. */
307 uint32_t offsets
[IRIS_SURFACE_GROUP_COUNT
];
309 /** Mask of surfaces used in each group. */
310 uint64_t used_mask
[IRIS_SURFACE_GROUP_COUNT
];
314 * A compiled shader variant, containing a pointer to the GPU assembly,
315 * as well as program data and other packets needed by state upload.
317 * There can be several iris_compiled_shader variants per API-level shader
318 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
320 struct iris_compiled_shader
{
321 /** Reference to the uploaded assembly. */
322 struct iris_state_ref assembly
;
324 /** Pointer to the assembly in the BO's map. */
327 /** The program data (owned by the program cache hash table) */
328 struct brw_stage_prog_data
*prog_data
;
330 /** A list of system values to be uploaded as uniforms. */
331 enum brw_param_builtin
*system_values
;
332 unsigned num_system_values
;
334 /** Number of constbufs expected by the shader. */
338 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
339 * (the VUE-based information for transform feedback outputs).
343 struct iris_binding_table bt
;
346 * Shader packets and other data derived from prog_data. These must be
347 * completely determined from prog_data.
349 uint8_t derived_data
[0];
353 * API context state that is replicated per shader stage.
355 struct iris_shader_state
{
356 /** Uniform Buffers */
357 struct pipe_shader_buffer constbuf
[PIPE_MAX_CONSTANT_BUFFERS
];
358 struct iris_state_ref constbuf_surf_state
[PIPE_MAX_CONSTANT_BUFFERS
];
360 bool sysvals_need_upload
;
362 /** Shader Storage Buffers */
363 struct pipe_shader_buffer ssbo
[PIPE_MAX_SHADER_BUFFERS
];
364 struct iris_state_ref ssbo_surf_state
[PIPE_MAX_SHADER_BUFFERS
];
366 /** Shader Storage Images (image load store) */
367 struct iris_image_view image
[PIPE_MAX_SHADER_IMAGES
];
369 struct iris_state_ref sampler_table
;
370 struct iris_sampler_state
*samplers
[IRIS_MAX_TEXTURE_SAMPLERS
];
371 struct iris_sampler_view
*textures
[IRIS_MAX_TEXTURE_SAMPLERS
];
373 /** Bitfield of which constant buffers are bound (non-null). */
374 uint32_t bound_cbufs
;
376 /** Bitfield of which image views are bound (non-null). */
377 uint32_t bound_image_views
;
379 /** Bitfield of which sampler views are bound (non-null). */
380 uint32_t bound_sampler_views
;
382 /** Bitfield of which shader storage buffers are bound (non-null). */
383 uint32_t bound_ssbos
;
385 /** Bitfield of which shader storage buffers are writable. */
386 uint32_t writable_ssbos
;
390 * Gallium CSO for stream output (transform feedback) targets.
392 struct iris_stream_output_target
{
393 struct pipe_stream_output_target base
;
395 /** Storage holding the offset where we're writing in the buffer */
396 struct iris_state_ref offset
;
398 /** Stride (bytes-per-vertex) during this transform feedback operation */
401 /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
406 * Virtual table for generation-specific (genxml) function calls.
409 void (*destroy_state
)(struct iris_context
*ice
);
410 void (*init_render_context
)(struct iris_screen
*screen
,
411 struct iris_batch
*batch
,
412 struct iris_vtable
*vtbl
,
413 struct pipe_debug_callback
*dbg
);
414 void (*init_compute_context
)(struct iris_screen
*screen
,
415 struct iris_batch
*batch
,
416 struct iris_vtable
*vtbl
,
417 struct pipe_debug_callback
*dbg
);
418 void (*upload_render_state
)(struct iris_context
*ice
,
419 struct iris_batch
*batch
,
420 const struct pipe_draw_info
*draw
);
421 void (*update_surface_base_address
)(struct iris_batch
*batch
,
422 struct iris_binder
*binder
);
423 void (*upload_compute_state
)(struct iris_context
*ice
,
424 struct iris_batch
*batch
,
425 const struct pipe_grid_info
*grid
);
426 void (*rebind_buffer
)(struct iris_context
*ice
,
427 struct iris_resource
*res
,
428 uint64_t old_address
);
429 void (*resolve_conditional_render
)(struct iris_context
*ice
);
430 void (*load_register_reg32
)(struct iris_batch
*batch
, uint32_t dst
,
432 void (*load_register_reg64
)(struct iris_batch
*batch
, uint32_t dst
,
434 void (*load_register_imm32
)(struct iris_batch
*batch
, uint32_t reg
,
436 void (*load_register_imm64
)(struct iris_batch
*batch
, uint32_t reg
,
438 void (*load_register_mem32
)(struct iris_batch
*batch
, uint32_t reg
,
439 struct iris_bo
*bo
, uint32_t offset
);
440 void (*load_register_mem64
)(struct iris_batch
*batch
, uint32_t reg
,
441 struct iris_bo
*bo
, uint32_t offset
);
442 void (*store_register_mem32
)(struct iris_batch
*batch
, uint32_t reg
,
443 struct iris_bo
*bo
, uint32_t offset
,
445 void (*store_register_mem64
)(struct iris_batch
*batch
, uint32_t reg
,
446 struct iris_bo
*bo
, uint32_t offset
,
448 void (*store_data_imm32
)(struct iris_batch
*batch
,
449 struct iris_bo
*bo
, uint32_t offset
,
451 void (*store_data_imm64
)(struct iris_batch
*batch
,
452 struct iris_bo
*bo
, uint32_t offset
,
454 void (*copy_mem_mem
)(struct iris_batch
*batch
,
455 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
456 struct iris_bo
*src_bo
, uint32_t src_offset
,
458 void (*emit_raw_pipe_control
)(struct iris_batch
*batch
,
459 const char *reason
, uint32_t flags
,
460 struct iris_bo
*bo
, uint32_t offset
,
463 void (*emit_mi_report_perf_count
)(struct iris_batch
*batch
,
465 uint32_t offset_in_bytes
,
468 unsigned (*derived_program_state_size
)(enum iris_program_cache_id id
);
469 void (*store_derived_program_state
)(struct iris_context
*ice
,
470 enum iris_program_cache_id cache_id
,
471 struct iris_compiled_shader
*shader
);
472 uint32_t *(*create_so_decl_list
)(const struct pipe_stream_output_info
*sol
,
473 const struct brw_vue_map
*vue_map
);
474 void (*populate_vs_key
)(const struct iris_context
*ice
,
475 const struct shader_info
*info
,
476 gl_shader_stage last_stage
,
477 struct brw_vs_prog_key
*key
);
478 void (*populate_tcs_key
)(const struct iris_context
*ice
,
479 struct brw_tcs_prog_key
*key
);
480 void (*populate_tes_key
)(const struct iris_context
*ice
,
481 const struct shader_info
*info
,
482 gl_shader_stage last_stage
,
483 struct brw_tes_prog_key
*key
);
484 void (*populate_gs_key
)(const struct iris_context
*ice
,
485 const struct shader_info
*info
,
486 gl_shader_stage last_stage
,
487 struct brw_gs_prog_key
*key
);
488 void (*populate_fs_key
)(const struct iris_context
*ice
,
489 const struct shader_info
*info
,
490 struct brw_wm_prog_key
*key
);
491 void (*populate_cs_key
)(const struct iris_context
*ice
,
492 struct brw_cs_prog_key
*key
);
493 uint32_t (*mocs
)(const struct iris_bo
*bo
);
494 void (*lost_genx_state
)(struct iris_context
*ice
, struct iris_batch
*batch
);
498 * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
500 * See iris_border_color.c for more information.
502 struct iris_border_color_pool
{
505 unsigned insert_point
;
507 /** Map from border colors to offsets in the buffer. */
508 struct hash_table
*ht
;
512 * The API context (derived from pipe_context).
514 * Most driver state is tracked here.
516 struct iris_context
{
517 struct pipe_context ctx
;
519 /** A debug callback for KHR_debug output. */
520 struct pipe_debug_callback dbg
;
522 /** A device reset status callback for notifying that the GPU is hosed. */
523 struct pipe_device_reset_callback reset
;
525 /** Slab allocator for iris_transfer_map objects. */
526 struct slab_child_pool transfer_pool
;
528 struct iris_vtable vtbl
;
530 struct blorp_context blorp
;
532 struct iris_batch batches
[IRIS_BATCH_COUNT
];
534 struct u_upload_mgr
*query_buffer_uploader
;
539 * Either the value of BaseVertex for indexed draw calls or the value
540 * of the argument <first> for non-indexed draw calls.
547 * Resource and offset that stores draw_parameters from the indirect
548 * buffer or to the buffer that stures the previous values for non
551 struct pipe_resource
*draw_params_res
;
552 uint32_t draw_params_offset
;
556 * The value of DrawID. This always comes in from it's own vertex
557 * buffer since it's not part of the indirect draw parameters.
562 * Stores if an indexed or non-indexed draw (~0/0). Useful to
563 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
569 * Resource and offset used for GL_ARB_shader_draw_parameters which
570 * contains parameters that are not present in the indirect buffer as
571 * drawid and is_indexed_draw. They will go in their own vertex element.
573 struct pipe_resource
*derived_draw_params_res
;
574 uint32_t derived_draw_params_offset
;
580 struct iris_uncompiled_shader
*uncompiled
[MESA_SHADER_STAGES
];
581 struct iris_compiled_shader
*prog
[MESA_SHADER_STAGES
];
582 struct brw_vue_map
*last_vue_map
;
584 struct u_upload_mgr
*uploader
;
585 struct hash_table
*cache
;
589 /** Is a GS or TES outputting points or lines? */
590 bool output_topology_is_points_or_lines
;
592 /* Track last VS URB entry size */
593 unsigned last_vs_entry_size
;
596 * Scratch buffers for various sizes and stages.
598 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
601 struct iris_bo
*scratch_bos
[1 << 4][MESA_SHADER_STAGES
];
605 struct iris_query
*query
;
609 struct gen_perf_context
*perf_ctx
;
613 uint64_t dirty_for_nos
[IRIS_NOS_COUNT
];
615 unsigned num_viewports
;
616 unsigned sample_mask
;
617 struct iris_blend_state
*cso_blend
;
618 struct iris_rasterizer_state
*cso_rast
;
619 struct iris_depth_stencil_alpha_state
*cso_zsa
;
620 struct iris_vertex_element_state
*cso_vertex_elements
;
621 struct pipe_blend_color blend_color
;
622 struct pipe_poly_stipple poly_stipple
;
623 struct pipe_viewport_state viewports
[IRIS_MAX_VIEWPORTS
];
624 struct pipe_scissor_state scissors
[IRIS_MAX_VIEWPORTS
];
625 struct pipe_stencil_ref stencil_ref
;
626 struct pipe_framebuffer_state framebuffer
;
627 struct pipe_clip_state clip_planes
;
629 float default_outer_level
[4];
630 float default_inner_level
[2];
632 /** Bitfield of which vertex buffers are bound (non-null). */
633 uint64_t bound_vertex_buffers
;
635 bool primitive_restart
;
637 enum pipe_prim_type prim_mode
:8;
638 bool prim_is_points_or_lines
;
639 uint8_t vertices_per_patch
;
641 bool window_space_position
;
643 /** The last compute grid size */
644 uint32_t last_grid
[3];
645 /** Reference to the BO containing the compute grid size */
646 struct iris_state_ref grid_size
;
647 /** Reference to the SURFACE_STATE for the compute grid resource */
648 struct iris_state_ref grid_surf_state
;
651 * Array of aux usages for drawing, altered to account for any
652 * self-dependencies from resources bound for sampling and rendering.
654 enum isl_aux_usage draw_aux_usage
[BRW_MAX_DRAW_BUFFERS
];
656 /** Bitfield of whether color blending is enabled for RT[i] */
657 uint8_t blend_enables
;
659 /** Are depth writes enabled? (Depth buffer may or may not exist.) */
660 bool depth_writes_enabled
;
662 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
663 bool stencil_writes_enabled
;
665 /** GenX-specific current state */
666 struct iris_genx_state
*genx
;
668 struct iris_shader_state shaders
[MESA_SHADER_STAGES
];
670 /** Do vertex shader uses shader draw parameters ? */
671 bool vs_uses_draw_params
;
672 bool vs_uses_derived_draw_params
;
673 bool vs_needs_sgvs_element
;
675 /** Do vertex shader uses edge flag ? */
676 bool vs_needs_edge_flag
;
678 /** Do any samplers need border color? One bit per shader stage. */
679 uint8_t need_border_colors
;
681 struct pipe_stream_output_target
*so_target
[PIPE_MAX_SO_BUFFERS
];
682 bool streamout_active
;
684 bool statistics_counters_enabled
;
686 /** Current conditional rendering mode */
687 enum iris_predicate_state predicate
;
690 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
691 * render context that needs to be uploaded to the compute context.
693 struct iris_bo
*compute_predicate
;
695 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
696 bool prims_generated_query_active
;
698 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
701 /** The SURFACE_STATE for a 1x1x1 null surface. */
702 struct iris_state_ref unbound_tex
;
704 /** The SURFACE_STATE for a framebuffer-sized null surface. */
705 struct iris_state_ref null_fb
;
707 struct u_upload_mgr
*surface_uploader
;
708 struct u_upload_mgr
*dynamic_uploader
;
710 struct iris_binder binder
;
712 struct iris_border_color_pool border_color_pool
;
714 /** The high 16-bits of the last VBO/index buffer addresses */
715 uint16_t last_vbo_high_bits
[33];
716 uint16_t last_index_bo_high_bits
;
719 * Resources containing streamed state which our render context
720 * currently points to. Used to re-add these to the validation
721 * list when we start a new batch and haven't resubmitted commands.
724 struct pipe_resource
*cc_vp
;
725 struct pipe_resource
*sf_cl_vp
;
726 struct pipe_resource
*color_calc
;
727 struct pipe_resource
*scissor
;
728 struct pipe_resource
*blend
;
729 struct pipe_resource
*index_buffer
;
730 struct pipe_resource
*cs_thread_ids
;
731 struct pipe_resource
*cs_desc
;
734 /** Records the size of variable-length state for INTEL_DEBUG=bat */
735 struct hash_table_u64
*sizes
;
739 #define perf_debug(dbg, ...) do { \
740 if (INTEL_DEBUG & DEBUG_PERF) \
741 dbg_printf(__VA_ARGS__); \
743 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
746 double get_time(void);
748 struct pipe_context
*
749 iris_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
);
751 void iris_lost_context_state(struct iris_batch
*batch
);
753 void iris_init_blit_functions(struct pipe_context
*ctx
);
754 void iris_init_clear_functions(struct pipe_context
*ctx
);
755 void iris_init_program_functions(struct pipe_context
*ctx
);
756 void iris_init_resource_functions(struct pipe_context
*ctx
);
757 void iris_update_compiled_shaders(struct iris_context
*ice
);
758 void iris_update_compiled_compute_shader(struct iris_context
*ice
);
759 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
764 void iris_blorp_surf_for_resource(struct iris_vtable
*vtbl
,
765 struct blorp_surf
*surf
,
766 struct pipe_resource
*p_res
,
767 enum isl_aux_usage aux_usage
,
769 bool is_render_target
);
770 void iris_copy_region(struct blorp_context
*blorp
,
771 struct iris_batch
*batch
,
772 struct pipe_resource
*dst
,
774 unsigned dstx
, unsigned dsty
, unsigned dstz
,
775 struct pipe_resource
*src
,
777 const struct pipe_box
*src_box
);
781 void iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
782 void iris_launch_grid(struct pipe_context
*, const struct pipe_grid_info
*);
784 /* iris_pipe_control.c */
786 void iris_emit_pipe_control_flush(struct iris_batch
*batch
,
787 const char *reason
, uint32_t flags
);
788 void iris_emit_pipe_control_write(struct iris_batch
*batch
,
789 const char *reason
, uint32_t flags
,
790 struct iris_bo
*bo
, uint32_t offset
,
792 void iris_emit_end_of_pipe_sync(struct iris_batch
*batch
,
793 const char *reason
, uint32_t flags
);
795 void iris_init_flush_functions(struct pipe_context
*ctx
);
797 /* iris_border_color.c */
799 void iris_init_border_color_pool(struct iris_context
*ice
);
800 void iris_destroy_border_color_pool(struct iris_context
*ice
);
801 void iris_border_color_pool_reserve(struct iris_context
*ice
, unsigned count
);
802 uint32_t iris_upload_border_color(struct iris_context
*ice
,
803 union pipe_color_union
*color
);
806 void iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
807 struct pipe_shader_buffer
*buf
,
808 struct iris_state_ref
*surf_state
,
810 const struct shader_info
*iris_get_shader_info(const struct iris_context
*ice
,
811 gl_shader_stage stage
);
812 struct iris_bo
*iris_get_scratch_space(struct iris_context
*ice
,
813 unsigned per_thread_scratch
,
814 gl_shader_stage stage
);
815 uint32_t iris_group_index_to_bti(const struct iris_binding_table
*bt
,
816 enum iris_surface_group group
,
818 uint32_t iris_bti_to_group_index(const struct iris_binding_table
*bt
,
819 enum iris_surface_group group
,
822 /* iris_disk_cache.c */
824 void iris_disk_cache_store(struct disk_cache
*cache
,
825 const struct iris_uncompiled_shader
*ish
,
826 const struct iris_compiled_shader
*shader
,
827 const void *prog_key
,
828 uint32_t prog_key_size
);
829 struct iris_compiled_shader
*
830 iris_disk_cache_retrieve(struct iris_context
*ice
,
831 const struct iris_uncompiled_shader
*ish
,
832 const void *prog_key
,
833 uint32_t prog_key_size
);
835 /* iris_program_cache.c */
837 void iris_init_program_cache(struct iris_context
*ice
);
838 void iris_destroy_program_cache(struct iris_context
*ice
);
839 void iris_print_program_cache(struct iris_context
*ice
);
840 struct iris_compiled_shader
*iris_find_cached_shader(struct iris_context
*ice
,
841 enum iris_program_cache_id
,
844 struct iris_compiled_shader
*iris_upload_shader(struct iris_context
*ice
,
845 enum iris_program_cache_id
,
848 const void *assembly
,
849 struct brw_stage_prog_data
*,
851 enum brw_param_builtin
*sysv
,
852 unsigned num_system_values
,
854 const struct iris_binding_table
*bt
);
855 const void *iris_find_previous_compile(const struct iris_context
*ice
,
856 enum iris_program_cache_id cache_id
,
857 unsigned program_string_id
);
858 bool iris_blorp_lookup_shader(struct blorp_batch
*blorp_batch
,
861 uint32_t *kernel_out
,
862 void *prog_data_out
);
863 bool iris_blorp_upload_shader(struct blorp_batch
*blorp_batch
,
864 const void *key
, uint32_t key_size
,
865 const void *kernel
, uint32_t kernel_size
,
866 const struct brw_stage_prog_data
*prog_data
,
867 uint32_t prog_data_size
,
868 uint32_t *kernel_out
,
869 void *prog_data_out
);
873 void iris_predraw_resolve_inputs(struct iris_context
*ice
,
874 struct iris_batch
*batch
,
875 bool *draw_aux_buffer_disabled
,
876 gl_shader_stage stage
,
877 bool consider_framebuffer
);
878 void iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
879 struct iris_batch
*batch
,
880 bool *draw_aux_buffer_disabled
);
881 void iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
882 struct iris_batch
*batch
);
883 void iris_cache_sets_clear(struct iris_batch
*batch
);
884 void iris_flush_depth_and_render_caches(struct iris_batch
*batch
);
885 void iris_cache_flush_for_read(struct iris_batch
*batch
, struct iris_bo
*bo
);
886 void iris_cache_flush_for_render(struct iris_batch
*batch
,
888 enum isl_format format
,
889 enum isl_aux_usage aux_usage
);
890 void iris_render_cache_add_bo(struct iris_batch
*batch
,
892 enum isl_format format
,
893 enum isl_aux_usage aux_usage
);
894 void iris_cache_flush_for_depth(struct iris_batch
*batch
, struct iris_bo
*bo
);
895 void iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
);
896 int iris_get_driver_query_info(struct pipe_screen
*pscreen
, unsigned index
,
897 struct pipe_driver_query_info
*info
);
898 int iris_get_driver_query_group_info(struct pipe_screen
*pscreen
,
900 struct pipe_driver_query_group_info
*info
);
903 void gen9_toggle_preemption(struct iris_context
*ice
,
904 struct iris_batch
*batch
,
905 const struct pipe_draw_info
*draw
);
908 # include "iris_genx_protos.h"
910 # define genX(x) gen4_##x
911 # include "iris_genx_protos.h"
913 # define genX(x) gen5_##x
914 # include "iris_genx_protos.h"
916 # define genX(x) gen6_##x
917 # include "iris_genx_protos.h"
919 # define genX(x) gen7_##x
920 # include "iris_genx_protos.h"
922 # define genX(x) gen75_##x
923 # include "iris_genx_protos.h"
925 # define genX(x) gen8_##x
926 # include "iris_genx_protos.h"
928 # define genX(x) gen9_##x
929 # include "iris_genx_protos.h"
931 # define genX(x) gen10_##x
932 # include "iris_genx_protos.h"
934 # define genX(x) gen11_##x
935 # include "iris_genx_protos.h"