src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/slab.h"
  29 #include "util/u_debug.h"
  30 #include "intel/blorp/blorp.h"
  31 #include "intel/dev/gen_debug.h"
  32 #include "intel/common/gen_l3_config.h"
  33 #include "intel/compiler/brw_compiler.h"
  34 #include "iris_batch.h"
  35 #include "iris_binder.h"
  36 #include "iris_fence.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39
  40 struct iris_bo;
  41 struct iris_context;
  42 struct blorp_batch;
  43 struct blorp_params;
  44
  45 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  46 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  47 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  48 #define IRIS_MAX_ABOS 16
  49 #define IRIS_MAX_SSBOS 16
  50 #define IRIS_MAX_VIEWPORTS 16
  51 #define IRIS_MAX_CLIP_PLANES 8
  52
  53 enum iris_param_domain {
  54    BRW_PARAM_DOMAIN_BUILTIN = 0,
  55    BRW_PARAM_DOMAIN_IMAGE,
  56 };
  57
  58 enum {
  59    DRI_CONF_BO_REUSE_DISABLED,
  60    DRI_CONF_BO_REUSE_ALL
  61 };
  62
  63 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  64 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  65 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  66 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  67 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  68 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  69
  70 /**
  71  * Dirty flags.  When state changes, we flag some combination of these
  72  * to indicate that particular GPU commands need to be re-emitted.
  73  *
  74  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  75  * in rare cases they map to a group of related packets that need to be
  76  * emitted together.
  77  *
  78  * See iris_upload_render_state().
  79  */
  80 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  81 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  82 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  83 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  84 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  85 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  86 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  87 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  88 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  89 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  90 #define IRIS_DIRTY_SBE                      (1ull << 10)
  91 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  92 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  93 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  94 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  95 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  96 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  97 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  98 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  99 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
 100 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
 101 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
 102 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
 103 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
 104 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
 105 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
 106 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 107 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 108 #define IRIS_DIRTY_VS                       (1ull << 28)
 109 #define IRIS_DIRTY_TCS                      (1ull << 29)
 110 #define IRIS_DIRTY_TES                      (1ull << 30)
 111 #define IRIS_DIRTY_GS                       (1ull << 31)
 112 #define IRIS_DIRTY_FS                       (1ull << 32)
 113 #define IRIS_DIRTY_CS                       (1ull << 33)
 114 #define IRIS_DIRTY_URB                      (1ull << 34)
 115 #define IRIS_SHIFT_FOR_DIRTY_CONSTANTS      35
 116 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 117 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 118 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 119 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 120 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 121 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 122 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 123 #define IRIS_DIRTY_WM                       (1ull << 42)
 124 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 125 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 126 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 127 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 128 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 129 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 130 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 131 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 132 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 133 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 134 #define IRIS_DIRTY_VF                       (1ull << 53)
 135 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 136 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 137 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 138 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 139 #define IRIS_DIRTY_PMA_FIX                  (1ull << 58)
 140 #define IRIS_DIRTY_DEPTH_BOUNDS             (1ull << 59)
 141 #define IRIS_DIRTY_RENDER_BUFFER            (1ull << 60)
 142
 143 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 144                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 145                                     IRIS_DIRTY_UNCOMPILED_CS | \
 146                                     IRIS_DIRTY_CONSTANTS_CS | \
 147                                     IRIS_DIRTY_BINDINGS_CS | \
 148                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 149
 150 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 151
 152 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 153                                  IRIS_DIRTY_BINDINGS_TCS | \
 154                                  IRIS_DIRTY_BINDINGS_TES | \
 155                                  IRIS_DIRTY_BINDINGS_GS  | \
 156                                  IRIS_DIRTY_BINDINGS_FS  | \
 157                                  IRIS_DIRTY_BINDINGS_CS  | \
 158                                  IRIS_DIRTY_RENDER_BUFFER)
 159
 160 /**
 161  * Non-orthogonal state (NOS) dependency flags.
 162  *
 163  * Shader programs may depend on non-orthogonal state.  These flags are
 164  * used to indicate that a shader's key depends on the state provided by
 165  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 166  * cause the driver to re-compute the shader key, possibly triggering a
 167  * shader recompile.
 168  */
 169 enum iris_nos_dep {
 170    IRIS_NOS_FRAMEBUFFER,
 171    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 172    IRIS_NOS_RASTERIZER,
 173    IRIS_NOS_BLEND,
 174    IRIS_NOS_LAST_VUE_MAP,
 175
 176    IRIS_NOS_COUNT,
 177 };
 178
 179 /** @{
 180  *
 181  * Program cache keys for state based recompiles.
 182  */
 183
 184 struct iris_base_prog_key {
 185    unsigned program_string_id;
 186 };
 187
 188 struct iris_vue_prog_key {
 189    struct iris_base_prog_key base;
 190
 191    unsigned nr_userclip_plane_consts:4;
 192 };
 193
 194 struct iris_vs_prog_key {
 195    struct iris_vue_prog_key vue;
 196 };
 197
 198 struct iris_tcs_prog_key {
 199    struct iris_vue_prog_key vue;
 200
 201    uint16_t tes_primitive_mode;
 202
 203    uint8_t input_vertices;
 204
 205    bool quads_workaround;
 206
 207    /** A bitfield of per-patch outputs written. */
 208    uint32_t patch_outputs_written;
 209
 210    /** A bitfield of per-vertex outputs written. */
 211    uint64_t outputs_written;
 212 };
 213
 214 struct iris_tes_prog_key {
 215    struct iris_vue_prog_key vue;
 216
 217    /** A bitfield of per-patch inputs read. */
 218    uint32_t patch_inputs_read;
 219
 220    /** A bitfield of per-vertex inputs read. */
 221    uint64_t inputs_read;
 222 };
 223
 224 struct iris_gs_prog_key {
 225    struct iris_vue_prog_key vue;
 226 };
 227
 228 struct iris_fs_prog_key {
 229    struct iris_base_prog_key base;
 230
 231    unsigned nr_color_regions:5;
 232    bool flat_shade:1;
 233    bool alpha_test_replicate_alpha:1;
 234    bool alpha_to_coverage:1;
 235    bool clamp_fragment_color:1;
 236    bool persample_interp:1;
 237    bool multisample_fbo:1;
 238    bool force_dual_color_blend:1;
 239    bool coherent_fb_fetch:1;
 240
 241    uint8_t color_outputs_valid;
 242    uint64_t input_slots_valid;
 243 };
 244
 245 struct iris_cs_prog_key {
 246    struct iris_base_prog_key base;
 247 };
 248
 249 /** @} */
 250
 251 struct iris_depth_stencil_alpha_state;
 252
 253 /**
 254  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 255  */
 256 enum iris_program_cache_id {
 257    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 258    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 259    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 260    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 261    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 262    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 263    IRIS_CACHE_BLORP,
 264 };
 265
 266 /** @{
 267  *
 268  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 269  * synchronization, pipelined memory writes, and so on.
 270  *
 271  * The bits here are not the actual hardware values.  The actual fields
 272  * move between various generations, so we just have flags for each
 273  * potential operation, and use genxml to encode the actual packet.
 274  */
 275 enum pipe_control_flags
 276 {
 277    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 278    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 279    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 280    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 281    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 282    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 283    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 284    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 285    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 286    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 287    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 288    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 289    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 290    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 291    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 292    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 293    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 294    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 295    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 296    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 297    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 298    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 299    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 300    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 301    PIPE_CONTROL_TILE_CACHE_FLUSH                = (1 << 25),
 302    PIPE_CONTROL_FLUSH_HDC                       = (1 << 26),
 303 };
 304
 305 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 306    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 307     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 308     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 309
 310 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 311    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 312     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 313     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 314     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 315     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 316
 317 enum iris_predicate_state {
 318    /* The first two states are used if we can determine whether to draw
 319     * without having to look at the values in the query object buffer. This
 320     * will happen if there is no conditional render in progress, if the query
 321     * object is already completed or if something else has already added
 322     * samples to the preliminary result.
 323     */
 324    IRIS_PREDICATE_STATE_RENDER,
 325    IRIS_PREDICATE_STATE_DONT_RENDER,
 326
 327    /* In this case whether to draw or not depends on the result of an
 328     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 329     */
 330    IRIS_PREDICATE_STATE_USE_BIT,
 331 };
 332
 333 /** @} */
 334
 335 /**
 336  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 337  * It primarily contains the NIR for the shader.
 338  *
 339  * Each API-facing shader can be compiled into multiple shader variants,
 340  * based on non-orthogonal state dependencies, recorded in the shader key.
 341  *
 342  * See iris_compiled_shader, which represents a compiled shader variant.
 343  */
 344 struct iris_uncompiled_shader {
 345    struct nir_shader *nir;
 346
 347    struct pipe_stream_output_info stream_output;
 348
 349    /* A SHA1 of the serialized NIR for the disk cache. */
 350    unsigned char nir_sha1[20];
 351
 352    unsigned program_id;
 353
 354    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 355    unsigned nos;
 356
 357    /** Have any shader variants been compiled yet? */
 358    bool compiled_once;
 359
 360    /** Should we use ALT mode for math?  Useful for ARB programs. */
 361    bool use_alt_mode;
 362
 363    bool needs_edge_flag;
 364
 365    /* Whether shader uses atomic operations. */
 366    bool uses_atomic_load_store;
 367
 368    /** Constant data scraped from the shader by nir_opt_large_constants */
 369    struct pipe_resource *const_data;
 370
 371    /** Surface state for const_data */
 372    struct iris_state_ref const_data_state;
 373 };
 374
 375 enum iris_surface_group {
 376    IRIS_SURFACE_GROUP_RENDER_TARGET,
 377    IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
 378    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 379    IRIS_SURFACE_GROUP_TEXTURE,
 380    IRIS_SURFACE_GROUP_IMAGE,
 381    IRIS_SURFACE_GROUP_UBO,
 382    IRIS_SURFACE_GROUP_SSBO,
 383
 384    IRIS_SURFACE_GROUP_COUNT,
 385 };
 386
 387 enum {
 388    /* Invalid value for a binding table index. */
 389    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 390 };
 391
 392 struct iris_binding_table {
 393    uint32_t size_bytes;
 394
 395    /** Number of surfaces in each group, before compacting. */
 396    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 397
 398    /** Initial offset of each group. */
 399    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 400
 401    /** Mask of surfaces used in each group. */
 402    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 403 };
 404
 405 /**
 406  * A compiled shader variant, containing a pointer to the GPU assembly,
 407  * as well as program data and other packets needed by state upload.
 408  *
 409  * There can be several iris_compiled_shader variants per API-level shader
 410  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 411  */
 412 struct iris_compiled_shader {
 413    /** Reference to the uploaded assembly. */
 414    struct iris_state_ref assembly;
 415
 416    /** Pointer to the assembly in the BO's map. */
 417    void *map;
 418
 419    /** The program data (owned by the program cache hash table) */
 420    struct brw_stage_prog_data *prog_data;
 421
 422    /** A list of system values to be uploaded as uniforms. */
 423    enum brw_param_builtin *system_values;
 424    unsigned num_system_values;
 425
 426    /** Number of constbufs expected by the shader. */
 427    unsigned num_cbufs;
 428
 429    /**
 430     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 431     * (the VUE-based information for transform feedback outputs).
 432     */
 433    uint32_t *streamout;
 434
 435    struct iris_binding_table bt;
 436
 437    /**
 438     * Shader packets and other data derived from prog_data.  These must be
 439     * completely determined from prog_data.
 440     */
 441    uint8_t derived_data[0];
 442 };
 443
 444 /**
 445  * API context state that is replicated per shader stage.
 446  */
 447 struct iris_shader_state {
 448    /** Uniform Buffers */
 449    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 450    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 451
 452    bool sysvals_need_upload;
 453
 454    /** Shader Storage Buffers */
 455    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 456    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 457
 458    /** Shader Storage Images (image load store) */
 459    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 460
 461    struct iris_state_ref sampler_table;
 462    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 463    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 464
 465    /** Bitfield of which constant buffers are bound (non-null). */
 466    uint32_t bound_cbufs;
 467
 468    /** Bitfield of which image views are bound (non-null). */
 469    uint32_t bound_image_views;
 470
 471    /** Bitfield of which sampler views are bound (non-null). */
 472    uint32_t bound_sampler_views;
 473
 474    /** Bitfield of which shader storage buffers are bound (non-null). */
 475    uint32_t bound_ssbos;
 476
 477    /** Bitfield of which shader storage buffers are writable. */
 478    uint32_t writable_ssbos;
 479 };
 480
 481 /**
 482  * Gallium CSO for stream output (transform feedback) targets.
 483  */
 484 struct iris_stream_output_target {
 485    struct pipe_stream_output_target base;
 486
 487    /** Storage holding the offset where we're writing in the buffer */
 488    struct iris_state_ref offset;
 489
 490    /** Stride (bytes-per-vertex) during this transform feedback operation */
 491    uint16_t stride;
 492
 493    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 494    bool zeroed;
 495 };
 496
 497 /**
 498  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 499  *
 500  * See iris_border_color.c for more information.
 501  */
 502 struct iris_border_color_pool {
 503    struct iris_bo *bo;
 504    void *map;
 505    unsigned insert_point;
 506
 507    /** Map from border colors to offsets in the buffer. */
 508    struct hash_table *ht;
 509 };
 510
 511 /**
 512  * The API context (derived from pipe_context).
 513  *
 514  * Most driver state is tracked here.
 515  */
 516 struct iris_context {
 517    struct pipe_context ctx;
 518
 519    /** A debug callback for KHR_debug output. */
 520    struct pipe_debug_callback dbg;
 521
 522    /** A device reset status callback for notifying that the GPU is hosed. */
 523    struct pipe_device_reset_callback reset;
 524
 525    /** Slab allocator for iris_transfer_map objects. */
 526    struct slab_child_pool transfer_pool;
 527
 528    struct blorp_context blorp;
 529
 530    struct iris_batch batches[IRIS_BATCH_COUNT];
 531
 532    struct u_upload_mgr *query_buffer_uploader;
 533
 534    struct {
 535       struct {
 536          /**
 537           * Either the value of BaseVertex for indexed draw calls or the value
 538           * of the argument <first> for non-indexed draw calls.
 539           */
 540          int firstvertex;
 541          int baseinstance;
 542       } params;
 543
 544       /**
 545        * Are the above values the ones stored in the draw_params buffer?
 546        * If so, we can compare them against new values to see if anything
 547        * changed.  If not, we need to assume they changed.
 548        */
 549       bool params_valid;
 550
 551       /**
 552        * Resource and offset that stores draw_parameters from the indirect
 553        * buffer or to the buffer that stures the previous values for non
 554        * indirect draws.
 555        */
 556       struct iris_state_ref draw_params;
 557
 558       struct {
 559          /**
 560           * The value of DrawID. This always comes in from it's own vertex
 561           * buffer since it's not part of the indirect draw parameters.
 562           */
 563          int drawid;
 564
 565          /**
 566           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 567           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 568           */
 569          int is_indexed_draw;
 570       } derived_params;
 571
 572       /**
 573        * Resource and offset used for GL_ARB_shader_draw_parameters which
 574        * contains parameters that are not present in the indirect buffer as
 575        * drawid and is_indexed_draw. They will go in their own vertex element.
 576        */
 577       struct iris_state_ref derived_draw_params;
 578    } draw;
 579
 580    struct {
 581       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 582       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 583       struct brw_vue_map *last_vue_map;
 584
 585       struct u_upload_mgr *uploader;
 586       struct hash_table *cache;
 587
 588       /** Is a GS or TES outputting points or lines? */
 589       bool output_topology_is_points_or_lines;
 590
 591       /**
 592        * Scratch buffers for various sizes and stages.
 593        *
 594        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 595        * and shader stage.
 596        */
 597       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 598    } shaders;
 599
 600    struct {
 601       struct iris_query *query;
 602       bool condition;
 603    } condition;
 604
 605    struct gen_perf_context *perf_ctx;
 606
 607    /** Frame number for debug prints */
 608    uint32_t frame;
 609
 610    struct {
 611       uint64_t dirty;
 612       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 613
 614       unsigned num_viewports;
 615       unsigned sample_mask;
 616       struct iris_blend_state *cso_blend;
 617       struct iris_rasterizer_state *cso_rast;
 618       struct iris_depth_stencil_alpha_state *cso_zsa;
 619       struct iris_vertex_element_state *cso_vertex_elements;
 620       struct pipe_blend_color blend_color;
 621       struct pipe_poly_stipple poly_stipple;
 622       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 623       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 624       struct pipe_stencil_ref stencil_ref;
 625       struct pipe_framebuffer_state framebuffer;
 626       struct pipe_clip_state clip_planes;
 627
 628       float default_outer_level[4];
 629       float default_inner_level[2];
 630
 631       /** Bitfield of which vertex buffers are bound (non-null). */
 632       uint64_t bound_vertex_buffers;
 633
 634       bool primitive_restart;
 635       unsigned cut_index;
 636       enum pipe_prim_type prim_mode:8;
 637       bool prim_is_points_or_lines;
 638       uint8_t vertices_per_patch;
 639
 640       bool window_space_position;
 641
 642       /** The last compute grid size */
 643       uint32_t last_grid[3];
 644       /** Reference to the BO containing the compute grid size */
 645       struct iris_state_ref grid_size;
 646       /** Reference to the SURFACE_STATE for the compute grid resource */
 647       struct iris_state_ref grid_surf_state;
 648
 649       /**
 650        * Array of aux usages for drawing, altered to account for any
 651        * self-dependencies from resources bound for sampling and rendering.
 652        */
 653       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 654
 655       enum gen_urb_deref_block_size urb_deref_block_size;
 656
 657       /** Bitfield of whether color blending is enabled for RT[i] */
 658       uint8_t blend_enables;
 659
 660       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 661       bool depth_writes_enabled;
 662
 663       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 664       bool stencil_writes_enabled;
 665
 666       /** GenX-specific current state */
 667       struct iris_genx_state *genx;
 668
 669       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 670
 671       /** Do vertex shader uses shader draw parameters ? */
 672       bool vs_uses_draw_params;
 673       bool vs_uses_derived_draw_params;
 674       bool vs_needs_sgvs_element;
 675
 676       /** Do vertex shader uses edge flag ? */
 677       bool vs_needs_edge_flag;
 678
 679       /** Do any samplers need border color?  One bit per shader stage. */
 680       uint8_t need_border_colors;
 681
 682       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 683       bool streamout_active;
 684
 685       bool statistics_counters_enabled;
 686
 687       /** Current conditional rendering mode */
 688       enum iris_predicate_state predicate;
 689
 690       /**
 691        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 692        * render context that needs to be uploaded to the compute context.
 693        */
 694       struct iris_bo *compute_predicate;
 695
 696       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 697       bool prims_generated_query_active;
 698
 699       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 700       uint32_t *streamout;
 701
 702       /** The SURFACE_STATE for a 1x1x1 null surface. */
 703       struct iris_state_ref unbound_tex;
 704
 705       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 706       struct iris_state_ref null_fb;
 707
 708       struct u_upload_mgr *surface_uploader;
 709       struct u_upload_mgr *dynamic_uploader;
 710
 711       struct iris_binder binder;
 712
 713       struct iris_border_color_pool border_color_pool;
 714
 715       /** The high 16-bits of the last VBO/index buffer addresses */
 716       uint16_t last_vbo_high_bits[33];
 717       uint16_t last_index_bo_high_bits;
 718
 719       /**
 720        * Resources containing streamed state which our render context
 721        * currently points to.  Used to re-add these to the validation
 722        * list when we start a new batch and haven't resubmitted commands.
 723        */
 724       struct {
 725          struct pipe_resource *cc_vp;
 726          struct pipe_resource *sf_cl_vp;
 727          struct pipe_resource *color_calc;
 728          struct pipe_resource *scissor;
 729          struct pipe_resource *blend;
 730          struct pipe_resource *index_buffer;
 731          struct pipe_resource *cs_thread_ids;
 732          struct pipe_resource *cs_desc;
 733       } last_res;
 734
 735       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 736       struct hash_table_u64 *sizes;
 737
 738       /** Last rendering scale argument provided to genX(emit_hashing_mode). */
 739       unsigned current_hash_scale;
 740    } state;
 741 };
 742
 743 #define perf_debug(dbg, ...) do {                      \
 744    if (INTEL_DEBUG & DEBUG_PERF)                       \
 745       dbg_printf(__VA_ARGS__);                         \
 746    if (unlikely(dbg))                                  \
 747       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 748 } while(0)
 749
 750 double get_time(void);
 751
 752 struct pipe_context *
 753 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 754
 755 void iris_lost_context_state(struct iris_batch *batch);
 756
 757 void iris_init_blit_functions(struct pipe_context *ctx);
 758 void iris_init_clear_functions(struct pipe_context *ctx);
 759 void iris_init_program_functions(struct pipe_context *ctx);
 760 void iris_init_resource_functions(struct pipe_context *ctx);
 761 void iris_init_perfquery_functions(struct pipe_context *ctx);
 762 void iris_update_compiled_shaders(struct iris_context *ice);
 763 void iris_update_compiled_compute_shader(struct iris_context *ice);
 764 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 765                                     unsigned threads,
 766                                     uint32_t *dst);
 767
 768
 769 /* iris_blit.c */
 770 void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
 771                                   struct blorp_surf *surf,
 772                                   struct pipe_resource *p_res,
 773                                   enum isl_aux_usage aux_usage,
 774                                   unsigned level,
 775                                   bool is_render_target);
 776 void iris_copy_region(struct blorp_context *blorp,
 777                       struct iris_batch *batch,
 778                       struct pipe_resource *dst,
 779                       unsigned dst_level,
 780                       unsigned dstx, unsigned dsty, unsigned dstz,
 781                       struct pipe_resource *src,
 782                       unsigned src_level,
 783                       const struct pipe_box *src_box);
 784
 785 /* iris_draw.c */
 786
 787 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 788 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 789
 790 /* iris_pipe_control.c */
 791
 792 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 793                                   const char *reason, uint32_t flags);
 794 void iris_emit_pipe_control_write(struct iris_batch *batch,
 795                                   const char *reason, uint32_t flags,
 796                                   struct iris_bo *bo, uint32_t offset,
 797                                   uint64_t imm);
 798 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 799                                 const char *reason, uint32_t flags);
 800 void iris_flush_all_caches(struct iris_batch *batch);
 801
 802 #define iris_handle_always_flush_cache(batch) \
 803    if (unlikely(batch->screen->driconf.always_flush_cache)) \
 804       iris_flush_all_caches(batch);
 805
 806 void iris_init_flush_functions(struct pipe_context *ctx);
 807
 808 /* iris_border_color.c */
 809
 810 void iris_init_border_color_pool(struct iris_context *ice);
 811 void iris_destroy_border_color_pool(struct iris_context *ice);
 812 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 813 uint32_t iris_upload_border_color(struct iris_context *ice,
 814                                   union pipe_color_union *color);
 815
 816 /* iris_program.c */
 817 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 818                                      struct pipe_shader_buffer *buf,
 819                                      struct iris_state_ref *surf_state,
 820                                      bool ssbo);
 821 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 822                                                gl_shader_stage stage);
 823 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 824                                        unsigned per_thread_scratch,
 825                                        gl_shader_stage stage);
 826 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 827                                  enum iris_surface_group group,
 828                                  uint32_t index);
 829 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 830                                  enum iris_surface_group group,
 831                                  uint32_t bti);
 832
 833 /* iris_disk_cache.c */
 834
 835 void iris_disk_cache_store(struct disk_cache *cache,
 836                            const struct iris_uncompiled_shader *ish,
 837                            const struct iris_compiled_shader *shader,
 838                            const void *prog_key,
 839                            uint32_t prog_key_size);
 840 struct iris_compiled_shader *
 841 iris_disk_cache_retrieve(struct iris_context *ice,
 842                          const struct iris_uncompiled_shader *ish,
 843                          const void *prog_key,
 844                          uint32_t prog_key_size);
 845
 846 /* iris_program_cache.c */
 847
 848 void iris_init_program_cache(struct iris_context *ice);
 849 void iris_destroy_program_cache(struct iris_context *ice);
 850 void iris_print_program_cache(struct iris_context *ice);
 851 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 852                                                      enum iris_program_cache_id,
 853                                                      uint32_t key_size,
 854                                                      const void *key);
 855 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 856                                                 enum iris_program_cache_id,
 857                                                 uint32_t key_size,
 858                                                 const void *key,
 859                                                 const void *assembly,
 860                                                 struct brw_stage_prog_data *,
 861                                                 uint32_t *streamout,
 862                                                 enum brw_param_builtin *sysv,
 863                                                 unsigned num_system_values,
 864                                                 unsigned num_cbufs,
 865                                                 const struct iris_binding_table *bt);
 866 const void *iris_find_previous_compile(const struct iris_context *ice,
 867                                        enum iris_program_cache_id cache_id,
 868                                        unsigned program_string_id);
 869 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 870                               const void *key,
 871                               uint32_t key_size,
 872                               uint32_t *kernel_out,
 873                               void *prog_data_out);
 874 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
 875                               const void *key, uint32_t key_size,
 876                               const void *kernel, uint32_t kernel_size,
 877                               const struct brw_stage_prog_data *prog_data,
 878                               uint32_t prog_data_size,
 879                               uint32_t *kernel_out,
 880                               void *prog_data_out);
 881
 882 /* iris_resolve.c */
 883
 884 void iris_predraw_resolve_inputs(struct iris_context *ice,
 885                                  struct iris_batch *batch,
 886                                  bool *draw_aux_buffer_disabled,
 887                                  gl_shader_stage stage,
 888                                  bool consider_framebuffer);
 889 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 890                                       struct iris_batch *batch,
 891                                       bool *draw_aux_buffer_disabled);
 892 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 893                                            struct iris_batch *batch);
 894 void iris_cache_sets_clear(struct iris_batch *batch);
 895 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 896 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 897 void iris_cache_flush_for_render(struct iris_batch *batch,
 898                                  struct iris_bo *bo,
 899                                  enum isl_format format,
 900                                  enum isl_aux_usage aux_usage);
 901 void iris_render_cache_add_bo(struct iris_batch *batch,
 902                               struct iris_bo *bo,
 903                               enum isl_format format,
 904                               enum isl_aux_usage aux_usage);
 905 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 906 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 907 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 908                                struct pipe_driver_query_info *info);
 909 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
 910                                      unsigned index,
 911                                      struct pipe_driver_query_group_info *info);
 912
 913 /* iris_state.c */
 914 void gen9_toggle_preemption(struct iris_context *ice,
 915                             struct iris_batch *batch,
 916                             const struct pipe_draw_info *draw);
 917
 918
 919
 920 #ifdef genX
 921 #  include "iris_genx_protos.h"
 922 #else
 923 #  define genX(x) gen4_##x
 924 #  include "iris_genx_protos.h"
 925 #  undef genX
 926 #  define genX(x) gen5_##x
 927 #  include "iris_genx_protos.h"
 928 #  undef genX
 929 #  define genX(x) gen6_##x
 930 #  include "iris_genx_protos.h"
 931 #  undef genX
 932 #  define genX(x) gen7_##x
 933 #  include "iris_genx_protos.h"
 934 #  undef genX
 935 #  define genX(x) gen75_##x
 936 #  include "iris_genx_protos.h"
 937 #  undef genX
 938 #  define genX(x) gen8_##x
 939 #  include "iris_genx_protos.h"
 940 #  undef genX
 941 #  define genX(x) gen9_##x
 942 #  include "iris_genx_protos.h"
 943 #  undef genX
 944 #  define genX(x) gen10_##x
 945 #  include "iris_genx_protos.h"
 946 #  undef genX
 947 #  define genX(x) gen11_##x
 948 #  include "iris_genx_protos.h"
 949 #  undef genX
 950 #  define genX(x) gen12_##x
 951 #  include "iris_genx_protos.h"
 952 #  undef genX
 953 #endif
 954
 955 #endif