src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35
  36 struct iris_bo;
  37 struct iris_context;
  38 struct blorp_batch;
  39 struct blorp_params;
  40
  41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  44
  45 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  46 #define IRIS_MAX_VIEWPORTS 16
  47
  48 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  49 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  50 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  51 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  52 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  53 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  54 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  55 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  56 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  57 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  58 #define IRIS_DIRTY_SBE                      (1ull << 10)
  59 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  60 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  61 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  62 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  63 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  64 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  65 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  66 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  67 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  68 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  69 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  70 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  71 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  72 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  73 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  74 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  75 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  76 #define IRIS_DIRTY_VS                       (1ull << 28)
  77 #define IRIS_DIRTY_TCS                      (1ull << 29)
  78 #define IRIS_DIRTY_TES                      (1ull << 30)
  79 #define IRIS_DIRTY_GS                       (1ull << 31)
  80 #define IRIS_DIRTY_FS                       (1ull << 32)
  81 #define IRIS_DIRTY_CS                       (1ull << 33)
  82 #define IRIS_DIRTY_URB                      (1ull << 34)
  83 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  84 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  85 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  86 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  87 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  88 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
  89 #define IRIS_DIRTY_WM                       (1ull << 41)
  90 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 42)
  91 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 43)
  92 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 44)
  93 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 45)
  94 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 46)
  95 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 47)
  96
  97 struct iris_depth_stencil_alpha_state;
  98
  99 enum iris_program_cache_id {
 100    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 101    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 102    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 103    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 104    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 105    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 106    IRIS_CACHE_BLORP,
 107 };
 108
 109 /** @{
 110  *
 111  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
 112  * additional flushing control.
 113  *
 114  * The bits here are not the actual hardware values.  The actual values
 115  * shift around a bit per-generation, so we just have flags for each
 116  * potential operation, and use genxml to encode the actual packet.
 117  */
 118 enum pipe_control_flags
 119 {
 120    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 121    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 122    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 123    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 124    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 125    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 126    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 127    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 128    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 129    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 130    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 131    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 132    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 133    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 134    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 135    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 136    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 137    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 138    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 139    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 140    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 141    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 142    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 143    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 144 };
 145
 146 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 147    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 148     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 149     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 150
 151 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 152    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 153     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 154     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 155     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 156     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 157
 158 /** @} */
 159
 160 struct iris_compiled_shader {
 161    /** Reference to the uploaded assembly. */
 162    struct iris_state_ref assembly;
 163
 164    /** Pointer to the assembly in the BO's map. */
 165    void *map;
 166
 167    /** The program data (owned by the program cache hash table) */
 168    struct brw_stage_prog_data *prog_data;
 169
 170    /**
 171     * Shader packets and other data derived from prog_data.  These must be
 172     * completely determined from prog_data.
 173     */
 174    uint8_t derived_data[0];
 175 };
 176
 177 struct iris_const_buffer {
 178    /** The resource and offset for the actual constant data */
 179    struct iris_state_ref data;
 180
 181    /** The resource and offset for the SURFACE_STATE for pull access. */
 182    struct iris_state_ref surface_state;
 183 };
 184
 185 struct iris_shader_state {
 186    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 187 };
 188
 189 struct iris_vtable {
 190    void (*destroy_state)(struct iris_context *ice);
 191    void (*init_render_context)(struct iris_screen *screen,
 192                                struct iris_batch *batch,
 193                                struct iris_vtable *vtbl,
 194                                struct pipe_debug_callback *dbg);
 195    void (*upload_render_state)(struct iris_context *ice,
 196                                struct iris_batch *batch,
 197                                const struct pipe_draw_info *draw);
 198    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 199                                  struct iris_bo *bo, uint32_t offset,
 200                                  uint64_t imm);
 201
 202    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 203    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 204                                        enum iris_program_cache_id cache_id,
 205                                        struct iris_compiled_shader *shader);
 206    void (*populate_vs_key)(const struct iris_context *ice,
 207                            struct brw_vs_prog_key *key);
 208    void (*populate_tcs_key)(const struct iris_context *ice,
 209                             struct brw_tcs_prog_key *key);
 210    void (*populate_tes_key)(const struct iris_context *ice,
 211                             struct brw_tes_prog_key *key);
 212    void (*populate_gs_key)(const struct iris_context *ice,
 213                            struct brw_gs_prog_key *key);
 214    void (*populate_fs_key)(const struct iris_context *ice,
 215                            struct brw_wm_prog_key *key);
 216 };
 217
 218 struct iris_border_color_pool {
 219    struct iris_bo *bo;
 220    void *map;
 221    unsigned insert_point;
 222
 223    /** Map from border colors to offsets in the buffer. */
 224    struct hash_table *ht;
 225 };
 226
 227 struct iris_context {
 228    struct pipe_context ctx;
 229
 230    struct pipe_debug_callback dbg;
 231
 232    struct slab_child_pool transfer_pool;
 233
 234    struct iris_vtable vtbl;
 235
 236    struct {
 237       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 238       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 239       struct brw_vue_map *last_vue_map;
 240
 241       struct iris_shader_state state[MESA_SHADER_STAGES];
 242
 243       struct u_upload_mgr *uploader;
 244       struct hash_table *cache;
 245
 246       unsigned urb_size;
 247    } shaders;
 248
 249    struct blorp_context blorp;
 250
 251    /** The main batch for rendering */
 252    struct iris_batch render_batch;
 253
 254    struct {
 255       uint64_t dirty;
 256       unsigned num_viewports;
 257       unsigned sample_mask;
 258       struct iris_blend_state *cso_blend;
 259       struct iris_rasterizer_state *cso_rast;
 260       struct iris_depth_stencil_alpha_state *cso_zsa;
 261       struct iris_vertex_element_state *cso_vertex_elements;
 262       struct pipe_blend_color blend_color;
 263       struct pipe_poly_stipple poly_stipple;
 264       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 265       struct pipe_stencil_ref stencil_ref;
 266       struct pipe_framebuffer_state framebuffer;
 267
 268       struct iris_genx_state *genx;
 269
 270       struct iris_state_ref sampler_table[MESA_SHADER_STAGES];
 271       bool need_border_colors;
 272       struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 273       struct iris_sampler_view *textures[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 274       unsigned num_samplers[MESA_SHADER_STAGES];
 275       unsigned num_textures[MESA_SHADER_STAGES];
 276
 277       struct iris_state_ref unbound_tex;
 278
 279       struct u_upload_mgr *surface_uploader;
 280       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 281       // "I'm streaming this out at draw time and never want it again!"
 282       struct u_upload_mgr *dynamic_uploader;
 283
 284       struct iris_border_color_pool border_color_pool;
 285
 286       /**
 287        * Resources containing streamed state which our render context
 288        * currently points to.  Used to re-add these to the validation
 289        * list when we start a new batch and haven't resubmitted commands.
 290        */
 291       struct {
 292          struct pipe_resource *cc_vp;
 293          struct pipe_resource *sf_cl_vp;
 294          struct pipe_resource *color_calc;
 295          struct pipe_resource *scissor;
 296          struct pipe_resource *blend;
 297       } last_res;
 298    } state;
 299 };
 300
 301 #define perf_debug(dbg, ...) do {                      \
 302    if (INTEL_DEBUG & DEBUG_PERF)                       \
 303       dbg_printf(__VA_ARGS__);                         \
 304    if (unlikely(dbg))                                  \
 305       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 306 } while(0)
 307
 308 double get_time(void);
 309
 310 struct pipe_context *
 311 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 312
 313 void iris_init_blit_functions(struct pipe_context *ctx);
 314 void iris_init_clear_functions(struct pipe_context *ctx);
 315 void iris_init_program_functions(struct pipe_context *ctx);
 316 void iris_init_resource_functions(struct pipe_context *ctx);
 317 void iris_init_query_functions(struct pipe_context *ctx);
 318 void iris_update_compiled_shaders(struct iris_context *ice);
 319
 320 /* iris_blit.c */
 321 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 322                                   struct pipe_resource *p_res,
 323                                   enum isl_aux_usage aux_usage,
 324                                   bool is_render_target);
 325
 326 /* iris_draw.c */
 327
 328 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 329
 330 /* iris_pipe_control.c */
 331
 332 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 333                                   uint32_t flags);
 334 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 335                                   struct iris_bo *bo, uint32_t offset,
 336                                   uint64_t imm);
 337 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 338                                 uint32_t flags);
 339
 340 void iris_cache_sets_clear(struct iris_batch *batch);
 341 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 342 void iris_cache_flush_for_render(struct iris_batch *batch,
 343                                  struct iris_bo *bo,
 344                                  enum isl_format format,
 345                                  enum isl_aux_usage aux_usage);
 346 void iris_render_cache_add_bo(struct iris_batch *batch,
 347                               struct iris_bo *bo,
 348                               enum isl_format format,
 349                               enum isl_aux_usage aux_usage);
 350 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 351 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 352
 353 /* iris_blorp.c */
 354
 355 void gen9_init_blorp(struct iris_context *ice);
 356 void gen10_init_blorp(struct iris_context *ice);
 357
 358 /* iris_border_color.c */
 359
 360 void iris_init_border_color_pool(struct iris_context *ice);
 361 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 362 uint32_t iris_upload_border_color(struct iris_context *ice,
 363                                   union pipe_color_union *color);
 364
 365 /* iris_state.c */
 366
 367 void gen9_init_state(struct iris_context *ice);
 368 void gen10_init_state(struct iris_context *ice);
 369
 370 /* iris_program_cache.c */
 371
 372 void iris_init_program_cache(struct iris_context *ice);
 373 void iris_destroy_program_cache(struct iris_context *ice);
 374 void iris_print_program_cache(struct iris_context *ice);
 375 bool iris_bind_cached_shader(struct iris_context *ice,
 376                              enum iris_program_cache_id cache_id,
 377                              const void *key);
 378 void iris_upload_and_bind_shader(struct iris_context *ice,
 379                                  enum iris_program_cache_id cache_id,
 380                                  const void *key,
 381                                  const void *assembly,
 382                                  struct brw_stage_prog_data *prog_data);
 383 const void *iris_find_previous_compile(const struct iris_context *ice,
 384                                        enum iris_program_cache_id cache_id,
 385                                        unsigned program_string_id);
 386 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 387                               const void *key,
 388                               uint32_t key_size,
 389                               uint32_t *kernel_out,
 390                               void *prog_data_out);
 391 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 392                               const void *key, uint32_t key_size,
 393                               const void *kernel, uint32_t kernel_size,
 394                               const struct brw_stage_prog_data *prog_data,
 395                               uint32_t prog_data_size,
 396                               uint32_t *kernel_out,
 397                               void *prog_data_out);
 398
 399 #endif