2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_CONTEXT_H
24 #define IRIS_CONTEXT_H
26 #include "pipe/p_context.h"
27 #include "pipe/p_state.h"
28 #include "util/u_debug.h"
29 #include "intel/blorp/blorp.h"
30 #include "intel/common/gen_debug.h"
31 #include "intel/compiler/brw_compiler.h"
32 #include "iris_batch.h"
33 #include "iris_binder.h"
34 #include "iris_fence.h"
35 #include "iris_resource.h"
36 #include "iris_screen.h"
43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
46 #define IRIS_MAX_ABOS 16
47 #define IRIS_MAX_SSBOS 16
48 #define IRIS_MAX_VIEWPORTS 16
51 * Dirty flags. When state changes, we flag some combination of these
52 * to indicate that particular GPU commands need to be re-emitted.
54 * Each bit typically corresponds to a single 3DSTATE_* command packet, but
55 * in rare cases they map to a group of related packets that need to be
58 * See iris_upload_render_state().
60 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
61 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
62 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
63 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
64 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
65 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
66 #define IRIS_DIRTY_PS_BLEND (1ull << 6)
67 #define IRIS_DIRTY_BLEND_STATE (1ull << 7)
68 #define IRIS_DIRTY_RASTER (1ull << 8)
69 #define IRIS_DIRTY_CLIP (1ull << 9)
70 #define IRIS_DIRTY_SBE (1ull << 10)
71 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
72 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
73 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
74 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
75 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
76 #define IRIS_DIRTY_SAMPLER_STATES_VS (1ull << 16)
77 #define IRIS_DIRTY_SAMPLER_STATES_TCS (1ull << 17)
78 #define IRIS_DIRTY_SAMPLER_STATES_TES (1ull << 18)
79 #define IRIS_DIRTY_SAMPLER_STATES_GS (1ull << 19)
80 #define IRIS_DIRTY_SAMPLER_STATES_PS (1ull << 20)
81 #define IRIS_DIRTY_SAMPLER_STATES_CS (1ull << 21)
82 #define IRIS_DIRTY_UNCOMPILED_VS (1ull << 22)
83 #define IRIS_DIRTY_UNCOMPILED_TCS (1ull << 23)
84 #define IRIS_DIRTY_UNCOMPILED_TES (1ull << 24)
85 #define IRIS_DIRTY_UNCOMPILED_GS (1ull << 25)
86 #define IRIS_DIRTY_UNCOMPILED_FS (1ull << 26)
87 #define IRIS_DIRTY_UNCOMPILED_CS (1ull << 27)
88 #define IRIS_DIRTY_VS (1ull << 28)
89 #define IRIS_DIRTY_TCS (1ull << 29)
90 #define IRIS_DIRTY_TES (1ull << 30)
91 #define IRIS_DIRTY_GS (1ull << 31)
92 #define IRIS_DIRTY_FS (1ull << 32)
93 #define IRIS_DIRTY_CS (1ull << 33)
94 #define IRIS_DIRTY_URB (1ull << 34)
95 #define IRIS_DIRTY_CONSTANTS_VS (1ull << 35)
96 #define IRIS_DIRTY_CONSTANTS_TCS (1ull << 36)
97 #define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
98 #define IRIS_DIRTY_CONSTANTS_GS (1ull << 38)
99 #define IRIS_DIRTY_CONSTANTS_FS (1ull << 39)
100 #define IRIS_DIRTY_CONSTANTS_CS (1ull << 40)
101 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 41)
102 #define IRIS_DIRTY_WM (1ull << 42)
103 #define IRIS_DIRTY_BINDINGS_VS (1ull << 43)
104 #define IRIS_DIRTY_BINDINGS_TCS (1ull << 44)
105 #define IRIS_DIRTY_BINDINGS_TES (1ull << 45)
106 #define IRIS_DIRTY_BINDINGS_GS (1ull << 46)
107 #define IRIS_DIRTY_BINDINGS_FS (1ull << 47)
108 #define IRIS_DIRTY_BINDINGS_CS (1ull << 48)
109 #define IRIS_DIRTY_SO_BUFFERS (1ull << 49)
110 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 50)
111 #define IRIS_DIRTY_STREAMOUT (1ull << 51)
112 #define IRIS_DIRTY_VF_SGVS (1ull << 52)
113 #define IRIS_DIRTY_VF (1ull << 53)
114 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
116 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
117 IRIS_DIRTY_SAMPLER_STATES_CS | \
118 IRIS_DIRTY_UNCOMPILED_CS | \
119 IRIS_DIRTY_CONSTANTS_CS | \
120 IRIS_DIRTY_BINDINGS_CS)
122 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
124 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS | \
125 IRIS_DIRTY_BINDINGS_TCS | \
126 IRIS_DIRTY_BINDINGS_TES | \
127 IRIS_DIRTY_BINDINGS_GS | \
128 IRIS_DIRTY_BINDINGS_FS | \
129 IRIS_DIRTY_BINDINGS_CS)
132 * Non-orthogonal state (NOS) dependency flags.
134 * Shader programs may depend on non-orthogonal state. These flags are
135 * used to indicate that a shader's key depends on the state provided by
136 * a certain Gallium CSO. Changing any CSOs marked as a dependency will
137 * cause the driver to re-compute the shader key, possibly triggering a
141 IRIS_NOS_FRAMEBUFFER
,
142 IRIS_NOS_DEPTH_STENCIL_ALPHA
,
145 IRIS_NOS_LAST_VUE_MAP
,
150 struct iris_depth_stencil_alpha_state
;
153 * Cache IDs for the in-memory program cache (ice->shaders.cache).
155 enum iris_program_cache_id
{
156 IRIS_CACHE_VS
= MESA_SHADER_VERTEX
,
157 IRIS_CACHE_TCS
= MESA_SHADER_TESS_CTRL
,
158 IRIS_CACHE_TES
= MESA_SHADER_TESS_EVAL
,
159 IRIS_CACHE_GS
= MESA_SHADER_GEOMETRY
,
160 IRIS_CACHE_FS
= MESA_SHADER_FRAGMENT
,
161 IRIS_CACHE_CS
= MESA_SHADER_COMPUTE
,
167 * Defines for PIPE_CONTROL operations, which trigger cache flushes,
168 * synchronization, pipelined memory writes, and so on.
170 * The bits here are not the actual hardware values. The actual fields
171 * move between various generations, so we just have flags for each
172 * potential operation, and use genxml to encode the actual packet.
174 enum pipe_control_flags
176 PIPE_CONTROL_FLUSH_LLC
= (1 << 1),
177 PIPE_CONTROL_LRI_POST_SYNC_OP
= (1 << 2),
178 PIPE_CONTROL_STORE_DATA_INDEX
= (1 << 3),
179 PIPE_CONTROL_CS_STALL
= (1 << 4),
180 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
= (1 << 5),
181 PIPE_CONTROL_SYNC_GFDT
= (1 << 6),
182 PIPE_CONTROL_TLB_INVALIDATE
= (1 << 7),
183 PIPE_CONTROL_MEDIA_STATE_CLEAR
= (1 << 8),
184 PIPE_CONTROL_WRITE_IMMEDIATE
= (1 << 9),
185 PIPE_CONTROL_WRITE_DEPTH_COUNT
= (1 << 10),
186 PIPE_CONTROL_WRITE_TIMESTAMP
= (1 << 11),
187 PIPE_CONTROL_DEPTH_STALL
= (1 << 12),
188 PIPE_CONTROL_RENDER_TARGET_FLUSH
= (1 << 13),
189 PIPE_CONTROL_INSTRUCTION_INVALIDATE
= (1 << 14),
190 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
= (1 << 15),
191 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
= (1 << 16),
192 PIPE_CONTROL_NOTIFY_ENABLE
= (1 << 17),
193 PIPE_CONTROL_FLUSH_ENABLE
= (1 << 18),
194 PIPE_CONTROL_DATA_CACHE_FLUSH
= (1 << 19),
195 PIPE_CONTROL_VF_CACHE_INVALIDATE
= (1 << 20),
196 PIPE_CONTROL_CONST_CACHE_INVALIDATE
= (1 << 21),
197 PIPE_CONTROL_STATE_CACHE_INVALIDATE
= (1 << 22),
198 PIPE_CONTROL_STALL_AT_SCOREBOARD
= (1 << 23),
199 PIPE_CONTROL_DEPTH_CACHE_FLUSH
= (1 << 24),
202 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
203 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
204 PIPE_CONTROL_DATA_CACHE_FLUSH | \
205 PIPE_CONTROL_RENDER_TARGET_FLUSH)
207 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
208 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
209 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
210 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
211 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
212 PIPE_CONTROL_INSTRUCTION_INVALIDATE)
214 enum iris_predicate_state
{
215 /* The first two states are used if we can determine whether to draw
216 * without having to look at the values in the query object buffer. This
217 * will happen if there is no conditional render in progress, if the query
218 * object is already completed or if something else has already added
219 * samples to the preliminary result.
221 IRIS_PREDICATE_STATE_RENDER
,
222 IRIS_PREDICATE_STATE_DONT_RENDER
,
224 /* In this case whether to draw or not depends on the result of an
225 * MI_PREDICATE command so the predicate enable bit needs to be checked.
227 IRIS_PREDICATE_STATE_USE_BIT
,
233 * A compiled shader variant, containing a pointer to the GPU assembly,
234 * as well as program data and other packets needed by state upload.
236 * There can be several iris_compiled_shader variants per API-level shader
237 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
239 struct iris_compiled_shader
{
240 /** Reference to the uploaded assembly. */
241 struct iris_state_ref assembly
;
243 /** Pointer to the assembly in the BO's map. */
246 /** The program data (owned by the program cache hash table) */
247 struct brw_stage_prog_data
*prog_data
;
249 /** A list of system values to be uploaded as uniforms. */
250 enum brw_param_builtin
*system_values
;
251 unsigned num_system_values
;
254 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
255 * (the VUE-based information for transform feedback outputs).
260 * Shader packets and other data derived from prog_data. These must be
261 * completely determined from prog_data.
263 uint8_t derived_data
[0];
267 * Constant buffer (UBO) information. See iris_set_const_buffer().
269 struct iris_const_buffer
{
270 /** The resource and offset for the actual constant data */
271 struct iris_state_ref data
;
273 /** The resource and offset for the SURFACE_STATE for pull access. */
274 struct iris_state_ref surface_state
;
278 * API context state that is replicated per shader stage.
280 struct iris_shader_state
{
281 /** Uniform Buffers */
282 struct iris_const_buffer constbuf
[PIPE_MAX_CONSTANT_BUFFERS
];
284 struct pipe_constant_buffer cbuf0
;
285 bool cbuf0_needs_upload
;
287 /** Shader Storage Buffers */
288 struct pipe_resource
*ssbo
[PIPE_MAX_SHADER_BUFFERS
];
289 struct iris_state_ref ssbo_surface_state
[PIPE_MAX_SHADER_BUFFERS
];
291 /** Shader Storage Images (image load store) */
293 struct pipe_resource
*res
;
294 struct iris_state_ref surface_state
;
296 } image
[PIPE_MAX_SHADER_IMAGES
];
298 struct iris_state_ref sampler_table
;
299 struct iris_sampler_state
*samplers
[IRIS_MAX_TEXTURE_SAMPLERS
];
300 struct iris_sampler_view
*textures
[IRIS_MAX_TEXTURE_SAMPLERS
];
302 unsigned num_samplers
;
303 unsigned num_textures
;
307 * Virtual table for generation-specific (genxml) function calls.
310 void (*destroy_state
)(struct iris_context
*ice
);
311 void (*init_render_context
)(struct iris_screen
*screen
,
312 struct iris_batch
*batch
,
313 struct iris_vtable
*vtbl
,
314 struct pipe_debug_callback
*dbg
);
315 void (*init_compute_context
)(struct iris_screen
*screen
,
316 struct iris_batch
*batch
,
317 struct iris_vtable
*vtbl
,
318 struct pipe_debug_callback
*dbg
);
319 void (*upload_render_state
)(struct iris_context
*ice
,
320 struct iris_batch
*batch
,
321 const struct pipe_draw_info
*draw
);
322 void (*update_surface_base_address
)(struct iris_batch
*batch
,
323 struct iris_binder
*binder
);
324 void (*upload_compute_state
)(struct iris_context
*ice
,
325 struct iris_batch
*batch
,
326 const struct pipe_grid_info
*grid
);
327 void (*load_register_reg32
)(struct iris_batch
*batch
, uint32_t src
,
329 void (*load_register_reg64
)(struct iris_batch
*batch
, uint32_t src
,
331 void (*load_register_imm32
)(struct iris_batch
*batch
, uint32_t reg
,
333 void (*load_register_imm64
)(struct iris_batch
*batch
, uint32_t reg
,
335 void (*load_register_mem32
)(struct iris_batch
*batch
, uint32_t reg
,
336 struct iris_bo
*bo
, uint32_t offset
);
337 void (*load_register_mem64
)(struct iris_batch
*batch
, uint32_t reg
,
338 struct iris_bo
*bo
, uint32_t offset
);
339 void (*store_register_mem32
)(struct iris_batch
*batch
, uint32_t reg
,
340 struct iris_bo
*bo
, uint32_t offset
,
342 void (*store_register_mem64
)(struct iris_batch
*batch
, uint32_t reg
,
343 struct iris_bo
*bo
, uint32_t offset
,
345 void (*store_data_imm32
)(struct iris_batch
*batch
,
346 struct iris_bo
*bo
, uint32_t offset
,
348 void (*store_data_imm64
)(struct iris_batch
*batch
,
349 struct iris_bo
*bo
, uint32_t offset
,
351 void (*copy_mem_mem
)(struct iris_batch
*batch
,
352 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
353 struct iris_bo
*src_bo
, uint32_t src_offset
,
355 void (*emit_raw_pipe_control
)(struct iris_batch
*batch
, uint32_t flags
,
356 struct iris_bo
*bo
, uint32_t offset
,
359 unsigned (*derived_program_state_size
)(enum iris_program_cache_id id
);
360 void (*store_derived_program_state
)(struct iris_context
*ice
,
361 enum iris_program_cache_id cache_id
,
362 struct iris_compiled_shader
*shader
);
363 uint32_t *(*create_so_decl_list
)(const struct pipe_stream_output_info
*sol
,
364 const struct brw_vue_map
*vue_map
);
365 void (*populate_vs_key
)(const struct iris_context
*ice
,
366 const struct shader_info
*info
,
367 struct brw_vs_prog_key
*key
);
368 void (*populate_tcs_key
)(const struct iris_context
*ice
,
369 struct brw_tcs_prog_key
*key
);
370 void (*populate_tes_key
)(const struct iris_context
*ice
,
371 struct brw_tes_prog_key
*key
);
372 void (*populate_gs_key
)(const struct iris_context
*ice
,
373 struct brw_gs_prog_key
*key
);
374 void (*populate_fs_key
)(const struct iris_context
*ice
,
375 struct brw_wm_prog_key
*key
);
376 void (*populate_cs_key
)(const struct iris_context
*ice
,
377 struct brw_cs_prog_key
*key
);
381 * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
383 * See iris_border_color.c for more information.
385 struct iris_border_color_pool
{
388 unsigned insert_point
;
390 /** Map from border colors to offsets in the buffer. */
391 struct hash_table
*ht
;
395 * The API context (derived from pipe_context).
397 * Most driver state is tracked here.
399 struct iris_context
{
400 struct pipe_context ctx
;
402 /** A debug callback for KHR_debug output. */
403 struct pipe_debug_callback dbg
;
405 /** Slab allocator for iris_transfer_map objects. */
406 struct slab_child_pool transfer_pool
;
408 struct iris_vtable vtbl
;
410 struct blorp_context blorp
;
412 struct iris_batch batches
[IRIS_BATCH_COUNT
];
415 struct iris_uncompiled_shader
*uncompiled
[MESA_SHADER_STAGES
];
416 struct iris_compiled_shader
*prog
[MESA_SHADER_STAGES
];
417 struct brw_vue_map
*last_vue_map
;
419 struct u_upload_mgr
*uploader
;
420 struct hash_table
*cache
;
425 * Scratch buffers for various sizes and stages.
427 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
430 struct iris_bo
*scratch_bos
[1 << 4][MESA_SHADER_STAGES
];
435 uint64_t dirty_for_nos
[IRIS_NOS_COUNT
];
437 unsigned num_viewports
;
438 unsigned sample_mask
;
439 struct iris_blend_state
*cso_blend
;
440 struct iris_rasterizer_state
*cso_rast
;
441 struct iris_depth_stencil_alpha_state
*cso_zsa
;
442 struct iris_vertex_element_state
*cso_vertex_elements
;
443 struct pipe_blend_color blend_color
;
444 struct pipe_poly_stipple poly_stipple
;
445 struct pipe_viewport_state viewports
[IRIS_MAX_VIEWPORTS
];
446 struct pipe_scissor_state scissors
[IRIS_MAX_VIEWPORTS
];
447 struct pipe_stencil_ref stencil_ref
;
448 struct pipe_framebuffer_state framebuffer
;
449 struct pipe_clip_state clip_planes
;
451 float default_outer_level
[4];
452 float default_inner_level
[2];
454 bool primitive_restart
;
456 enum pipe_prim_type prim_mode
:8;
457 uint8_t vertices_per_patch
;
459 /** The last compute grid size */
460 uint32_t last_grid
[3];
461 /** Reference to the BO containing the compute grid size */
462 struct iris_state_ref grid_size
;
463 /** Reference to the SURFACE_STATE for the compute grid resource */
464 struct iris_state_ref grid_surf_state
;
466 /** Are depth writes enabled? (Depth buffer may or may not exist.) */
467 bool depth_writes_enabled
;
469 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
470 bool stencil_writes_enabled
;
472 /** GenX-specific current state */
473 struct iris_genx_state
*genx
;
475 struct iris_shader_state shaders
[MESA_SHADER_STAGES
];
477 /** Do any samplers (for any stage) need border color? */
478 bool need_border_colors
;
480 struct pipe_stream_output_target
*so_target
[PIPE_MAX_SO_BUFFERS
];
481 bool streamout_active
;
483 bool statistics_counters_enabled
;
485 /** Current conditional rendering mode */
486 enum iris_predicate_state predicate
;
489 * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
490 * render context that needs to be uploaded to the compute context.
492 struct iris_bo
*compute_predicate
;
494 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
495 bool prims_generated_query_active
;
497 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
500 /** The SURFACE_STATE for a 1x1x1 null surface. */
501 struct iris_state_ref unbound_tex
;
503 /** The SURFACE_STATE for a framebuffer-sized null surface. */
504 struct iris_state_ref null_fb
;
506 struct u_upload_mgr
*surface_uploader
;
507 // XXX: may want a separate uploader for "hey I made a CSO!" vs
508 // "I'm streaming this out at draw time and never want it again!"
509 struct u_upload_mgr
*dynamic_uploader
;
511 struct iris_binder binder
;
513 struct iris_border_color_pool border_color_pool
;
515 /** The high 16-bits of the last VBO/index buffer addresses */
516 uint16_t last_vbo_high_bits
[33];
517 uint16_t last_index_bo_high_bits
;
520 * Resources containing streamed state which our render context
521 * currently points to. Used to re-add these to the validation
522 * list when we start a new batch and haven't resubmitted commands.
525 struct pipe_resource
*cc_vp
;
526 struct pipe_resource
*sf_cl_vp
;
527 struct pipe_resource
*color_calc
;
528 struct pipe_resource
*scissor
;
529 struct pipe_resource
*blend
;
530 struct pipe_resource
*index_buffer
;
535 #define perf_debug(dbg, ...) do { \
536 if (INTEL_DEBUG & DEBUG_PERF) \
537 dbg_printf(__VA_ARGS__); \
539 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
542 double get_time(void);
544 struct pipe_context
*
545 iris_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
);
547 void iris_init_blit_functions(struct pipe_context
*ctx
);
548 void iris_init_clear_functions(struct pipe_context
*ctx
);
549 void iris_init_program_functions(struct pipe_context
*ctx
);
550 void iris_init_resource_functions(struct pipe_context
*ctx
);
551 void iris_init_query_functions(struct pipe_context
*ctx
);
552 void iris_update_compiled_shaders(struct iris_context
*ice
);
553 void iris_update_compiled_compute_shader(struct iris_context
*ice
);
554 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
559 void iris_blorp_surf_for_resource(struct blorp_surf
*surf
,
560 struct pipe_resource
*p_res
,
561 enum isl_aux_usage aux_usage
,
562 bool is_render_target
);
566 void iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
567 void iris_launch_grid(struct pipe_context
*, const struct pipe_grid_info
*);
569 /* iris_pipe_control.c */
571 void iris_emit_pipe_control_flush(struct iris_batch
*batch
,
573 void iris_emit_pipe_control_write(struct iris_batch
*batch
, uint32_t flags
,
574 struct iris_bo
*bo
, uint32_t offset
,
576 void iris_emit_end_of_pipe_sync(struct iris_batch
*batch
,
579 void iris_init_flush_functions(struct pipe_context
*ctx
);
583 void gen9_init_blorp(struct iris_context
*ice
);
584 void gen10_init_blorp(struct iris_context
*ice
);
585 void gen11_init_blorp(struct iris_context
*ice
);
587 /* iris_border_color.c */
589 void iris_init_border_color_pool(struct iris_context
*ice
);
590 void iris_border_color_pool_reserve(struct iris_context
*ice
, unsigned count
);
591 uint32_t iris_upload_border_color(struct iris_context
*ice
,
592 union pipe_color_union
*color
);
596 void gen9_init_state(struct iris_context
*ice
);
597 void gen10_init_state(struct iris_context
*ice
);
598 void gen11_init_state(struct iris_context
*ice
);
601 const struct shader_info
*iris_get_shader_info(const struct iris_context
*ice
,
602 gl_shader_stage stage
);
603 unsigned iris_get_shader_num_ubos(const struct iris_context
*ice
,
604 gl_shader_stage stage
);
605 uint32_t iris_get_scratch_space(struct iris_context
*ice
,
606 unsigned per_thread_scratch
,
607 gl_shader_stage stage
);
609 /* iris_program_cache.c */
611 void iris_init_program_cache(struct iris_context
*ice
);
612 void iris_destroy_program_cache(struct iris_context
*ice
);
613 void iris_print_program_cache(struct iris_context
*ice
);
614 struct iris_compiled_shader
*iris_find_cached_shader(struct iris_context
*ice
,
615 enum iris_program_cache_id
,
618 struct iris_compiled_shader
*iris_upload_shader(struct iris_context
*ice
,
619 enum iris_program_cache_id
,
622 const void *assembly
,
623 struct brw_stage_prog_data
*,
625 enum brw_param_builtin
*sysv
,
626 unsigned num_system_values
);
627 const void *iris_find_previous_compile(const struct iris_context
*ice
,
628 enum iris_program_cache_id cache_id
,
629 unsigned program_string_id
);
630 bool iris_blorp_lookup_shader(struct blorp_batch
*blorp_batch
,
633 uint32_t *kernel_out
,
634 void *prog_data_out
);
635 bool iris_blorp_upload_shader(struct blorp_batch
*blorp_batch
,
636 const void *key
, uint32_t key_size
,
637 const void *kernel
, uint32_t kernel_size
,
638 const struct brw_stage_prog_data
*prog_data
,
639 uint32_t prog_data_size
,
640 uint32_t *kernel_out
,
641 void *prog_data_out
);
645 uint64_t iris_timebase_scale(const struct gen_device_info
*devinfo
,
646 uint64_t gpu_timestamp
);
650 void iris_predraw_resolve_inputs(struct iris_context
*ice
,
651 struct iris_batch
*batch
);
652 void iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
653 struct iris_batch
*batch
);
654 void iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
655 struct iris_batch
*batch
);
656 void iris_cache_sets_clear(struct iris_batch
*batch
);
657 void iris_flush_depth_and_render_caches(struct iris_batch
*batch
);
658 void iris_cache_flush_for_read(struct iris_batch
*batch
, struct iris_bo
*bo
);
659 void iris_cache_flush_for_render(struct iris_batch
*batch
,
661 enum isl_format format
,
662 enum isl_aux_usage aux_usage
);
663 void iris_render_cache_add_bo(struct iris_batch
*batch
,
665 enum isl_format format
,
666 enum isl_aux_usage aux_usage
);
667 void iris_cache_flush_for_depth(struct iris_batch
*batch
, struct iris_bo
*bo
);
668 void iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
);