src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/slab.h"
  29 #include "util/u_debug.h"
  30 #include "intel/blorp/blorp.h"
  31 #include "intel/dev/gen_debug.h"
  32 #include "intel/common/gen_l3_config.h"
  33 #include "intel/compiler/brw_compiler.h"
  34 #include "iris_batch.h"
  35 #include "iris_binder.h"
  36 #include "iris_fence.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39
  40 struct iris_bo;
  41 struct iris_context;
  42 struct blorp_batch;
  43 struct blorp_params;
  44
  45 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  46 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  47 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  48 #define IRIS_MAX_ABOS 16
  49 #define IRIS_MAX_SSBOS 16
  50 #define IRIS_MAX_VIEWPORTS 16
  51 #define IRIS_MAX_CLIP_PLANES 8
  52
  53 enum iris_param_domain {
  54    BRW_PARAM_DOMAIN_BUILTIN = 0,
  55    BRW_PARAM_DOMAIN_IMAGE,
  56 };
  57
  58 enum {
  59    DRI_CONF_BO_REUSE_DISABLED,
  60    DRI_CONF_BO_REUSE_ALL
  61 };
  62
  63 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  64 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  65 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  66 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  67 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  68 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  69
  70 /**
  71  * Dirty flags.  When state changes, we flag some combination of these
  72  * to indicate that particular GPU commands need to be re-emitted.
  73  *
  74  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  75  * in rare cases they map to a group of related packets that need to be
  76  * emitted together.
  77  *
  78  * See iris_upload_render_state().
  79  */
  80 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  81 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  82 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  83 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  84 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  85 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  86 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  87 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  88 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  89 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  90 #define IRIS_DIRTY_SBE                      (1ull << 10)
  91 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  92 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  93 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  94 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  95 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  96 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  97 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  98 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  99 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
 100 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
 101 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
 102 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
 103 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
 104 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
 105 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
 106 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 107 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 108 #define IRIS_DIRTY_VS                       (1ull << 28)
 109 #define IRIS_DIRTY_TCS                      (1ull << 29)
 110 #define IRIS_DIRTY_TES                      (1ull << 30)
 111 #define IRIS_DIRTY_GS                       (1ull << 31)
 112 #define IRIS_DIRTY_FS                       (1ull << 32)
 113 #define IRIS_DIRTY_CS                       (1ull << 33)
 114 #define IRIS_DIRTY_URB                      (1ull << 34)
 115 #define IRIS_SHIFT_FOR_DIRTY_CONSTANTS      35
 116 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 117 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 118 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 119 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 120 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 121 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 122 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 123 #define IRIS_DIRTY_WM                       (1ull << 42)
 124 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 125 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 126 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 127 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 128 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 129 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 130 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 131 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 132 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 133 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 134 #define IRIS_DIRTY_VF                       (1ull << 53)
 135 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 136 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 137 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 138 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 139 #define IRIS_DIRTY_PMA_FIX                  (1ull << 58)
 140 #define IRIS_DIRTY_DEPTH_BOUNDS             (1ull << 59)
 141 #define IRIS_DIRTY_RENDER_BUFFER            (1ull << 60)
 142 #define IRIS_DIRTY_STENCIL_REF              (1ull << 61)
 143
 144 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 145                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 146                                     IRIS_DIRTY_UNCOMPILED_CS | \
 147                                     IRIS_DIRTY_CONSTANTS_CS | \
 148                                     IRIS_DIRTY_BINDINGS_CS | \
 149                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 150
 151 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 152
 153 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 154                                  IRIS_DIRTY_BINDINGS_TCS | \
 155                                  IRIS_DIRTY_BINDINGS_TES | \
 156                                  IRIS_DIRTY_BINDINGS_GS  | \
 157                                  IRIS_DIRTY_BINDINGS_FS  | \
 158                                  IRIS_DIRTY_BINDINGS_CS  | \
 159                                  IRIS_DIRTY_RENDER_BUFFER)
 160
 161 /**
 162  * Non-orthogonal state (NOS) dependency flags.
 163  *
 164  * Shader programs may depend on non-orthogonal state.  These flags are
 165  * used to indicate that a shader's key depends on the state provided by
 166  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 167  * cause the driver to re-compute the shader key, possibly triggering a
 168  * shader recompile.
 169  */
 170 enum iris_nos_dep {
 171    IRIS_NOS_FRAMEBUFFER,
 172    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 173    IRIS_NOS_RASTERIZER,
 174    IRIS_NOS_BLEND,
 175    IRIS_NOS_LAST_VUE_MAP,
 176
 177    IRIS_NOS_COUNT,
 178 };
 179
 180 /** @{
 181  *
 182  * Program cache keys for state based recompiles.
 183  */
 184
 185 struct iris_base_prog_key {
 186    unsigned program_string_id;
 187 };
 188
 189 struct iris_vue_prog_key {
 190    struct iris_base_prog_key base;
 191
 192    unsigned nr_userclip_plane_consts:4;
 193 };
 194
 195 struct iris_vs_prog_key {
 196    struct iris_vue_prog_key vue;
 197 };
 198
 199 struct iris_tcs_prog_key {
 200    struct iris_vue_prog_key vue;
 201
 202    uint16_t tes_primitive_mode;
 203
 204    uint8_t input_vertices;
 205
 206    bool quads_workaround;
 207
 208    /** A bitfield of per-patch outputs written. */
 209    uint32_t patch_outputs_written;
 210
 211    /** A bitfield of per-vertex outputs written. */
 212    uint64_t outputs_written;
 213 };
 214
 215 struct iris_tes_prog_key {
 216    struct iris_vue_prog_key vue;
 217
 218    /** A bitfield of per-patch inputs read. */
 219    uint32_t patch_inputs_read;
 220
 221    /** A bitfield of per-vertex inputs read. */
 222    uint64_t inputs_read;
 223 };
 224
 225 struct iris_gs_prog_key {
 226    struct iris_vue_prog_key vue;
 227 };
 228
 229 struct iris_fs_prog_key {
 230    struct iris_base_prog_key base;
 231
 232    unsigned nr_color_regions:5;
 233    bool flat_shade:1;
 234    bool alpha_test_replicate_alpha:1;
 235    bool alpha_to_coverage:1;
 236    bool clamp_fragment_color:1;
 237    bool persample_interp:1;
 238    bool multisample_fbo:1;
 239    bool force_dual_color_blend:1;
 240    bool coherent_fb_fetch:1;
 241
 242    uint8_t color_outputs_valid;
 243    uint64_t input_slots_valid;
 244 };
 245
 246 struct iris_cs_prog_key {
 247    struct iris_base_prog_key base;
 248 };
 249
 250 /** @} */
 251
 252 struct iris_depth_stencil_alpha_state;
 253
 254 /**
 255  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 256  */
 257 enum iris_program_cache_id {
 258    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 259    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 260    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 261    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 262    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 263    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 264    IRIS_CACHE_BLORP,
 265 };
 266
 267 /** @{
 268  *
 269  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 270  * synchronization, pipelined memory writes, and so on.
 271  *
 272  * The bits here are not the actual hardware values.  The actual fields
 273  * move between various generations, so we just have flags for each
 274  * potential operation, and use genxml to encode the actual packet.
 275  */
 276 enum pipe_control_flags
 277 {
 278    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 279    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 280    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 281    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 282    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 283    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 284    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 285    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 286    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 287    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 288    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 289    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 290    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 291    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 292    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 293    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 294    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 295    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 296    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 297    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 298    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 299    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 300    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 301    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 302    PIPE_CONTROL_TILE_CACHE_FLUSH                = (1 << 25),
 303    PIPE_CONTROL_FLUSH_HDC                       = (1 << 26),
 304 };
 305
 306 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 307    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 308     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 309     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 310
 311 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 312    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 313     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 314     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 315     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 316     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 317
 318 enum iris_predicate_state {
 319    /* The first two states are used if we can determine whether to draw
 320     * without having to look at the values in the query object buffer. This
 321     * will happen if there is no conditional render in progress, if the query
 322     * object is already completed or if something else has already added
 323     * samples to the preliminary result.
 324     */
 325    IRIS_PREDICATE_STATE_RENDER,
 326    IRIS_PREDICATE_STATE_DONT_RENDER,
 327
 328    /* In this case whether to draw or not depends on the result of an
 329     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 330     */
 331    IRIS_PREDICATE_STATE_USE_BIT,
 332 };
 333
 334 /** @} */
 335
 336 /**
 337  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 338  * It primarily contains the NIR for the shader.
 339  *
 340  * Each API-facing shader can be compiled into multiple shader variants,
 341  * based on non-orthogonal state dependencies, recorded in the shader key.
 342  *
 343  * See iris_compiled_shader, which represents a compiled shader variant.
 344  */
 345 struct iris_uncompiled_shader {
 346    struct nir_shader *nir;
 347
 348    struct pipe_stream_output_info stream_output;
 349
 350    /* A SHA1 of the serialized NIR for the disk cache. */
 351    unsigned char nir_sha1[20];
 352
 353    unsigned program_id;
 354
 355    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 356    unsigned nos;
 357
 358    /** Have any shader variants been compiled yet? */
 359    bool compiled_once;
 360
 361    /** Should we use ALT mode for math?  Useful for ARB programs. */
 362    bool use_alt_mode;
 363
 364    bool needs_edge_flag;
 365
 366    /* Whether shader uses atomic operations. */
 367    bool uses_atomic_load_store;
 368
 369    /** Constant data scraped from the shader by nir_opt_large_constants */
 370    struct pipe_resource *const_data;
 371
 372    /** Surface state for const_data */
 373    struct iris_state_ref const_data_state;
 374 };
 375
 376 enum iris_surface_group {
 377    IRIS_SURFACE_GROUP_RENDER_TARGET,
 378    IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
 379    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 380    IRIS_SURFACE_GROUP_TEXTURE,
 381    IRIS_SURFACE_GROUP_IMAGE,
 382    IRIS_SURFACE_GROUP_UBO,
 383    IRIS_SURFACE_GROUP_SSBO,
 384
 385    IRIS_SURFACE_GROUP_COUNT,
 386 };
 387
 388 enum {
 389    /* Invalid value for a binding table index. */
 390    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 391 };
 392
 393 struct iris_binding_table {
 394    uint32_t size_bytes;
 395
 396    /** Number of surfaces in each group, before compacting. */
 397    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 398
 399    /** Initial offset of each group. */
 400    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 401
 402    /** Mask of surfaces used in each group. */
 403    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 404 };
 405
 406 /**
 407  * A compiled shader variant, containing a pointer to the GPU assembly,
 408  * as well as program data and other packets needed by state upload.
 409  *
 410  * There can be several iris_compiled_shader variants per API-level shader
 411  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 412  */
 413 struct iris_compiled_shader {
 414    /** Reference to the uploaded assembly. */
 415    struct iris_state_ref assembly;
 416
 417    /** Pointer to the assembly in the BO's map. */
 418    void *map;
 419
 420    /** The program data (owned by the program cache hash table) */
 421    struct brw_stage_prog_data *prog_data;
 422
 423    /** A list of system values to be uploaded as uniforms. */
 424    enum brw_param_builtin *system_values;
 425    unsigned num_system_values;
 426
 427    /** Number of constbufs expected by the shader. */
 428    unsigned num_cbufs;
 429
 430    /**
 431     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 432     * (the VUE-based information for transform feedback outputs).
 433     */
 434    uint32_t *streamout;
 435
 436    struct iris_binding_table bt;
 437
 438    /**
 439     * Shader packets and other data derived from prog_data.  These must be
 440     * completely determined from prog_data.
 441     */
 442    uint8_t derived_data[0];
 443 };
 444
 445 /**
 446  * API context state that is replicated per shader stage.
 447  */
 448 struct iris_shader_state {
 449    /** Uniform Buffers */
 450    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 451    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 452
 453    bool sysvals_need_upload;
 454
 455    /** Shader Storage Buffers */
 456    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 457    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 458
 459    /** Shader Storage Images (image load store) */
 460    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 461
 462    struct iris_state_ref sampler_table;
 463    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 464    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 465
 466    /** Bitfield of which constant buffers are bound (non-null). */
 467    uint32_t bound_cbufs;
 468
 469    /** Bitfield of which image views are bound (non-null). */
 470    uint32_t bound_image_views;
 471
 472    /** Bitfield of which sampler views are bound (non-null). */
 473    uint32_t bound_sampler_views;
 474
 475    /** Bitfield of which shader storage buffers are bound (non-null). */
 476    uint32_t bound_ssbos;
 477
 478    /** Bitfield of which shader storage buffers are writable. */
 479    uint32_t writable_ssbos;
 480 };
 481
 482 /**
 483  * Gallium CSO for stream output (transform feedback) targets.
 484  */
 485 struct iris_stream_output_target {
 486    struct pipe_stream_output_target base;
 487
 488    /** Storage holding the offset where we're writing in the buffer */
 489    struct iris_state_ref offset;
 490
 491    /** Stride (bytes-per-vertex) during this transform feedback operation */
 492    uint16_t stride;
 493
 494    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 495    bool zeroed;
 496 };
 497
 498 /**
 499  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 500  *
 501  * See iris_border_color.c for more information.
 502  */
 503 struct iris_border_color_pool {
 504    struct iris_bo *bo;
 505    void *map;
 506    unsigned insert_point;
 507
 508    /** Map from border colors to offsets in the buffer. */
 509    struct hash_table *ht;
 510 };
 511
 512 /**
 513  * The API context (derived from pipe_context).
 514  *
 515  * Most driver state is tracked here.
 516  */
 517 struct iris_context {
 518    struct pipe_context ctx;
 519
 520    /** A debug callback for KHR_debug output. */
 521    struct pipe_debug_callback dbg;
 522
 523    /** A device reset status callback for notifying that the GPU is hosed. */
 524    struct pipe_device_reset_callback reset;
 525
 526    /** Slab allocator for iris_transfer_map objects. */
 527    struct slab_child_pool transfer_pool;
 528
 529    struct blorp_context blorp;
 530
 531    struct iris_batch batches[IRIS_BATCH_COUNT];
 532
 533    struct u_upload_mgr *query_buffer_uploader;
 534
 535    struct {
 536       struct {
 537          /**
 538           * Either the value of BaseVertex for indexed draw calls or the value
 539           * of the argument <first> for non-indexed draw calls.
 540           */
 541          int firstvertex;
 542          int baseinstance;
 543       } params;
 544
 545       /**
 546        * Are the above values the ones stored in the draw_params buffer?
 547        * If so, we can compare them against new values to see if anything
 548        * changed.  If not, we need to assume they changed.
 549        */
 550       bool params_valid;
 551
 552       /**
 553        * Resource and offset that stores draw_parameters from the indirect
 554        * buffer or to the buffer that stures the previous values for non
 555        * indirect draws.
 556        */
 557       struct iris_state_ref draw_params;
 558
 559       struct {
 560          /**
 561           * The value of DrawID. This always comes in from it's own vertex
 562           * buffer since it's not part of the indirect draw parameters.
 563           */
 564          int drawid;
 565
 566          /**
 567           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 568           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 569           */
 570          int is_indexed_draw;
 571       } derived_params;
 572
 573       /**
 574        * Resource and offset used for GL_ARB_shader_draw_parameters which
 575        * contains parameters that are not present in the indirect buffer as
 576        * drawid and is_indexed_draw. They will go in their own vertex element.
 577        */
 578       struct iris_state_ref derived_draw_params;
 579    } draw;
 580
 581    struct {
 582       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 583       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 584       struct brw_vue_map *last_vue_map;
 585
 586       struct u_upload_mgr *uploader;
 587       struct hash_table *cache;
 588
 589       /** Is a GS or TES outputting points or lines? */
 590       bool output_topology_is_points_or_lines;
 591
 592       /**
 593        * Scratch buffers for various sizes and stages.
 594        *
 595        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 596        * and shader stage.
 597        */
 598       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 599    } shaders;
 600
 601    struct {
 602       struct iris_query *query;
 603       bool condition;
 604    } condition;
 605
 606    struct gen_perf_context *perf_ctx;
 607
 608    /** Frame number for debug prints */
 609    uint32_t frame;
 610
 611    struct {
 612       uint64_t dirty;
 613       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 614
 615       unsigned num_viewports;
 616       unsigned sample_mask;
 617       struct iris_blend_state *cso_blend;
 618       struct iris_rasterizer_state *cso_rast;
 619       struct iris_depth_stencil_alpha_state *cso_zsa;
 620       struct iris_vertex_element_state *cso_vertex_elements;
 621       struct pipe_blend_color blend_color;
 622       struct pipe_poly_stipple poly_stipple;
 623       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 624       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 625       struct pipe_stencil_ref stencil_ref;
 626       struct pipe_framebuffer_state framebuffer;
 627       struct pipe_clip_state clip_planes;
 628
 629       float default_outer_level[4];
 630       float default_inner_level[2];
 631
 632       /** Bitfield of which vertex buffers are bound (non-null). */
 633       uint64_t bound_vertex_buffers;
 634
 635       bool primitive_restart;
 636       unsigned cut_index;
 637       enum pipe_prim_type prim_mode:8;
 638       bool prim_is_points_or_lines;
 639       uint8_t vertices_per_patch;
 640
 641       bool window_space_position;
 642
 643       /** The last compute group size */
 644       uint32_t last_block[3];
 645
 646       /** The last compute grid size */
 647       uint32_t last_grid[3];
 648       /** Reference to the BO containing the compute grid size */
 649       struct iris_state_ref grid_size;
 650       /** Reference to the SURFACE_STATE for the compute grid resource */
 651       struct iris_state_ref grid_surf_state;
 652
 653       /**
 654        * Array of aux usages for drawing, altered to account for any
 655        * self-dependencies from resources bound for sampling and rendering.
 656        */
 657       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 658
 659       enum gen_urb_deref_block_size urb_deref_block_size;
 660
 661       /** Bitfield of whether color blending is enabled for RT[i] */
 662       uint8_t blend_enables;
 663
 664       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 665       bool depth_writes_enabled;
 666
 667       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 668       bool stencil_writes_enabled;
 669
 670       /** GenX-specific current state */
 671       struct iris_genx_state *genx;
 672
 673       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 674
 675       /** Do vertex shader uses shader draw parameters ? */
 676       bool vs_uses_draw_params;
 677       bool vs_uses_derived_draw_params;
 678       bool vs_needs_sgvs_element;
 679
 680       /** Do vertex shader uses edge flag ? */
 681       bool vs_needs_edge_flag;
 682
 683       /** Do any samplers need border color?  One bit per shader stage. */
 684       uint8_t need_border_colors;
 685
 686       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 687       bool streamout_active;
 688
 689       bool statistics_counters_enabled;
 690
 691       /** Current conditional rendering mode */
 692       enum iris_predicate_state predicate;
 693
 694       /**
 695        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 696        * render context that needs to be uploaded to the compute context.
 697        */
 698       struct iris_bo *compute_predicate;
 699
 700       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 701       bool prims_generated_query_active;
 702
 703       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 704       uint32_t *streamout;
 705
 706       /** The SURFACE_STATE for a 1x1x1 null surface. */
 707       struct iris_state_ref unbound_tex;
 708
 709       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 710       struct iris_state_ref null_fb;
 711
 712       struct u_upload_mgr *surface_uploader;
 713       struct u_upload_mgr *dynamic_uploader;
 714
 715       struct iris_binder binder;
 716
 717       struct iris_border_color_pool border_color_pool;
 718
 719       /** The high 16-bits of the last VBO/index buffer addresses */
 720       uint16_t last_vbo_high_bits[33];
 721       uint16_t last_index_bo_high_bits;
 722
 723       /**
 724        * Resources containing streamed state which our render context
 725        * currently points to.  Used to re-add these to the validation
 726        * list when we start a new batch and haven't resubmitted commands.
 727        */
 728       struct {
 729          struct pipe_resource *cc_vp;
 730          struct pipe_resource *sf_cl_vp;
 731          struct pipe_resource *color_calc;
 732          struct pipe_resource *scissor;
 733          struct pipe_resource *blend;
 734          struct pipe_resource *index_buffer;
 735          struct pipe_resource *cs_thread_ids;
 736          struct pipe_resource *cs_desc;
 737       } last_res;
 738
 739       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 740       struct hash_table_u64 *sizes;
 741
 742       /** Last rendering scale argument provided to genX(emit_hashing_mode). */
 743       unsigned current_hash_scale;
 744    } state;
 745 };
 746
 747 #define perf_debug(dbg, ...) do {                      \
 748    if (INTEL_DEBUG & DEBUG_PERF)                       \
 749       dbg_printf(__VA_ARGS__);                         \
 750    if (unlikely(dbg))                                  \
 751       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 752 } while(0)
 753
 754 double get_time(void);
 755
 756 struct pipe_context *
 757 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 758
 759 void iris_lost_context_state(struct iris_batch *batch);
 760
 761 void iris_init_blit_functions(struct pipe_context *ctx);
 762 void iris_init_clear_functions(struct pipe_context *ctx);
 763 void iris_init_program_functions(struct pipe_context *ctx);
 764 void iris_init_resource_functions(struct pipe_context *ctx);
 765 void iris_init_perfquery_functions(struct pipe_context *ctx);
 766 void iris_update_compiled_shaders(struct iris_context *ice);
 767 void iris_update_compiled_compute_shader(struct iris_context *ice);
 768 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 769                                     unsigned threads,
 770                                     uint32_t *dst);
 771
 772
 773 /* iris_blit.c */
 774 void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
 775                                   struct blorp_surf *surf,
 776                                   struct pipe_resource *p_res,
 777                                   enum isl_aux_usage aux_usage,
 778                                   unsigned level,
 779                                   bool is_render_target);
 780 void iris_copy_region(struct blorp_context *blorp,
 781                       struct iris_batch *batch,
 782                       struct pipe_resource *dst,
 783                       unsigned dst_level,
 784                       unsigned dstx, unsigned dsty, unsigned dstz,
 785                       struct pipe_resource *src,
 786                       unsigned src_level,
 787                       const struct pipe_box *src_box);
 788
 789 /* iris_draw.c */
 790
 791 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 792 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 793
 794 /* iris_pipe_control.c */
 795
 796 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 797                                   const char *reason, uint32_t flags);
 798 void iris_emit_pipe_control_write(struct iris_batch *batch,
 799                                   const char *reason, uint32_t flags,
 800                                   struct iris_bo *bo, uint32_t offset,
 801                                   uint64_t imm);
 802 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 803                                 const char *reason, uint32_t flags);
 804 void iris_flush_all_caches(struct iris_batch *batch);
 805
 806 #define iris_handle_always_flush_cache(batch) \
 807    if (unlikely(batch->screen->driconf.always_flush_cache)) \
 808       iris_flush_all_caches(batch);
 809
 810 void iris_init_flush_functions(struct pipe_context *ctx);
 811
 812 /* iris_border_color.c */
 813
 814 void iris_init_border_color_pool(struct iris_context *ice);
 815 void iris_destroy_border_color_pool(struct iris_context *ice);
 816 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 817 uint32_t iris_upload_border_color(struct iris_context *ice,
 818                                   union pipe_color_union *color);
 819
 820 /* iris_program.c */
 821 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 822                                      struct pipe_shader_buffer *buf,
 823                                      struct iris_state_ref *surf_state,
 824                                      bool ssbo);
 825 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 826                                                gl_shader_stage stage);
 827 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 828                                        unsigned per_thread_scratch,
 829                                        gl_shader_stage stage);
 830 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 831                                  enum iris_surface_group group,
 832                                  uint32_t index);
 833 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 834                                  enum iris_surface_group group,
 835                                  uint32_t bti);
 836
 837 /* iris_disk_cache.c */
 838
 839 void iris_disk_cache_store(struct disk_cache *cache,
 840                            const struct iris_uncompiled_shader *ish,
 841                            const struct iris_compiled_shader *shader,
 842                            const void *prog_key,
 843                            uint32_t prog_key_size);
 844 struct iris_compiled_shader *
 845 iris_disk_cache_retrieve(struct iris_context *ice,
 846                          const struct iris_uncompiled_shader *ish,
 847                          const void *prog_key,
 848                          uint32_t prog_key_size);
 849
 850 /* iris_program_cache.c */
 851
 852 void iris_init_program_cache(struct iris_context *ice);
 853 void iris_destroy_program_cache(struct iris_context *ice);
 854 void iris_print_program_cache(struct iris_context *ice);
 855 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 856                                                      enum iris_program_cache_id,
 857                                                      uint32_t key_size,
 858                                                      const void *key);
 859 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 860                                                 enum iris_program_cache_id,
 861                                                 uint32_t key_size,
 862                                                 const void *key,
 863                                                 const void *assembly,
 864                                                 struct brw_stage_prog_data *,
 865                                                 uint32_t *streamout,
 866                                                 enum brw_param_builtin *sysv,
 867                                                 unsigned num_system_values,
 868                                                 unsigned num_cbufs,
 869                                                 const struct iris_binding_table *bt);
 870 const void *iris_find_previous_compile(const struct iris_context *ice,
 871                                        enum iris_program_cache_id cache_id,
 872                                        unsigned program_string_id);
 873 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 874                               const void *key,
 875                               uint32_t key_size,
 876                               uint32_t *kernel_out,
 877                               void *prog_data_out);
 878 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
 879                               const void *key, uint32_t key_size,
 880                               const void *kernel, uint32_t kernel_size,
 881                               const struct brw_stage_prog_data *prog_data,
 882                               uint32_t prog_data_size,
 883                               uint32_t *kernel_out,
 884                               void *prog_data_out);
 885
 886 /* iris_resolve.c */
 887
 888 void iris_predraw_resolve_inputs(struct iris_context *ice,
 889                                  struct iris_batch *batch,
 890                                  bool *draw_aux_buffer_disabled,
 891                                  gl_shader_stage stage,
 892                                  bool consider_framebuffer);
 893 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 894                                       struct iris_batch *batch,
 895                                       bool *draw_aux_buffer_disabled);
 896 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 897                                            struct iris_batch *batch);
 898 void iris_cache_sets_clear(struct iris_batch *batch);
 899 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 900 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 901 void iris_cache_flush_for_render(struct iris_batch *batch,
 902                                  struct iris_bo *bo,
 903                                  enum isl_format format,
 904                                  enum isl_aux_usage aux_usage);
 905 void iris_render_cache_add_bo(struct iris_batch *batch,
 906                               struct iris_bo *bo,
 907                               enum isl_format format,
 908                               enum isl_aux_usage aux_usage);
 909 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 910 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 911 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 912                                struct pipe_driver_query_info *info);
 913 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
 914                                      unsigned index,
 915                                      struct pipe_driver_query_group_info *info);
 916
 917 /* iris_state.c */
 918 void gen9_toggle_preemption(struct iris_context *ice,
 919                             struct iris_batch *batch,
 920                             const struct pipe_draw_info *draw);
 921
 922
 923
 924 #ifdef genX
 925 #  include "iris_genx_protos.h"
 926 #else
 927 #  define genX(x) gen4_##x
 928 #  include "iris_genx_protos.h"
 929 #  undef genX
 930 #  define genX(x) gen5_##x
 931 #  include "iris_genx_protos.h"
 932 #  undef genX
 933 #  define genX(x) gen6_##x
 934 #  include "iris_genx_protos.h"
 935 #  undef genX
 936 #  define genX(x) gen7_##x
 937 #  include "iris_genx_protos.h"
 938 #  undef genX
 939 #  define genX(x) gen75_##x
 940 #  include "iris_genx_protos.h"
 941 #  undef genX
 942 #  define genX(x) gen8_##x
 943 #  include "iris_genx_protos.h"
 944 #  undef genX
 945 #  define genX(x) gen9_##x
 946 #  include "iris_genx_protos.h"
 947 #  undef genX
 948 #  define genX(x) gen10_##x
 949 #  include "iris_genx_protos.h"
 950 #  undef genX
 951 #  define genX(x) gen11_##x
 952 #  include "iris_genx_protos.h"
 953 #  undef genX
 954 #  define genX(x) gen12_##x
 955 #  include "iris_genx_protos.h"
 956 #  undef genX
 957 #endif
 958
 959 #endif